/* eth.h -- Simulation of Ethernet MAC header
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/* eth.h -- Simulation of Ethernet MAC header
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Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
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Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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#ifndef ETH__H
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#ifndef ETH__H
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#define ETH__H
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#define ETH__H
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#if HAVE_NET_ETHERNET_H
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#if HAVE_NET_ETHERNET_H
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# include <net/ethernet.h>
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# include <net/ethernet.h>
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#elif defined(HAVE_SYS_ETHERNET_H)
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#elif defined(HAVE_SYS_ETHERNET_H)
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# include <sys/ethernet.h>
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# include <sys/ethernet.h>
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#else /* !HAVE_NET_ETHERNET_H && !HAVE_SYS_ETHERNET_H - */
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#else /* !HAVE_NET_ETHERNET_H && !HAVE_SYS_ETHERNET_H - */
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#include <sys/types.h>
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#include <sys/types.h>
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#endif
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#endif
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/* Address space required by one Ethernet MAC */
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/* Address space required by one Ethernet MAC */
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#define ETH_ADDR_SPACE 0x1000
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#define ETH_ADDR_SPACE 0x1000
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/* Relative Register Addresses */
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/* Relative Register Addresses */
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#define ETH_MODER (4 * 0x00)
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#define ETH_MODER (4 * 0x00)
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#define ETH_INT_SOURCE (4 * 0x01)
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#define ETH_INT_SOURCE (4 * 0x01)
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#define ETH_INT_MASK (4 * 0x02)
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#define ETH_INT_MASK (4 * 0x02)
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#define ETH_IPGT (4 * 0x03)
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#define ETH_IPGT (4 * 0x03)
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#define ETH_IPGR1 (4 * 0x04)
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#define ETH_IPGR1 (4 * 0x04)
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#define ETH_IPGR2 (4 * 0x05)
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#define ETH_IPGR2 (4 * 0x05)
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#define ETH_PACKETLEN (4 * 0x06)
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#define ETH_PACKETLEN (4 * 0x06)
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#define ETH_COLLCONF (4 * 0x07)
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#define ETH_COLLCONF (4 * 0x07)
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#define ETH_TX_BD_NUM (4 * 0x08)
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#define ETH_TX_BD_NUM (4 * 0x08)
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#define ETH_CTRLMODER (4 * 0x09)
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#define ETH_CTRLMODER (4 * 0x09)
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#define ETH_MIIMODER (4 * 0x0A)
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#define ETH_MIIMODER (4 * 0x0A)
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#define ETH_MIICOMMAND (4 * 0x0B)
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#define ETH_MIICOMMAND (4 * 0x0B)
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#define ETH_MIIADDRESS (4 * 0x0C)
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#define ETH_MIIADDRESS (4 * 0x0C)
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#define ETH_MIITX_DATA (4 * 0x0D)
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#define ETH_MIITX_DATA (4 * 0x0D)
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#define ETH_MIIRX_DATA (4 * 0x0E)
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#define ETH_MIIRX_DATA (4 * 0x0E)
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#define ETH_MIISTATUS (4 * 0x0F)
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#define ETH_MIISTATUS (4 * 0x0F)
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#define ETH_MAC_ADDR0 (4 * 0x10)
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#define ETH_MAC_ADDR0 (4 * 0x10)
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#define ETH_MAC_ADDR1 (4 * 0x11)
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#define ETH_MAC_ADDR1 (4 * 0x11)
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#define ETH_HASH0 (4 * 0x12)
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#define ETH_HASH0 (4 * 0x12)
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#define ETH_HASH1 (4 * 0x13)
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#define ETH_HASH1 (4 * 0x13)
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/* Where BD's are stored */
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/* Where BD's are stored */
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#define ETH_BD_BASE 0x400
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#define ETH_BD_BASE 0x400
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#define ETH_BD_COUNT 0x100
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#define ETH_BD_COUNT 0x100
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#define ETH_BD_SPACE (4 * ETH_BD_COUNT)
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#define ETH_BD_SPACE (4 * ETH_BD_COUNT)
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/* Where to point DMA to transmit/receive */
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/* Where to point DMA to transmit/receive */
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#define ETH_DMA_RX_TX 0x800
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#define ETH_DMA_RX_TX 0x800
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/* Field definitions for MODER */
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/* Field definitions for MODER */
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#define ETH_MODER_DMAEN_OFFSET 17
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#define ETH_MODER_DMAEN_OFFSET 17
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#define ETH_MODER_RECSMALL_OFFSET 16
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#define ETH_MODER_RECSMALL_OFFSET 16
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#define ETH_MODER_PAD_OFFSET 15
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#define ETH_MODER_PAD_OFFSET 15
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#define ETH_MODER_HUGEN_OFFSET 14
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#define ETH_MODER_HUGEN_OFFSET 14
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#define ETH_MODER_CRCEN_OFFSET 13
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#define ETH_MODER_CRCEN_OFFSET 13
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#define ETH_MODER_DLYCRCEN_OFFSET 12
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#define ETH_MODER_DLYCRCEN_OFFSET 12
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#define ETH_MODER_RST_OFFSET 11
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#define ETH_MODER_RST_OFFSET 11
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#define ETH_MODER_FULLD_OFFSET 10
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#define ETH_MODER_FULLD_OFFSET 10
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#define ETH_MODER_EXDFREN_OFFSET 9
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#define ETH_MODER_EXDFREN_OFFSET 9
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#define ETH_MODER_NOBCKOF_OFFSET 8
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#define ETH_MODER_NOBCKOF_OFFSET 8
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#define ETH_MODER_LOOPBCK_OFFSET 7
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#define ETH_MODER_LOOPBCK_OFFSET 7
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#define ETH_MODER_IFG_OFFSET 6
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#define ETH_MODER_IFG_OFFSET 6
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#define ETH_MODER_PRO_OFFSET 5
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#define ETH_MODER_PRO_OFFSET 5
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#define ETH_MODER_IAM_OFFSET 4
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#define ETH_MODER_IAM_OFFSET 4
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#define ETH_MODER_BRO_OFFSET 3
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#define ETH_MODER_BRO_OFFSET 3
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#define ETH_MODER_NOPRE_OFFSET 2
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#define ETH_MODER_NOPRE_OFFSET 2
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#define ETH_MODER_TXEN_OFFSET 1
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#define ETH_MODER_TXEN_OFFSET 1
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#define ETH_MODER_RXEN_OFFSET 0
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#define ETH_MODER_RXEN_OFFSET 0
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/* Field definitions for INT_SOURCE */
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/* Field definitions for INT_SOURCE */
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#define ETH_INT_SOURCE_RXC_OFFSET 6
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#define ETH_INT_SOURCE_RXC_OFFSET 6
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#define ETH_INT_SOURCE_TXC_OFFSET 5
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#define ETH_INT_SOURCE_TXC_OFFSET 5
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#define ETH_INT_SOURCE_BUSY_OFFSET 4
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#define ETH_INT_SOURCE_BUSY_OFFSET 4
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#define ETH_INT_SOURCE_RXE_OFFSET 3
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#define ETH_INT_SOURCE_RXE_OFFSET 3
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#define ETH_INT_SOURCE_RXB_OFFSET 2
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#define ETH_INT_SOURCE_RXB_OFFSET 2
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#define ETH_INT_SOURCE_TXE_OFFSET 1
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#define ETH_INT_SOURCE_TXE_OFFSET 1
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#define ETH_INT_SOURCE_TXB_OFFSET 0
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#define ETH_INT_SOURCE_TXB_OFFSET 0
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/* Field definitions for INT_MASK */
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/* Field definitions for INT_MASK */
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#define ETH_INT_MASK_RXC_M_OFFSET 6
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#define ETH_INT_MASK_RXC_M_OFFSET 6
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#define ETH_INT_MASK_TXC_M_OFFSET 5
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#define ETH_INT_MASK_TXC_M_OFFSET 5
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#define ETH_INT_MASK_BUSY_M_OFFSET 4
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#define ETH_INT_MASK_BUSY_M_OFFSET 4
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#define ETH_INT_MASK_RXE_M_OFFSET 3
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#define ETH_INT_MASK_RXE_M_OFFSET 3
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#define ETH_INT_MASK_RXB_M_OFFSET 2
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#define ETH_INT_MASK_RXB_M_OFFSET 2
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#define ETH_INT_MASK_TXE_M_OFFSET 1
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#define ETH_INT_MASK_TXE_M_OFFSET 1
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#define ETH_INT_MASK_TXB_M_OFFSET 0
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#define ETH_INT_MASK_TXB_M_OFFSET 0
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/* Field definitions for PACKETLEN */
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/* Field definitions for PACKETLEN */
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#define ETH_PACKETLEN_MINFL_OFFSET 16
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#define ETH_PACKETLEN_MINFL_OFFSET 16
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#define ETH_PACKETLEN_MINFL_WIDTH 16
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#define ETH_PACKETLEN_MINFL_WIDTH 16
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#define ETH_PACKETLEN_MAXFL_OFFSET 0
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#define ETH_PACKETLEN_MAXFL_OFFSET 0
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#define ETH_PACKETLEN_MAXFL_WIDTH 16
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#define ETH_PACKETLEN_MAXFL_WIDTH 16
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/* Field definitions for COLLCONF */
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/* Field definitions for COLLCONF */
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#define ETH_COLLCONF_MAXRET_OFFSET 16
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#define ETH_COLLCONF_MAXRET_OFFSET 16
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#define ETH_COLLCONF_MAXRET_WIDTH 4
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#define ETH_COLLCONF_MAXRET_WIDTH 4
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#define ETH_COLLCONF_COLLVALID_OFFSET 0
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#define ETH_COLLCONF_COLLVALID_OFFSET 0
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#define ETH_COLLCONF_COLLVALID_WIDTH 6
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#define ETH_COLLCONF_COLLVALID_WIDTH 6
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/* Field definitions for CTRLMODER */
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/* Field definitions for CTRLMODER */
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#define ETH_CMODER_TXFLOW_OFFSET 2
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#define ETH_CMODER_TXFLOW_OFFSET 2
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#define ETH_CMODER_RXFLOW_OFFSET 1
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#define ETH_CMODER_RXFLOW_OFFSET 1
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#define ETH_CMODER_PASSALL_OFFSET 0
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#define ETH_CMODER_PASSALL_OFFSET 0
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/* Field definitions for MIIMODER */
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/* Field definitions for MIIMODER */
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#define ETH_MIIMODER_NOPRE_OFFSET 8
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#define ETH_MIIMODER_NOPRE_OFFSET 8
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#define ETH_MIIMODER_CLKDIV_OFFSET 0
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#define ETH_MIIMODER_CLKDIV_OFFSET 0
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#define ETH_MIIMODER_CLKDIV_MASK 0xff
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#define ETH_MIIMODER_CLKDIV_MASK 0xff
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/* Field definitions for MIICOMMAND */
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/* Field definitions for MIICOMMAND */
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#define ETH_MIICOMM_WCDATA_OFFSET 2
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#define ETH_MIICOMM_WCDATA_OFFSET 2
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#define ETH_MIICOMM_RSTAT_OFFSET 1
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#define ETH_MIICOMM_RSTAT_OFFSET 1
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#define ETH_MIICOMM_SCANS_OFFSET 0
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#define ETH_MIICOMM_SCANS_OFFSET 0
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/* Field definitions for MIIADDRESS */
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/* Field definitions for MIIADDRESS */
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#define ETH_MIIADDR_RGAD_OFFSET 8
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#define ETH_MIIADDR_RGAD_OFFSET 8
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#define ETH_MIIADDR_RGAD_MASK 0x1f
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#define ETH_MIIADDR_RGAD_MASK 0x1f
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#define ETH_MIIADDR_FIAD_OFFSET 0
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#define ETH_MIIADDR_FIAD_OFFSET 0
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#define ETH_MIIADDR_FIAD_MASK 0x1f
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#define ETH_MIIADDR_FIAD_MASK 0x1f
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/* Field definitions for MIISTATUS */
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/* Field definitions for MIISTATUS */
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#define ETH_MIISTAT_NVALID_OFFSET 1
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#define ETH_MIISTAT_NVALID_OFFSET 1
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#define ETH_MIISTAT_BUSY_OFFSET 1
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#define ETH_MIISTAT_BUSY_OFFSET 1
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#define ETH_MIISTAT_FAIL_OFFSET 0
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#define ETH_MIISTAT_FAIL_OFFSET 0
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/* Field definitions for TX buffer descriptors */
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/* Field definitions for TX buffer descriptors */
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#define ETH_TX_BD_LENGTH_OFFSET 16
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#define ETH_TX_BD_LENGTH_OFFSET 16
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#define ETH_TX_BD_LENGTH_WIDTH 16
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#define ETH_TX_BD_LENGTH_WIDTH 16
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#define ETH_TX_BD_READY_OFFSET 15
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#define ETH_TX_BD_READY_OFFSET 15
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#define ETH_TX_BD_IRQ_OFFSET 14
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#define ETH_TX_BD_IRQ_OFFSET 14
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#define ETH_TX_BD_WRAP_OFFSET 13
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#define ETH_TX_BD_WRAP_OFFSET 13
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#define ETH_TX_BD_PAD_OFFSET 12
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#define ETH_TX_BD_PAD_OFFSET 12
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#define ETH_TX_BD_CRC_OFFSET 11
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#define ETH_TX_BD_CRC_OFFSET 11
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#define ETH_TX_BD_LAST_OFFSET 10
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#define ETH_TX_BD_LAST_OFFSET 10
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#define ETH_TX_BD_PAUSE_OFFSET 9
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#define ETH_TX_BD_PAUSE_OFFSET 9
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#define ETH_TX_BD_UNDERRUN_OFFSET 8
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#define ETH_TX_BD_UNDERRUN_OFFSET 8
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#define ETH_TX_BD_RETRY_OFFSET 4
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#define ETH_TX_BD_RETRY_OFFSET 4
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#define ETH_TX_BD_RETRY_WIDTH 4
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#define ETH_TX_BD_RETRY_WIDTH 4
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#define ETH_TX_BD_RETRANSMIT_OFFSET 3
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#define ETH_TX_BD_RETRANSMIT_OFFSET 3
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#define ETH_TX_BD_COLLISION_OFFSET 2
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#define ETH_TX_BD_COLLISION_OFFSET 2
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#define ETH_TX_BD_DEFER_OFFSET 1
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#define ETH_TX_BD_DEFER_OFFSET 1
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#define ETH_TX_BD_NO_CARRIER_OFFSET 0
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#define ETH_TX_BD_NO_CARRIER_OFFSET 0
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/* Field definitions for RX buffer descriptors */
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/* Field definitions for RX buffer descriptors */
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#define ETH_RX_BD_LENGTH_OFFSET 16
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#define ETH_RX_BD_LENGTH_OFFSET 16
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#define ETH_RX_BD_LENGTH_WIDTH 16
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#define ETH_RX_BD_LENGTH_WIDTH 16
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#define ETH_RX_BD_READY_OFFSET 15
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#define ETH_RX_BD_READY_OFFSET 15
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#define ETH_RX_BD_IRQ_OFFSET 14
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#define ETH_RX_BD_IRQ_OFFSET 14
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#define ETH_RX_BD_WRAP_OFFSET 13
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#define ETH_RX_BD_WRAP_OFFSET 13
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#define ETH_RX_BD_MISS_OFFSET 7
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#define ETH_RX_BD_MISS_OFFSET 7
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#define ETH_RX_BD_UVERRUN_OFFSET 6
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#define ETH_RX_BD_UVERRUN_OFFSET 6
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#define ETH_RX_BD_INVALID_OFFSET 5
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#define ETH_RX_BD_INVALID_OFFSET 5
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#define ETH_RX_BD_DRIBBLE_OFFSET 4
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#define ETH_RX_BD_DRIBBLE_OFFSET 4
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#define ETH_RX_BD_TOOBIG_OFFSET 3
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#define ETH_RX_BD_TOOBIG_OFFSET 3
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#define ETH_RX_BD_TOOSHORT_OFFSET 2
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#define ETH_RX_BD_TOOSHORT_OFFSET 2
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#define ETH_RX_BD_CRC_OFFSET 1
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#define ETH_RX_BD_CRC_OFFSET 1
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#define ETH_RX_BD_COLLISION_OFFSET 0
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#define ETH_RX_BD_COLLISION_OFFSET 0
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/*
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/*
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* Ethernet protocol definitions
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* Ethernet protocol definitions
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*/
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*/
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#ifdef HAVE_NET_ETHERNET_H
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#ifdef HAVE_NET_ETHERNET_H
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#elif defined(HAVE_SYS_ETHERNET_H)
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#elif defined(HAVE_SYS_ETHERNET_H)
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#ifndef ETHER_ADDR_LEN
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#ifndef ETHER_ADDR_LEN
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#define ETHER_ADDR_LEN ETHERADDRL
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#define ETHER_ADDR_LEN ETHERADDRL
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#endif
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#endif
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#ifndef ETHER_HDR_LEN
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#ifndef ETHER_HDR_LEN
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#define ETHER_HDR_LEN sizeof(struct ether_header)
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#define ETHER_HDR_LEN sizeof(struct ether_header)
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#endif
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#endif
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#else /* !HAVE_NET_ETHERNET_H && !HAVE_SYS_ETHERNET_H - */
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#else /* !HAVE_NET_ETHERNET_H && !HAVE_SYS_ETHERNET_H - */
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#ifdef __CYGWIN__
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#ifdef __CYGWIN__
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/* define some missing cygwin defines.
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/* define some missing cygwin defines.
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*/
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*/
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#define ETH_HLEN 14
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#define ETH_HLEN 14
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#endif /* __CYGWIN__ */
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#endif /* __CYGWIN__ */
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#define ETH_ALEN 6
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#define ETH_ALEN 6
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struct ether_addr
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struct ether_addr
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{
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{
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u_int8_t ether_addr_octet[ETH_ALEN];
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u_int8_t ether_addr_octet[ETH_ALEN];
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};
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};
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struct ether_header
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struct ether_header
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{
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{
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u_int8_t ether_dhost[ETH_ALEN]; /* destination eth addr */
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u_int8_t ether_dhost[ETH_ALEN]; /* destination eth addr */
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u_int8_t ether_shost[ETH_ALEN]; /* source ether addr */
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u_int8_t ether_shost[ETH_ALEN]; /* source ether addr */
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u_int16_t ether_type; /* packet type ID field */
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u_int16_t ether_type; /* packet type ID field */
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};
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};
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/* Ethernet protocol ID's */
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/* Ethernet protocol ID's */
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#define ETHERTYPE_PUP 0x0200 /* Xerox PUP */
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#define ETHERTYPE_PUP 0x0200 /* Xerox PUP */
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#define ETHERTYPE_IP 0x0800 /* IP */
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#define ETHERTYPE_IP 0x0800 /* IP */
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#define ETHERTYPE_ARP 0x0806 /* Address resolution */
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#define ETHERTYPE_ARP 0x0806 /* Address resolution */
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#define ETHERTYPE_REVARP 0x8035 /* Reverse ARP */
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#define ETHERTYPE_REVARP 0x8035 /* Reverse ARP */
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#define ETHER_ADDR_LEN ETH_ALEN /* size of ethernet addr */
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#define ETHER_ADDR_LEN ETH_ALEN /* size of ethernet addr */
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#define ETHER_TYPE_LEN 2 /* bytes in type field */
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#define ETHER_TYPE_LEN 2 /* bytes in type field */
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#define ETHER_CRC_LEN 4 /* bytes in CRC field */
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#define ETHER_CRC_LEN 4 /* bytes in CRC field */
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#define ETHER_HDR_LEN ETH_HLEN /* total octets in header */
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#define ETHER_HDR_LEN ETH_HLEN /* total octets in header */
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#define ETHER_MIN_LEN (ETH_ZLEN + ETHER_CRC_LEN) /* min packet length */
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#define ETHER_MIN_LEN (ETH_ZLEN + ETHER_CRC_LEN) /* min packet length */
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#define ETHER_MAX_LEN (ETH_FRAME_LEN + ETHER_CRC_LEN) /* max packet length */
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#define ETHER_MAX_LEN (ETH_FRAME_LEN + ETHER_CRC_LEN) /* max packet length */
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/* make sure ethenet length is valid */
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/* make sure ethenet length is valid */
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#define ETHER_IS_VALID_LEN(foo) \
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#define ETHER_IS_VALID_LEN(foo) \
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((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
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((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
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/*
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/*
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* The ETHERTYPE_NTRAILER packet types starting at ETHERTYPE_TRAIL have
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* The ETHERTYPE_NTRAILER packet types starting at ETHERTYPE_TRAIL have
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* (type-ETHERTYPE_TRAIL)*512 bytes of data followed
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* (type-ETHERTYPE_TRAIL)*512 bytes of data followed
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* by an ETHER type (as given above) and then the (variable-length) header.
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* by an ETHER type (as given above) and then the (variable-length) header.
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*/
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*/
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#define ETHERTYPE_TRAIL 0x1000 /* Trailer packet */
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#define ETHERTYPE_TRAIL 0x1000 /* Trailer packet */
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#define ETHERTYPE_NTRAILER 16
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#define ETHERTYPE_NTRAILER 16
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#define ETHERMTU ETH_DATA_LEN
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#define ETHERMTU ETH_DATA_LEN
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#define ETHERMIN (ETHER_MIN_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
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#define ETHERMIN (ETHER_MIN_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
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#endif /* HAVE_NET_ETHERNET_H */
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#endif /* HAVE_NET_ETHERNET_H */
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/*
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/*
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* Implementatino of Ethernet MAC Registers and State
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* Implementatino of Ethernet MAC Registers and State
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*/
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*/
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#define ETH_TXSTATE_IDLE 0
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#define ETH_TXSTATE_WAIT4BD 10
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#define ETH_TXSTATE_READFIFO 20
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#define ETH_TXSTATE_TRANSMIT 30
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#define ETH_RXSTATE_IDLE 0
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#define ETH_RXSTATE_WAIT4BD 10
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#define ETH_RXSTATE_RECV 20
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#define ETH_RXSTATE_WRITEFIFO 30
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#define ETH_RTX_FILE 0
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#define ETH_RTX_FILE 0
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#define ETH_RTX_TAP 1
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#define ETH_RTX_TAP 1
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#define ETH_RTX_VAPI 2
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#define ETH_RTX_VAPI 2
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#define ETH_MAXPL 0x10000
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#define ETH_MAXPL 0x10000
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enum
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enum
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{ ETH_VAPI_DATA = 0,
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{ ETH_VAPI_DATA = 0,
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ETH_VAPI_CTRL,
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ETH_VAPI_CTRL,
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ETH_NUM_VAPI_IDS
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ETH_NUM_VAPI_IDS
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};
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};
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/* Prototypes for external use */
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/* Prototypes for external use */
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extern void reg_ethernet_sec ();
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extern void reg_ethernet_sec ();
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/* Defines taken from linux-2.6.36/include/linux/mii.h for PHY register IF */
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/* Defines taken from linux-2.6.36/include/linux/mii.h for PHY register IF */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_NCONFIG 0x1c /* Network interface config */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* Basic mode control register. */
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/* Basic mode control register. */
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#define BMCR_RESV 0x003f /* Unused... */
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#define BMCR_RESV 0x003f /* Unused... */
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#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
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#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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/* Basic mode status register. */
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/* Basic mode status register. */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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#define BMSR_JCD 0x0002 /* Jabber detected */
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#define BMSR_JCD 0x0002 /* Jabber detected */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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#define BMSR_RFAULT 0x0010 /* Remote fault detected */
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#define BMSR_RFAULT 0x0010 /* Remote fault detected */
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#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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#define BMSR_RESV 0x00c0 /* Unused... */
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#define BMSR_RESV 0x00c0 /* Unused... */
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#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
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#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
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#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
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#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
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#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
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#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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/* Advertisement control register. */
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/* Advertisement control register. */
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#define ADVERTISE_SLCT 0x001f /* Selector bits */
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#define ADVERTISE_SLCT 0x001f /* Selector bits */
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#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
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#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
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#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
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#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
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#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
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#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
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#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
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#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
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#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
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#define ADVERTISE_RESV 0x1000 /* Unused... */
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#define ADVERTISE_RESV 0x1000 /* Unused... */
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#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
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#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
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ADVERTISE_CSMA)
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ADVERTISE_CSMA)
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#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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ADVERTISE_100HALF | ADVERTISE_100FULL)
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ADVERTISE_100HALF | ADVERTISE_100FULL)
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/* Link partner ability register. */
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/* Link partner ability register. */
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#define LPA_SLCT 0x001f /* Same as advertise selector */
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#define LPA_SLCT 0x001f /* Same as advertise selector */
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#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
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#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
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#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
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#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
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#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
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#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
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#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
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#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
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#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
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#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
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#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
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#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
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#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
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#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
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#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
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#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
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#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
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#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
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#define LPA_PAUSE_CAP 0x0400 /* Can pause */
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#define LPA_PAUSE_CAP 0x0400 /* Can pause */
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#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
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#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
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#define LPA_RESV 0x1000 /* Unused... */
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#define LPA_RESV 0x1000 /* Unused... */
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#define LPA_RFAULT 0x2000 /* Link partner faulted */
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#define LPA_RFAULT 0x2000 /* Link partner faulted */
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#define LPA_LPACK 0x4000 /* Link partner acked us */
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#define LPA_LPACK 0x4000 /* Link partner acked us */
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#define LPA_NPAGE 0x8000 /* Next page bit */
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#define LPA_NPAGE 0x8000 /* Next page bit */
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#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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/* Expansion register for auto-negotiation. */
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/* Expansion register for auto-negotiation. */
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#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
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#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
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#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
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#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
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#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
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#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
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#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
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#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
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#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
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#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
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#define EXPANSION_RESV 0xffe0 /* Unused... */
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#define EXPANSION_RESV 0xffe0 /* Unused... */
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#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
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#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
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#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
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#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
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/* N-way test register. */
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/* N-way test register. */
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#define NWAYTEST_RESV1 0x00ff /* Unused... */
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#define NWAYTEST_RESV1 0x00ff /* Unused... */
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#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
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#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
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#define NWAYTEST_RESV2 0xfe00 /* Unused... */
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#define NWAYTEST_RESV2 0xfe00 /* Unused... */
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/* 1000BASE-T Control register */
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/* 1000BASE-T Control register */
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#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
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#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
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#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
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#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
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/* 1000BASE-T Status register */
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/* 1000BASE-T Status register */
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#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
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#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
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#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
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#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
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#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
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#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
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#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
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#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
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/* Flow control flags */
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/* Flow control flags */
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#define FLOW_CTRL_TX 0x01
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#define FLOW_CTRL_TX 0x01
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#define FLOW_CTRL_RX 0x02
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#define FLOW_CTRL_RX 0x02
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#endif /* ETH__H */
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#endif /* ETH__H */
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