/* mc.c -- Simulation of Memory Controller
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/* mc.c -- Simulation of Memory Controller
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Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
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Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Enable memory controller, via:
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/* Enable memory controller, via:
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section mc
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section mc
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enable = 1
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enable = 1
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POC = 0x13243545
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POC = 0x13243545
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end
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end
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Limitations:
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Limitations:
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- memory refresh is not simulated
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- memory refresh is not simulated
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*/
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*/
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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/* Package includes */
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/* Package includes */
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "toplevel-support.h"
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#include "toplevel-support.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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#include "mc.h"
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#include "mc.h"
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struct mc_area
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struct mc_area
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{
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{
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struct dev_memarea *mem;
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struct dev_memarea *mem;
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unsigned int cs;
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unsigned int cs;
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int mc;
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int mc;
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struct mc_area *next;
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struct mc_area *next;
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};
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};
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struct mc
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struct mc
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{
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{
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uint32_t csr;
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uint32_t csr;
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uint32_t poc;
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uint32_t poc;
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uint32_t ba_mask;
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uint32_t ba_mask;
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uint32_t csc[N_CE];
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uint32_t csc[N_CE];
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uint32_t tms[N_CE];
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uint32_t tms[N_CE];
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oraddr_t baseaddr;
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oraddr_t baseaddr;
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int enabled;
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int enabled;
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/* Index of this memory controler amongst all the memory controlers */
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/* Index of this memory controler amongst all the memory controlers */
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int index;
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int index;
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/* List of memory devices under this mc's control */
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/* List of memory devices under this mc's control */
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struct mc_area *mc_areas;
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struct mc_area *mc_areas;
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struct mc *next;
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struct mc *next;
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};
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};
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static struct mc *mcs = NULL;
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static struct mc *mcs = NULL;
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/* List used to temporarily hold memory areas registered with the mc, while the
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/* List used to temporarily hold memory areas registered with the mc, while the
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* mc configureation has not been loaded */
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* mc configureation has not been loaded */
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static struct mc_area *mc_areas = NULL;
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static struct mc_area *mc_areas = NULL;
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void
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void
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set_csc_tms (int cs, uint32_t csc, uint32_t tms, struct mc *mc)
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set_csc_tms (int cs, uint32_t csc, uint32_t tms, struct mc *mc)
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{
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{
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struct mc_area *cur = mc->mc_areas;
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struct mc_area *cur = mc->mc_areas;
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while (cur)
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while (cur)
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{
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{
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if (cur->cs == cs)
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if (cur->cs == cs)
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{
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{
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/* FIXME: No peripheral should _ever_ acess a dev_memarea structure
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/* FIXME: No peripheral should _ever_ acess a dev_memarea structure
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* directly */
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* directly */
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cur->mem->addr_mask = mc->ba_mask << 22;
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cur->mem->addr_mask = mc->ba_mask << 22;
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cur->mem->addr_compare =
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cur->mem->addr_compare =
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((csc >> MC_CSC_SEL_OFFSET) /* & 0xff */ ) << 22;
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((csc >> MC_CSC_SEL_OFFSET) /* & 0xff */ ) << 22;
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set_mem_valid (cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);
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set_mem_valid (cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC)
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if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC)
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{
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{
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adjust_rw_delay (cur->mem, (tms & 0xff) + ((tms >> 8) & 0x0f),
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adjust_rw_delay (cur->mem, (tms & 0xff) + ((tms >> 8) & 0x0f),
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((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) +
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((tms >> 12) & 0x0f) + ((tms >> 16) & 0x0f) +
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((tms >> 20) & 0x3f));
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((tms >> 20) & 0x3f));
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}
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}
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else if ((csc >> MC_CSC_MEMTYPE_OFFSET)
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else if ((csc >> MC_CSC_MEMTYPE_OFFSET)
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&& 0x07 == MC_CSC_MEMTYPE_SDRAM)
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&& 0x07 == MC_CSC_MEMTYPE_SDRAM)
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{
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{
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adjust_rw_delay (cur->mem, 3 + ((tms >> 4) & 0x03),
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adjust_rw_delay (cur->mem, 3 + ((tms >> 4) & 0x03),
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3 + ((tms >> 4) & 0x03));
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3 + ((tms >> 4) & 0x03));
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}
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}
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else if ((csc >> MC_CSC_MEMTYPE_OFFSET)
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else if ((csc >> MC_CSC_MEMTYPE_OFFSET)
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&& 0x07 == MC_CSC_MEMTYPE_SSRAM)
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&& 0x07 == MC_CSC_MEMTYPE_SSRAM)
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{
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{
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adjust_rw_delay (cur->mem, 2, 2);
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adjust_rw_delay (cur->mem, 2, 2);
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}
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}
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else if ((csc >> MC_CSC_MEMTYPE_OFFSET)
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else if ((csc >> MC_CSC_MEMTYPE_OFFSET)
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&& 0x07 == MC_CSC_MEMTYPE_SYNC)
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&& 0x07 == MC_CSC_MEMTYPE_SYNC)
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{
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{
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adjust_rw_delay (cur->mem, 2, 2);
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adjust_rw_delay (cur->mem, 2, 2);
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}
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}
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return;
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return;
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}
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}
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cur = cur->next;
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cur = cur->next;
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}
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}
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}
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}
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/* Set a specific MC register with value. */
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/* Set a specific MC register with value. */
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void
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void
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mc_write_word (oraddr_t addr, uint32_t value, void *dat)
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mc_write_word (oraddr_t addr, uint32_t value, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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int chipsel;
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int chipsel;
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switch (addr)
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switch (addr)
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{
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{
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case MC_CSR:
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case MC_CSR:
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mc->csr = value;
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mc->csr = value;
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break;
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break;
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case MC_POC:
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case MC_POC:
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fprintf (stderr, "Warning: write to MC's POC register!");
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fprintf (stderr, "Warning: write to MC's POC register!");
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break;
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break;
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case MC_BA_MASK:
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case MC_BA_MASK:
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mc->ba_mask = value & MC_BA_MASK_VALID;
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mc->ba_mask = value & MC_BA_MASK_VALID;
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for (chipsel = 0; chipsel < N_CE; chipsel++)
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for (chipsel = 0; chipsel < N_CE; chipsel++)
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set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
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set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
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break;
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break;
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default:
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default:
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if (addr >= MC_CSC (0) && addr <= MC_TMS (N_CE - 1))
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if (addr >= MC_CSC (0) && addr <= MC_TMS (N_CE - 1))
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{
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{
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addr -= MC_CSC (0);
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addr -= MC_CSC (0);
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if ((addr >> 2) & 1)
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if ((addr >> 2) & 1)
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mc->tms[addr >> 3] = value;
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mc->tms[addr >> 3] = value;
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else
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else
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mc->csc[addr >> 3] = value;
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mc->csc[addr >> 3] = value;
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set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
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set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
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break;
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break;
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}
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}
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}
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}
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}
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}
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/* Read a specific MC register. */
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/* Read a specific MC register. */
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uint32_t
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uint32_t
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mc_read_word (oraddr_t addr, void *dat)
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mc_read_word (oraddr_t addr, void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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uint32_t value = 0;
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uint32_t value = 0;
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switch (addr)
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switch (addr)
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{
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{
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case MC_CSR:
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case MC_CSR:
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value = mc->csr;
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value = mc->csr;
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break;
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break;
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case MC_POC:
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case MC_POC:
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value = mc->poc;
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value = mc->poc;
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break;
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break;
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case MC_BA_MASK:
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case MC_BA_MASK:
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value = mc->ba_mask;
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value = mc->ba_mask;
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break;
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break;
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default:
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default:
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if (addr >= MC_CSC (0) && addr <= MC_TMS (N_CE - 1))
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if (addr >= MC_CSC (0) && addr <= MC_TMS (N_CE - 1))
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{
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{
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addr -= MC_CSC (0);
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addr -= MC_CSC (0);
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if ((addr >> 2) & 1)
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if ((addr >> 2) & 1)
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value = mc->tms[addr >> 3];
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value = mc->tms[addr >> 3];
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else
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else
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value = mc->csc[addr >> 3];
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value = mc->csc[addr >> 3];
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}
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}
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break;
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break;
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}
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}
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return value;
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return value;
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}
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}
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/* Read POC register and init memory controler regs. */
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/* Read POC register and init memory controler regs. */
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void
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void
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mc_reset (void *dat)
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mc_reset (void *dat)
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{
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{
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struct mc *mc = dat;
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struct mc *mc = dat;
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struct mc_area *cur, *prev, *tmp;
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struct mc_area *cur, *prev, *tmp;
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PRINTF ("Resetting memory controller.\n");
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PRINTF ("Resetting memory controller.\n");
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memset (mc->csc, 0, sizeof (mc->csc));
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memset (mc->csc, 0, sizeof (mc->csc));
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memset (mc->tms, 0, sizeof (mc->tms));
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memset (mc->tms, 0, sizeof (mc->tms));
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mc->csr = 0;
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mc->csr = 0;
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mc->ba_mask = 0;
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mc->ba_mask = 0;
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/* Set CS0 */
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/* Set CS0 */
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mc->csc[0] =
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mc->csc[0] =
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(((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((mc->
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(((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((mc->
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poc & 0x03) <<
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poc & 0x03) <<
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MC_CSC_BW_OFFSET) |
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MC_CSC_BW_OFFSET) |
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1;
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1;
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if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC)
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if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC)
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{
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{
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mc->tms[0] = MC_TMS_ASYNC_VALID;
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mc->tms[0] = MC_TMS_ASYNC_VALID;
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}
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}
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else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET)
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else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET)
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&& 0x07 == MC_CSC_MEMTYPE_SDRAM)
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&& 0x07 == MC_CSC_MEMTYPE_SDRAM)
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{
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{
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mc->tms[0] = MC_TMS_SDRAM_VALID;
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mc->tms[0] = MC_TMS_SDRAM_VALID;
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}
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}
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else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET)
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else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET)
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&& 0x07 == MC_CSC_MEMTYPE_SSRAM)
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&& 0x07 == MC_CSC_MEMTYPE_SSRAM)
|
{
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{
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mc->tms[0] = MC_TMS_SSRAM_VALID;
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mc->tms[0] = MC_TMS_SSRAM_VALID;
|
}
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}
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else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET)
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else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET)
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&& 0x07 == MC_CSC_MEMTYPE_SYNC)
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&& 0x07 == MC_CSC_MEMTYPE_SYNC)
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{
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{
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mc->tms[0] = MC_TMS_SYNC_VALID;
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mc->tms[0] = MC_TMS_SYNC_VALID;
|
}
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}
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|
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/* Grab control over all the devices we are destined to control */
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/* Grab control over all the devices we are destined to control */
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cur = mc_areas;
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cur = mc_areas;
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prev = NULL;
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prev = NULL;
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while (cur)
|
while (cur)
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{
|
{
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if (cur->mc == mc->index)
|
if (cur->mc == mc->index)
|
{
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{
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if (prev)
|
if (prev)
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prev->next = cur->next;
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prev->next = cur->next;
|
else
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else
|
mc_areas = cur->next;
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mc_areas = cur->next;
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prev = cur;
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prev = cur;
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tmp = cur->next;
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tmp = cur->next;
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cur->next = mc->mc_areas;
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cur->next = mc->mc_areas;
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mc->mc_areas = cur;
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mc->mc_areas = cur;
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cur = tmp;
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cur = tmp;
|
}
|
}
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else
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else
|
{
|
{
|
prev = cur;
|
prev = cur;
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cur = cur->next;
|
cur = cur->next;
|
}
|
}
|
}
|
}
|
|
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for (cur = mc->mc_areas; cur; cur = cur->next)
|
for (cur = mc->mc_areas; cur; cur = cur->next)
|
set_mem_valid (cur->mem, 0);
|
set_mem_valid (cur->mem, 0);
|
|
|
set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
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set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
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}
|
}
|
|
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Free all allocated memory */
|
/*!Free all allocated memory */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
void
|
void
|
mc_done ()
|
mc_done ()
|
{
|
{
|
while (NULL != mc_areas)
|
while (NULL != mc_areas)
|
{
|
{
|
struct mc_area *next = mc_areas->next;
|
struct mc_area *next = mc_areas->next;
|
|
|
free (mc_areas);
|
free (mc_areas);
|
mc_areas = next;
|
mc_areas = next;
|
}
|
}
|
} /* mc_done () */
|
} /* mc_done () */
|
|
|
|
|
void
|
void
|
mc_status (void *dat)
|
mc_status (void *dat)
|
{
|
{
|
struct mc *mc = dat;
|
struct mc *mc = dat;
|
int i;
|
int i;
|
|
|
PRINTF ("\nMemory Controller at 0x%" PRIxADDR ":\n", mc->baseaddr);
|
PRINTF ("\nMemory Controller at 0x%" PRIxADDR ":\n", mc->baseaddr);
|
PRINTF ("POC: 0x%" PRIx32 "\n", mc->poc);
|
PRINTF ("POC: 0x%" PRIx32 "\n", mc->poc);
|
PRINTF ("BAS: 0x%" PRIx32 "\n", mc->ba_mask);
|
PRINTF ("BAS: 0x%" PRIx32 "\n", mc->ba_mask);
|
PRINTF ("CSR: 0x%" PRIx32 "\n", mc->csr);
|
PRINTF ("CSR: 0x%" PRIx32 "\n", mc->csr);
|
|
|
for (i = 0; i < N_CE; i++)
|
for (i = 0; i < N_CE; i++)
|
{
|
{
|
PRINTF ("CE %02d - CSC: 0x%" PRIx32 " TMS: 0x%" PRIx32 "\n", i,
|
PRINTF ("CE %02d - CSC: 0x%" PRIx32 " TMS: 0x%" PRIx32 "\n", i,
|
mc->csc[i], mc->tms[i]);
|
mc->csc[i], mc->tms[i]);
|
}
|
}
|
}
|
}
|
|
|
/*--------------------------------------------[ Peripheral<->MC interface ]---*/
|
/*--------------------------------------------[ Peripheral<->MC interface ]---*/
|
/* Registers some memory to be under the memory controllers control */
|
/* Registers some memory to be under the memory controllers control */
|
void
|
void
|
mc_reg_mem_area (struct dev_memarea *mem, unsigned int cs, int mc)
|
mc_reg_mem_area (struct dev_memarea *mem, unsigned int cs, int mc)
|
{
|
{
|
struct mc_area *new = malloc (sizeof (struct mc_area));
|
struct mc_area *new = malloc (sizeof (struct mc_area));
|
|
|
if (NULL == new)
|
if (NULL == new)
|
{
|
{
|
fprintf (stderr, "Out-of-memory\n");
|
fprintf (stderr, "Out-of-memory\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
|
|
new->cs = cs;
|
new->cs = cs;
|
new->mem = mem;
|
new->mem = mem;
|
new->mc = mc;
|
new->mc = mc;
|
|
|
new->next = mc_areas;
|
new->next = mc_areas;
|
|
|
mc_areas = new;
|
mc_areas = new;
|
}
|
}
|
|
|
/*-----------------------------------------------------[ MC configuration ]---*/
|
/*-----------------------------------------------------[ MC configuration ]---*/
|
static void
|
static void
|
mc_enabled (union param_val val, void *dat)
|
mc_enabled (union param_val val, void *dat)
|
{
|
{
|
struct mc *mc = dat;
|
struct mc *mc = dat;
|
mc->enabled = val.int_val;
|
mc->enabled = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
mc_baseaddr (union param_val val, void *dat)
|
mc_baseaddr (union param_val val, void *dat)
|
{
|
{
|
struct mc *mc = dat;
|
struct mc *mc = dat;
|
mc->baseaddr = val.addr_val;
|
mc->baseaddr = val.addr_val;
|
}
|
}
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the power on configuration state
|
/*!Set the power on configuration state
|
|
|
Only the bottom 4 bits are signficant. Other bits are truncated with a
|
Only the bottom 4 bits are signficant. Other bits are truncated with a
|
warning.
|
warning.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
mc_poc (union param_val val,
|
mc_poc (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct mc *mc = dat;
|
struct mc *mc = dat;
|
|
|
if (val.int_val > 0xf)
|
if (val.int_val > MC_POC_VALID)
|
{
|
{
|
fprintf (stderr, "Warning: memory controller PoC > 4 bits: truncated\n");
|
fprintf (stderr, "Warning: memory controller PoC > 0x%lx: truncated\n",
|
|
MC_POC_VALID);
|
}
|
}
|
|
|
mc->poc = val.int_val & 0xf;
|
mc->poc = val.int_val & MC_POC_VALID;
|
|
|
} /* mc_poc() */
|
} /* mc_poc() */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Set the index of this memory controller.
|
|
|
|
This identifies which chip enable value will select this memory
|
|
controller. Truncate if the value is too large with a warning.
|
|
|
|
@param[in] val The value to use
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
mc_index (union param_val val, void *dat)
|
mc_index (union param_val val, void *dat)
|
{
|
{
|
struct mc *mc = dat;
|
struct mc *mc = dat;
|
mc->index = val.int_val;
|
|
|
if (val.int_val > MC_CE_VALID)
|
|
{
|
|
fprintf (stderr, "Warning: memory controller index > 0x%x: truncated.\n",
|
|
MC_CE_VALID);
|
}
|
}
|
|
|
|
mc->index = val.int_val & MC_CE_VALID;
|
|
}
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Initialize a new memory controller configuration
|
/*!Initialize a new memory controller configuration
|
|
|
ALL parameters are set explicitly to default values. */
|
ALL parameters are set explicitly to default values. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void *
|
static void *
|
mc_sec_start ()
|
mc_sec_start ()
|
{
|
{
|
struct mc *new = malloc (sizeof (struct mc));
|
struct mc *new = malloc (sizeof (struct mc));
|
|
|
if (!new)
|
if (!new)
|
{
|
{
|
fprintf (stderr, "Peripheral MC: Run out of memory\n");
|
fprintf (stderr, "Peripheral MC: Run out of memory\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
|
|
new->enabled = 1;
|
new->enabled = 1;
|
new->baseaddr = 0;
|
new->baseaddr = 0;
|
new->poc = 0;
|
new->poc = 0;
|
new->index = 0;
|
new->index = 0;
|
|
|
new->mc_areas = NULL;
|
new->mc_areas = NULL;
|
|
|
return new;
|
return new;
|
}
|
}
|
|
|
static void
|
static void
|
mc_sec_end (void *dat)
|
mc_sec_end (void *dat)
|
{
|
{
|
struct mc *mc = dat;
|
struct mc *mc = dat;
|
struct mem_ops ops;
|
struct mem_ops ops;
|
|
|
if (!mc->enabled)
|
if (!mc->enabled)
|
{
|
{
|
free (dat);
|
free (dat);
|
return;
|
return;
|
}
|
}
|
|
|
/* FIXME: Check to see that the index given to this mc is unique */
|
/* FIXME: Check to see that the index given to this mc is unique */
|
|
|
mc->next = mcs;
|
mc->next = mcs;
|
mcs = mc;
|
mcs = mc;
|
|
|
memset (&ops, 0, sizeof (struct mem_ops));
|
memset (&ops, 0, sizeof (struct mem_ops));
|
|
|
ops.readfunc32 = mc_read_word;
|
ops.readfunc32 = mc_read_word;
|
ops.writefunc32 = mc_write_word;
|
ops.writefunc32 = mc_write_word;
|
ops.write_dat32 = dat;
|
ops.write_dat32 = dat;
|
ops.read_dat32 = dat;
|
ops.read_dat32 = dat;
|
|
|
/* FIXME: Correct delays? */
|
/* FIXME: Correct delays? */
|
ops.delayr = 2;
|
ops.delayr = 2;
|
ops.delayw = 2;
|
ops.delayw = 2;
|
|
|
reg_mem_area (mc->baseaddr, MC_ADDR_SPACE, 1, &ops);
|
reg_mem_area (mc->baseaddr, MC_ADDR_SPACE, 1, &ops);
|
reg_sim_reset (mc_reset, dat);
|
reg_sim_reset (mc_reset, dat);
|
reg_sim_stat (mc_status, dat);
|
reg_sim_stat (mc_status, dat);
|
}
|
}
|
|
|
void
|
void
|
reg_mc_sec (void)
|
reg_mc_sec (void)
|
{
|
{
|
struct config_section *sec =
|
struct config_section *sec =
|
reg_config_sec ("mc", mc_sec_start, mc_sec_end);
|
reg_config_sec ("mc", mc_sec_start, mc_sec_end);
|
|
|
reg_config_param (sec, "enabled", PARAMT_INT, mc_enabled);
|
reg_config_param (sec, "enabled", PARAMT_INT, mc_enabled);
|
reg_config_param (sec, "baseaddr", PARAMT_ADDR, mc_baseaddr);
|
reg_config_param (sec, "baseaddr", PARAMT_ADDR, mc_baseaddr);
|
reg_config_param (sec, "POC", PARAMT_INT, mc_poc);
|
reg_config_param (sec, "POC", PARAMT_INT, mc_poc);
|
reg_config_param (sec, "index", PARAMT_INT, mc_index);
|
reg_config_param (sec, "index", PARAMT_INT, mc_index);
|
}
|
}
|
|
|
