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/* sim.cfg -- Simulator configuration script file
/* sim.cfg -- Simulator configuration script file
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
 
 
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
It contains the default configuration and help about configuring
 
the simulator.
 
 
 
This program is free software; you can redistribute it and/or modify
 
it under the terms of the GNU General Public License as published by
 
the Free Software Foundation; either version 2 of the License, or
 
(at your option) any later version.
 
 
 
This program is distributed in the hope that it will be useful,
 
but WITHOUT ANY WARRANTY; without even the implied warranty of
 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
GNU General Public License for more details.
 
 
 
You should have received a copy of the GNU General Public License
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
along with this program; if not, write to the Free Software
   Copyright (C) 2010, Embecosm Limited
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
 
 
 
/* INTRODUCTION
 
 
 
   The ork1sim has various parameters, that are set in configuration files
 
   like this one. The user can switch between configurations at startup by
 
   specifying the required configuration file with the -f  option.
 
   If no configuration file is specified or1ksim searches for the default
 
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
 
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
 
   not found too, it reverts to the built-in default configuration.
 
 
 
   NOTE: Users should not rely on the built-in configuration, since the
   Contributor Jeremy Bennett 
         default configuration may differ between version.
 
         Rather create a configuration file that sets all critical values.
 
 
 
   This file may contain (standard C) comments only - no // support.
   This file is part of OpenRISC 1000 Architectural Simulator.
 
 
   Configure files may be be included, using:
   This program is free software; you can redistribute it and/or modify it
   include "file_name_to_include"
   under the terms of the GNU General Public License as published by the Free
 
   Software Foundation; either version 3 of the License, or (at your option)
 
   any later version.
 
 
 
   This program is distributed in the hope that it will be useful, but WITHOUT
 
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 
   more details.
 
 
 
   You should have received a copy of the GNU General Public License along
 
   with this program.  If not, see . */
 
 
 
 
 
/* -------------------------------------------------------------------------- */
 
/* The Ork1sim has various parameters, that can be set in configuration files
 
   like this one. The user can specify a configuration file at startu[ with
 
   the -f  option.
 
 
 
   The user guide (see the 'doc' directory) gives full details on
 
   configuration files. This is a reference configuration, which may be used
 
   as a starting point for customization.
 
 
 
   A number of peripherals are mapped at standard addresses (above 0x80000000)
 
   in the Verilog RTL of ORPSoC standard sitribution. The same values should
 
   be used in Or1ksim section definitions to match the behavior of the Verilog
 
 
 
      0x90000000 UART
 
      0x91000000 GPIO
 
      0x92000000 Ethernet
 
      0x93000000 Memory controller
 
      0x94000000 PS2 keyboard
 
      0x97000000 Frame buffer
 
      0x97100000 VGA
 
      0x9a000000 DMA controller
 
      0x9e000000 ATA disc
 
 
 
   Section ordering matches that in the user guide. All optional peripherals
 
   and functionality is disabled. Comments only list the possible entries and
 
   values. Consult the user guide for their meaning.
 
 
   Like normal configuration files, the included file is divided into
   Unless otherwise indicated, the first named option is the default.         */
   sections. Each section is described in detail also.
/* -------------------------------------------------------------------------- */
 
 
   Some section have subsections. One example of such a subsection is:
 
 
 
   device 
/* Simulator section
     instance specific parameters...
 
   enddevice
 
 
 
   which creates a device instance.
   verbose               = 0|1
 
   debug                 = 0-9
 
   profile               = 0|1
 
   prof_file             = "" (default: "sim.profile")
 
   mprofile              = 0|1
 
   mprof_file            = "" (default: "sim.mprofile")
 
   history               = 0|1
 
   exe_log               = 0|1
 
   exe_log_type          = hardware|simple|software|default
 
   exe_log_start         =  (default: 0)
 
   exe_log_end           =  (default: never end)
 
   exe_log_marker        =  (default: no markers)
 
   exe_log_file          = "" (default: "executed.log")
 
   exe_bin_insn_log      = 0|1
 
   exe_bin_insn_log_file = "" (default: "exe-insn.bin")
 
   clkcycle              = [ps|ns|us|ms]
*/
*/
 
section sim
 
  clkcycle = 100ns
 
end
 
 
 
 
/* MEMORY SECTION
/* VAPI section
 
 
   This section specifies how the memory is generated and the blocks
 
   it consists of.
 
 
 
   type = random/unknown/pattern
 
      Specifies the initial memory values.
 
      'random' generates random memory using seed 'random_seed'.
 
      'pattern' fills memory with 'pattern'.
 
      'unknown' does not specify how memory should be generated,
 
      leaving the memory in a undefined state. This is the fastest
 
      option.
 
 
 
   random_seed = 
   enabled        = 0|1
      random seed for randomizer, used if type = 'random'.
   server_port    =  (default: 50000)
 
   log_enabled    = 0|1
 
   hide_device_id = 0|1
 
   vapi_log_file  = "" (default "vapi.log")
 
*/
 
section VAPI
 
  server_port = 50000
 
  log_enabled = 0
 
  vapi_log_file = "vapi.log"
 
end
 
 
   pattern = 
 
      pattern to fill memory, used if type = 'pattern'.
 
 
 
   baseaddr = 
/* CUC section
      memory start address
 
 
 
   size = 
    memory_order       = none|weak|strong|exact (default: strong)
      memory size
    calling_convention = 0|1
 
    enable_bursts      = 0|1
 
    no_multicycle      = 0|1
 
    timings_file       = "" (default: virtex.tim)
 
*/
 
section cuc
 
  memory_order       = weak
 
  calling_convention = 1
 
  enable_bursts      = 1
 
  no_multicycle      = 1
 
end
 
 
   name = ""
 
      memory block name
 
 
 
   ce = 
/* CPU section
      chip enable index of the memory instance
 
 
 
   mc = 
   ver         =  (default: 0)
      memory controller this memory is connected to
   cfg         =  (default: 0)
 
   rev         =  (default: 0)
 
   upr         =  (see user manual for default settings)
 
   cfgr        =  (default: 0x00000020)
 
   sr          =  (default: 0x00008001)
 
   superscalar = 0|1
 
   hazards     = 0|1
 
   dependstats = 0|1
 
   sbuf_len    =  (default: 0)
 
   hardfloat   = 0|1
 
*/
 
section cpu
 
  ver = 0x12
 
  cfg = 0x00
 
  rev = 0x0001
 
end
 
 
   delayr = 
 
      cycles, required for read access, -1 if instance does not support reading
 
 
 
   delayw = 
/* Memory section
      cycles, required for write access, -1 if instance does not support
 
      writing
 
 
 
   log = ""
   type        = unknown|random|unknown|pattern
      filename, where to log memory accesses to. If log command is not
   random_seed =  (default: -1)
      specified, accesses are not logged.
   pattern     =  (default: 0)
 
   baseaddr    =  (default: 0)
 
   size        =  (default: 1024)
 
   name        = "" (default: "anonymous memory block")
 
   ce          =  (default: -1)
 
   mc          =  (default: 0)
 
   delayr      =  (default: 1)
 
   delayw      =  (default: 1)
 
   log         = "" (default: NULL)
*/
*/
 
 
 
 
section memory
section memory
  name        = "RAM"
  name        = "RAM"
  random_seed = 12345
  type        = unknown
  type        = random
 
  ce          = 0
 
  mc          = 0
 
  baseaddr    = 0x00000000
  baseaddr    = 0x00000000
  size        = 0x00400000
  size        = 0x00800000
  delayr      = 1
  delayr      = 1
  delayw      = 2
  delayw      = 2
end
end
 
 
/* IMMU SECTION
 
 
 
    This section configures the Instruction Memory Manangement Unit
 
 
 
    enabled = 0/1
 
       '0': disabled
 
       '1': enabled
 
       (NOTE: UPR bit is set)
 
 
 
    nsets = 
 
       number of ITLB sets; must be power of two
 
 
 
    nways = 
 
       number of ITLB ways
 
 
 
    pagesize = 
 
       instruction page size; must be power of two
 
 
 
    entrysize = 
 
       instruction entry size in bytes
 
 
 
    ustates = 
/* Data MMU section
       number of ITLB usage states (2, 3, 4 etc., max is 4)
 
 
 
    hitdelay = 
   enabled   = 0|1
       number of cycles immu hit costs
   nsets     =  (default: 1)
 
   nways     =  (default: 1)
    missdelay = 
   pagesize  =  (default: 8192)
       number of cycles immu miss costs
   entrysize =  (default: 1)
 
   ustates   =  (default: 1)
 
   hitdelay  =  (default: 1)
 
   missdelay =  (default: 1)
*/
*/
 
section dmmu
section immu
  enabled   = 0
  enabled = 1
 
  nsets = 64
  nsets = 64
  nways = 1
  nways     = 1
  pagesize = 8192
  pagesize  = 8192
  hitdelay = 0
  hitdelay  = 0
  missdelay = 0
  missdelay = 0
end
end
 
 
/* DMMU SECTION
/* Instruction MMU section
 
 
    This section configures the Data Memory Manangement Unit
 
 
 
    enabled = 0/1
 
       '0': disabled
 
       '1': enabled
 
       (NOTE: UPR bit is set)
 
 
 
    nsets = 
 
       number of DTLB sets; must be power of two
 
 
 
    nways = 
   enabled   = 0|1
       number of DTLB ways
   nsets     =  (default: 1)
 
   nways     =  (default: 1)
    pagesize = 
   pagesize  =  (default: 8192)
       data page size; must be power of two
   entrysize =  (default: 1)
 
   ustates   =  (default: 1)
    entrysize = 
   hitdelay  =  (default: 1)
       data entry size in bytes
   missdelay =  (default: 1)
 
 
    ustates = 
 
       number of DTLB usage states (2, 3, 4 etc., max is 4)
 
 
 
    hitdelay = 
 
       number of cycles dmmu hit costs
 
 
 
    missdelay = 
 
       number of cycles dmmu miss costs
 
*/
*/
 
section immu
section dmmu
  enabled   = 0
  enabled = 1
 
  nsets = 64
  nsets = 64
  nways = 1
  nways     = 1
  pagesize = 8192
  pagesize  = 8192
  hitdelay = 0
  hitdelay  = 0
  missdelay = 0
  missdelay = 0
end
end
 
 
/* IC SECTION
/* Data cache section
 
 
   This section configures the Instruction Cache
 
 
 
   enabled = 0/1
 
       '0': disabled
 
       '1': enabled
 
      (NOTE: UPR bit is set)
 
 
 
   nsets = 
 
      number of IC sets; must be power of two
 
 
 
   nways = 
 
      number of IC ways
 
 
 
   blocksize = 
 
      IC block size in bytes; must be power of two
 
 
 
   ustates = 
 
      number of IC usage states (2, 3, 4 etc., max is 4)
 
 
 
   hitdelay = 
 
      number of cycles ic hit costs
 
 
 
    missdelay = 
   enabled         = 0|1
      number of cycles ic miss costs
   nsets           =  (default: 1)
*/
   nways           =  (default: 1)
 
   blocksize       =  (default: 16)
section ic
   ustates         =  (default: 2)
  enabled = 1
   load_hitdelay   =  (default: 2)
  nsets = 256
   load_missdelay  =  (default: 2)
  nways = 1
   store_hitdelay  =  (default: 0)
  blocksize = 16
   store_missdelay =  (default: 0)
  hitdelay = 0
 
  missdelay = 0
 
end
 
 
 
 
 
/* DC SECTION
 
 
 
   This section configures the Data Cache
 
 
 
   enabled = 0/1
 
       '0': disabled
 
       '1': enabled
 
      (NOTE: UPR bit is set)
 
 
 
   nsets = 
 
      number of DC sets; must be power of two
 
 
 
   nways = 
 
      number of DC ways
 
 
 
   blocksize = 
 
      DC block size in bytes; must be power of two
 
 
 
   ustates = 
 
      number of DC usage states (2, 3, 4 etc., max is 4)
 
 
 
   load_hitdelay = 
 
      number of cycles dc load hit costs
 
 
 
   load_missdelay = 
 
      number of cycles dc load miss costs
 
 
 
   store_hitdelay = 
 
      number of cycles dc store hit costs
 
 
 
   store_missdelay = 
 
      number of cycles dc store miss costs
 
*/
*/
section dc
section dc
  enabled = 1
  enabled         = 0
  nsets = 256
  nsets = 256
  nways = 1
  nways           = 1
  blocksize = 16
  blocksize       = 16
  load_hitdelay = 0
  load_hitdelay   = 0
  load_missdelay = 0
  load_missdelay  = 0
  store_hitdelay = 0
  store_hitdelay  = 0
  store_missdelay = 0
  store_missdelay = 0
end
end
 
 
/* PIC SECTION
/* Instruction cache section
 
 
  This section specifies how the pic should behave
 
 
 
  enabled = 0/1
 
      '0': PIC is disabled
 
      '1': PIC is enabled
 
 
 
  edge_trigger = 0/1
 
      '0': Level triggered PIC
 
      '1': Edge triggered PIC
 
*/
 
 
 
section pic
 
  enabled = 1
 
  edge_trigger = 1
 
end
 
 
 
 
 
/* SIM SECTION
 
 
 
  This section specifies how or1ksim should behave.
 
 
 
  verbose = 0/1
 
       '0': don't print extra messages
 
       '1': print extra messages
 
 
 
  debug = 0-9
 
      0  : no debug messages
 
      1-9: debug message level.
 
           higher numbers produce more messages
 
 
 
  profile = 0/1
 
      '0': don't generate profiling file 'sim.profile'
 
      '1': don't generate profiling file 'sim.profile'
 
 
 
  prof_file = ""
 
      optional filename for the profiling file.
 
      valid only if 'profile' is set
 
 
 
  mprofile = 0/1
 
      '0': don't generate memory profiling file 'sim.mprofile'
 
      '1': generate memory profiling file 'sim.mprofile'
 
 
 
  mprof_file = ""
 
      optional filename for the memory profiling file.
 
      valid only if 'mprofile' is set
 
 
 
  history = 0/1
 
      '0': don't track execution flow
 
      '1': track execution flow
 
      Execution flow can be tracked for the simulator's
 
      'hist' command. Useful for back-trace debugging.
 
 
 
  iprompt = 0/1
 
     '0': start in  (so what do we start in ???)
 
     '1': start in interactive prompt.
 
 
 
  exe_log = 0/1
 
      '0': don't generate execution log.
 
      '1': generate execution log.
 
 
 
  exe_log_type = default/hardware/simple/software
 
      type of execution log, default is used when not specified
 
 
 
  exe_log_start = 
 
      index of first instruction to start logging, default = 0
 
 
 
  exe_log_end = 
 
      index of last instruction to end logging; not limited, if omitted
 
 
 
  exe_log_marker = 
 
       specifies number of instructions before horizontal marker is
 
      printed; if zero, markers are disabled (default)
 
 
 
  exe_log_file = ""
 
      filename for the exection log file.
 
      valid only if 'exe_log' is set
 
 
 
  clkcycle = [ps|ns|us|ms]
 
      specifies time measurement for one cycle
 
*/
 
 
 
section sim
 
  /* verbose = 1 */
 
  debug = 0
 
  profile = 0
 
  prof_file = "sim.profile"
 
 
 
  history = 0
 
  /* iprompt = 0 */
 
  exe_log = 0
 
  exe_log_type = software
 
  exe_log_start = 0
 
/*  exe_log_end = 20000000*/
 
  exe_log_marker = 10000
 
  exe_log_file = "executed.log"
 
 
 
  clkcycle = 100ns
 
end
 
 
 
 
 
/* SECTION VAPI
 
 
 
    This section configures the Verification API, used for Advanced
 
    Core Verification.
 
 
 
    enabled = 0/1
 
        '0': disbable VAPI server
 
        '1': enable/start VAPI server
 
 
 
    server_port = 
 
        TCP/IP port to start VAPI server on
 
 
 
    log_enabled = 0/1
 
       '0': disable VAPI requests logging
 
       '1': enable VAPI requests logging
 
 
 
    hide_device_id = 0/1
 
       '1': don't log device id (for compatability with old version)
 
       '0': log device id
 
 
 
 
   enabled    = 0|1
    vapi_log_file = 
   nsets      =  (default: 1)
       filename for the log file.
   nways      =  (default: 1)
       valid only if log_enabled is set
   blocksize  =  (default: 16)
 
   ustates    =  (default: 2)
 
   hitdelay   =  (default: 1)
 
   missdelay  =  (default: 1)
*/
*/
 
section ic
section VAPI
 
  enabled = 0
  enabled = 0
  server_port = 50000
  nsets     = 256
  log_enabled = 0
  nways     = 1
  vapi_log_file = "vapi.log"
  blocksize = 16
 
  hitdelay  = 0
 
  missdelay = 0
end
end
 
 
/* CPU SECTION
/* Programmable interrupt controller section
 
 
   This section specifies various CPU parameters.
 
 
 
   ver = 
  enabled      = 0|1
   cfg = 
  edge_trigger = 0|1 (default: 1)
   rev = 
 
      specifies version, configuration and revision fields of the CPU version
 
      register.
 
 
 
   upr = 
 
      changes the upr register
 
 
 
   cfgr = 
 
      changes the CPU configuration register
 
 
 
   sr = 
 
      sets the initial Supervision Register value
 
 
 
   superscalar = 0/1
 
      '0': CPU is scalar
 
      '1': CPU is superscalar
 
      (modify cpu/or32/execute.c to tune superscalar model)
 
 
 
   hazards = 0/1
 
      '0': don't track data hazards in superscalar CPU
 
      '1': track data hazards in superscalar CPU
 
      If tracked, data hazards can be displayed using the
 
      simulator's 'r' command.
 
 
 
   dependstats = 0/1
 
      '0': don't calculate inter-instruction dependencies.
 
      '1': calculate inter-instruction dependencies.
 
      If calculated, inter-instruction dependencies can be
 
      displayed using the simulator's 'stat' command.
 
 
 
   sbuf_len = 
 
      length of store buffer (<= 256), 0 = disabled
 
*/
*/
 
 
section cpu
section pic
  ver = 0x12
  enabled = 0
  cfg = 0x00
 
  rev = 0x0001
 
  superscalar = 0
 
  hazards = 0
 
  dependstats = 0
 
  sbuf_len = 0
 
end
end
 
 
/* PM SECTION
/* Power management section
 
 
   This section specifies Power Management parameters
   enabled = 0|1
 
 
   enabled = 0/1
 
      '0': disable power management
 
      '1': enable power management
 
*/
*/
section pm
section pm
  enabled = 1
  enabled = 0
end
end
 
 
/* BPB SECTION
/* Branch prediction section
 
 
   This section specifies how branch prediction should behave.
 
 
 
   enabled = 0/1
 
     '0': disable branch prediction
 
     '1': enable branch prediction
 
 
 
   btic = 0/1
 
     '0': disable branch target instruction cache model
 
     '1': enable branch target instruction cache model
 
 
 
   sbp_bf_fwd = 0/1
   enabled     = 0|1
     Static branch prediction for 'l.bf'
   btic        = 0|1
     '0': don't use forward prediction
   sbp_bf_fwd  = 0|1
     '1': use forward prediction
   sbp_bnf_fwd = 0|1
 
   hitdelay    =  (default: 0)
   sbp_bnf_fwd = 0/1
   missdelay   =  (default: 0)
     Static branch prediction for 'l.bnf'
 
     '0': don't use forward prediction
 
     '1': use forward prediction
 
 
 
   hitdelay = 
 
       number of cycles bpb hit costs
 
 
 
   missdelay = 
 
       number of cycles bpb miss costs
 
*/
*/
section bpb
section bpb
  enabled = 1
  enabled = 0
  btic = 0
 
  sbp_bf_fwd = 0
 
  sbp_bnf_fwd = 0
 
  hitdelay = 0
 
  missdelay = 0
 
end
end
 
 
/* DEBUG SECTION
/* Debug unit section
 
 
   This sections specifies how the debug unit should behave.
 
 
 
   enabled = 0/1
 
      '0': disable debug unit
 
      '1': enable debug unit
 
 
 
   gdb_enabled = 0/1
   enabled     = 0|1
      '0': don't start gdb server
   rsp_enabled = 0|1
      '1': start gdb server at port 'server_port'
   rsp_port    =  (default: 51000)
 
   vapi_id     =  (default: 0)
   server_port = 
 
      TCP/IP port to start gdb server on
 
      valid only if gdb_enabled is set
 
 
 
   vapi_id = 
 
      Used to create "fake" vapi log file containing the JTAG proxy messages.
 
*/
*/
 
 
section debug
section debug
  enabled = 0
  enabled = 0
  gdb_enabled = 0
 
  server_port = 51000
 
end
end
 
 
/* MC SECTION
/* Memory controller section
 
 
   This section configures the memory controller
 
 
 
   enabled = 0/1
 
     '0': disable memory controller
 
     '1': enable memory controller
 
 
 
   baseaddr = 
   enabled  = 0|1
      address of first MC register
   baseaddr =  (default: 0)
 
   POC      =  (default: 0)
   POC = 
   index    =  (default: 0)
      Power On Configuration register
 
 
 
   index = 
 
      Index of this memory controller amongst all the memory controllers
 
*/
*/
section mc
section mc
  enabled = 1
  enabled  = 0
  baseaddr = 0x93000000
  baseaddr = 0x93000000
  POC = 0x0000000a                 /* 32 bit SSRAM */
  POC      = 0x0000000a                 /* 32 bit SSRAM */
  index = 0
  index    = 0
end
end
 
 
/* UART SECTION
/* UART section
 
 
   This section configures the UARTs
 
 
 
     enabled = <0|1>
 
        Enable/disable the peripheral.  By default if it is enabled.
 
 
 
     baseaddr = 
 
        address of first UART register for this device
 
 
 
 
 
     channel = :
 
 
 
        The channel parameter indicates the source of received UART characters
 
        and the sink for transmitted UART characters.
 
 
 
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
 
        (without quotes).
 
 
 
          A) To send/receive characters from a pair of files, use a file
 
             channel:
 
 
 
               channel=file:,
   enabled  = 0|1
 
   baseaddr =  (default: 0)
          B) To create an interactive terminal window, use an xterm channel:
   channel  = "value>" (default: "xterm:")
 
   irq      =  (default: 0)
               channel=xterm:[]*
   16550    = 0|1
 
   jitter   =  (default: 0)
          C) To create a bidirectional tcp socket which one could, for example,
   vapi_id  =  (default: 0)
             access via telnet, use a tcp channel:
 
 
 
               channel=tcp:
 
 
 
          D) To cause the UART to read/write from existing numeric file
 
             descriptors, use an fd channel:
 
 
 
               channel=fd:,
 
 
 
          E) To connect the UART to a physical serial port, create a tty
 
             channel:
 
 
 
               channel=tty:device=/dev/ttyS0,baud=9600
 
 
 
     irq = 
 
        irq number for this device
 
 
 
     16550 = 0/1
 
        '0': this device is a UART16450
 
        '1': this device is a UART16550
 
 
 
     jitter = 
 
        in msecs... time to block, -1 to disable it
 
 
 
     vapi_id = 
 
        VAPI id of this instance
 
*/
*/
section uart
section uart
  enabled = 1
  enabled  = 0
  baseaddr = 0x90000000
  baseaddr = 0x90000000
  irq = 2
  irq = 2
  channel = "file:uart0.rx,uart0.tx"
 
  jitter = -1                     /* async behaviour */
 
  16550 = 1
  16550 = 1
end
end
 
 
/* DMA SECTION
/* DMA section
 
 
   This section configures the DMAs
 
 
 
     enabled = <0|1>
 
        Enable/disable the peripheral.  By default if it is enabled.
 
 
 
     baseaddr = 
 
        address of first DMA register for this device
 
 
 
     irq = 
 
        irq number for this device
 
 
 
     vapi_id = 
   enabled  = 0|1
        VAPI id of this instance
   baseaddr =  (default: 0)
 
   irq      =  (default: 0)
 
   vapi_id  =  (default: 0)
*/
*/
 
 
section dma
section dma
  enabled = 1
  enabled  = 0
  baseaddr = 0x9a000000
  baseaddr = 0x9a000000
  irq = 11
  irq      = 11
end
end
 
 
/* ETHERNET SECTION
/* Ethernet section
 
 
   This section configures the ETHERNETs
 
 
 
     enabled = <0|1>
 
        Enable/disable the peripheral.  By default if it is enabled.
 
 
 
     baseaddr = 
 
        address of first ethernet register for this device
 
 
 
     dma = 
 
        which controller is this ethernet "connected" to
 
 
 
     irq = 
 
        ethernet mac IRQ level
 
 
 
     rtx_type = 
 
        use 0 - file interface, 1 - socket interface. Note the socket
 
        interface must be configured at build time.
 
 
 
     rx_channel = 
   enabled    = 0|1
        DMA channel used for RX
   baseaddr   =  (default: 0)
 
   dma        =  (default: 0)
     tx_channel = 
   irq        =  (default: 0)
        DMA channel used for TX
   rtx_type   = 0|1
 
   rx_channel =  (default: 0)
     rxfile = ""
   tx_channel =  (default: 0)
        filename, where to read data from
   rxfile     = "" (default: "eth_rx")
 
   txfile     = "" (default: "eth_rx")
     txfile = ""
   sockif     = "" (default: "or1ksim_eth")
        filename, where to write data to
   vapi_id    =  (default: 0)
 
 
     sockif = ""
 
        interface name of ethernet socket
 
 
 
     vapi_id = 
 
        VAPI id of this instance
 
*/
*/
 
 
section ethernet
section ethernet
  enabled = 1
  enabled  = 0
  baseaddr = 0x92000000
  baseaddr = 0x92000000
  irq = 4
  irq      = 4
  rtx_type = 0
  rtx_type = 0
  rxfile = "eth0.rx"
 
  txfile = "eth0.tx"
 
  sockif = "eth0"
 
end
end
 
 
/* GPIO SECTION
/* GPIO section
 
 
   This section configures the GPIOs
   enabled      = 0|1
 
   baseaddr     =  (default: 0)
     enabled = <0|1>
   irq          =  (default: 0)
        Enable/disable the peripheral.  By default if it is enabled.
   base_vapi_id =  (default: 0)
 
 
     baseaddr = 
 
        address of first GPIO register for this device
 
 
 
     irq = 
 
        irq number for this device
 
 
 
     base_vapi_id = 
 
        first VAPI id of this instance
 
        GPIO uses 8 consecutive VAPI IDs
 
*/
*/
 
 
section gpio
section gpio
  enabled = 1
  enabled      = 0
  baseaddr = 0x91000000
  baseaddr = 0x91000000
  irq = 3
  irq          = 3
  base_vapi_id = 0x0200
  base_vapi_id = 0x0200
end
end
 
 
/* VGA SECTION
/* VGA section
 
 
    This section configures the VGA/LCD controller
 
 
 
      enabled = <0|1>
 
        Enable/disable the peripheral.  By default if it is enabled.
 
 
 
      baseaddr = 
   enabled      = 0|1
        address of first VGA register
   baseaddr     =  (default: 0)
 
   irq          =  (default: 0)
      irq = 
   refresh_rate =  (default: cycles equivalent to 50Hz)
        irq number for this device
   filename     = "" (default: "vga_out))
 
 
      refresh_rate = 
 
        number of cycles between screen dumps
 
 
 
      filename = ""
 
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
 
*/
*/
 
 
section vga
section vga
  enabled = 1
  enabled      = 0
  baseaddr = 0x97100000
  baseaddr = 0x97100000
  irq = 8
  irq = 8
  refresh_rate = 100000
 
  filename = "primary"
 
end
end
 
 
/* FB SECTION
/* Frame buffer section
 
 
    This section configures the frame buffer
 
 
 
    enabled = <0|1>
 
      Enable/disable the peripheral.  By default if it is enabled.
 
 
 
    baseaddr = 
 
      base address of frame buffer
 
 
 
    refresh_rate = 
   enabled      = 0|1
      number of cycles between screen dumps
   baseaddr     =  (default: 0)
 
   refresh_rate =  (default: cycles equivalent to 50Hz)
    filename = ""
   filename     = "" (default: "fb_out))
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
 
*/
*/
 
 
section fb
section fb
  enabled = 1
  enabled      = 0
  baseaddr = 0x97000000
  baseaddr = 0x97000000
  refresh_rate = 1000000
 
  filename = "primary"
 
end
end
 
 
/* KBD SECTION
/* PS2 keyboard section
 
 
    This section configures the PS/2 compatible keyboard
    This section configures the PS/2 compatible keyboard
 
 
    enabled = <0|1>
    enabled  = 0|1
      Enable/disable the peripheral.  By default if it is enabled.
    baseaddr =  (default: 0)
 
    irq      =  (default: 0)
    baseaddr = 
    rxfile   = "" (default: "kbd_in")
      base address of the keyboard device
 
 
 
    irq = 
 
      irq number for this device
 
 
 
    rxfile = ""
 
      filename, where to read data from
 
*/
*/
 
 
section kbd
section kbd
  enabled = 1
  enabled  = 1
  baseaddr = 0x94000000
  baseaddr = 0x94000000
  irq = 5
  irq = 5
  rxfile = "kbd.rx"
 
end
end
 
 
/* ATA SECTION
/* ATA disc section
 
 
    This section configures the ATA/ATAPI host controller
 
 
 
      enabled = <0|1>
 
        Enable/disable the peripheral.  By default it is enabled.
 
 
 
      baseaddr = 
 
        address of first ATA register
 
 
 
      irq = 
 
        irq number for this device
 
 
 
      dev_id = 1/2/3
 
        Which OCIDEC version to imitate
 
 
 
      rev = 
 
        Revision of OCIDEC
 
 
 
      pio_mode0_t1 = <0-255>
 
        PIO T1 reset value
 
 
 
      pio_mode0_t2 = <0-255>
 
        PIO T2 reset value
 
 
 
      pio_mode0_t4 = <0-255>
 
        PIO T4 reset value
 
 
 
      pio_mode0_teoc = <0-255>
   enabled        = 0|1
        PIO Teoc reset value
   baseaddr       =  (default: 0)
 
   irq            =  (default: 0)
      dma_mode0_tm = <0-255>
   dev_id         = 1|2|3
        DMA Tm reset value
   rev            = 0-15 (default: 1)
 
   pio_mode0_t1   = 0-255 (default: 6)
      dma_mode0_td = <0-255>
   pio_mode0_t2   = 0-255 (default: 28)
        DMA Td reset value
   pio_mode0_t4   = 0-255 (default: 2)
 
   pio_mode0_teoc = 0-255 (default: 23)
      dma_mode0_teoc = <0-255>
   dma_mode0_tm   = 0-255 (default: 4)
        DMA Teoc reset value
   dma_mode0_td   = 0-255 (default: 21)
 
   dma_mode0_teoc = 0-255 (default: 21)
      Device specific
   device         = 0|1
 
 
        type = 
   Device specific:
          ata device 0 type
 
          0: NO_CONNECT: none (not connected)
      type     = 0|1|2
          1: FILE      : simulated harddisk
      file     = "" (default: "ata_file")
          2: LOCAL     : local system harddisk
      size     =  (default: 0)
 
      packet   = 0|1
        file = ""
      firmware = "" (default: "02207031")
          filename for simulated ATA device
      heads    =  (default: 7)
          valid only if dev_type0 == 1
      sectors  =  (default: 32)
 
      mwdma    = 2|1|0|-1
        size = 
      pio      = 4|3|2|1|0
          size of simulated hard-disk (in MBytes)
 
          valid only if dev_type0 == 1
 
 
 
        packet = 
 
          0: simulated ATA device does NOT implement PACKET command feature set
 
          1: simulated ATA device does implement PACKET command feature set
 
 
 
        firmware = 
 
          Firmware to report in `Identify device command'
 
 
 
        heads = 
 
          Number of default heads (-1)
 
 
 
        sectors = 
 
          Number of default sectors per track
 
 
 
        mwdma = 
 
          The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
 
 
 
        pio = 
 
          The highest supported pio mode; 4, 3, 2, 1, 0
 
 
 
   FIXME: irq number
 
*/
*/
 
 
section ata
section ata
  enabled = 1
  enabled  = 0
  baseaddr = 0x9e000000
  baseaddr = 0x9e000000
  irq = 15
  irq = 15
  dev_id = 1
 
  rev = 0
 
 
 
  pio_mode0_t1 = 6
 
  pio_mode0_t2 = 28
 
  pio_mode0_t4 = 2
 
  pio_mode0_teoc = 23
 
 
 
  dma_mode0_tm = 4
 
  dma_mode0_td = 21
 
  dma_mode0_teoc = 21
 
 
 
  device 0
  device 0
    type   = 1
    type   = 1
    file   = "/tmp/sim_atadev0"
 
    size   = 1
    size   = 1
    packet = 0
 
 
 
    heads  = 7
 
    sectors = 32
 
 
 
    firmware = "02207031"
 
    mwdma = 2
 
    pio = 4
 
  enddevice
 
 
 
  device 1
 
    type   = 0
 
    file   = ""
 
    size   = 0
 
    packet = 0
 
  enddevice
  enddevice
end
end
 
 
/* CUC SECTION
/* Generic peripheral section
 
 
    This section configures the OpenRISC Custom Unit Compiler
 
 
 
    memory_order = none/weak/strong/exact
 
      none   different memory ordering, even if there are dependencies,
 
             burst can be made, width can change
 
      weak   different memory ordering, if there cannot be dependencies
 
             burst can be made, width can change
 
      strong same memory ordering, burst can be made, width can change
 
      exact  exacltly the same memory ordering and widths
 
 
 
    calling_convention = 0/1
 
      whether programs follow OpenRISC calling conventions
 
 
 
    enable_bursts = 0/1
 
      whether burst are detected
 
 
 
    no_multicycle = 0/1
 
      if selected no multicycle logic paths will be generated
 
 
 
    timings_fn = ""
   enabled      = 0|1
 
   baseaddr     =  (default: 0)
 
   size         =  (default: 0)
 
   name         = "" (default: "anonymous external peripheral")
 
   byte_enabled = 1|0
 
   hw_enabled   = 1|0
 
   word_enabled = 1|0
*/
*/
 
section generic
section cuc
  enabled  = 0
  memory_order = weak
 
  calling_convention = 1
 
  enable_bursts = 1
 
  no_multicycle = 1
 
  timings_fn = "virtex.tim"
 
end
end
 
 
 
 

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