/* dumpverilog.c -- Dumps memory region as Verilog representation
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/* dumpverilog.c -- Dumps memory region as Verilog representation
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or as hex code
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or as hex code
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Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */
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/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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/* Package includes */
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/* Package includes */
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#include "sim-config.h"
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#include "sim-config.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "labels.h"
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#include "labels.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#define DW 32 /* Data width of mem model generated by */
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#define DW 32 /* Data width of mem model generated by */
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/* dumpverilog in bits */
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/* dumpverilog in bits */
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#define DWQ (DW/8) /* Same as DW but units are bytes */
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#define DWQ (DW/8) /* Same as DW but units are bytes */
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#define DISWIDTH 25 /* Width of disassembled message in bytes */
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#define DISWIDTH 25 /* Width of disassembled message in bytes */
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#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR, DISWIDTH) "\n"\
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#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR, DISWIDTH) "\n"\
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"include \"general.h\"\n\n"\
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"include \"general.h\"\n\n"\
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"`timescale 1ns/100ps\n\n"\
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"`timescale 1ns/100ps\n\n"\
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"// Simple dw-wide Sync SRAM with initial content generated by or1ksim.\n"\
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"// Simple dw-wide Sync SRAM with initial content generated by or1ksim.\n"\
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"// All control, data in and addr signals are sampled at rising clock edge \n"\
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"// All control, data in and addr signals are sampled at rising clock edge \n"\
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"// Data out is not registered. Address bits specify dw-word (narrowest \n"\
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"// Data out is not registered. Address bits specify dw-word (narrowest \n"\
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"// addressed data is not byte but dw-word !). \n"\
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"// addressed data is not byte but dw-word !). \n"\
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"// There are still some bugs in generated output (dump word aligned regions)\n\n"\
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"// There are still some bugs in generated output (dump word aligned regions)\n\n"\
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"module %s(clk, data, addr, ce, we, disout);\n\n"\
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"module %s(clk, data, addr, ce, we, disout);\n\n"\
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"parameter dw = 32;\n"\
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"parameter dw = 32;\n"\
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"parameter amin = %" PRIdREG ";\n\n"\
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"parameter amin = %" PRIdREG ";\n\n"\
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"parameter amax = %" PRIdREG ";\n\n"\
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"parameter amax = %" PRIdREG ";\n\n"\
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"input clk;\n"\
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"input clk;\n"\
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"inout [dw-1:0] data;\n"\
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"inout [dw-1:0] data;\n"\
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"input [31:0] addr;\n"\
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"input [31:0] addr;\n"\
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"input ce;\n"\
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"input ce;\n"\
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"input we;\n"\
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"input we;\n"\
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"output [%d:0] disout;\n\n"\
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"output [%d:0] disout;\n\n"\
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"reg [%d:0] disout;\n"\
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"reg [%d:0] disout;\n"\
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"reg [dw-1:0] mem [amax:amin];\n"\
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"reg [dw-1:0] mem [amax:amin];\n"\
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"reg [%d:0] dis [amax:amin];\n"\
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"reg [%d:0] dis [amax:amin];\n"\
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"reg [dw-1:0] dataout;\n"\
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"reg [dw-1:0] dataout;\n"\
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"tri [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n"\
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"tri [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n"\
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"initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH-1, DISWIDTH-1, DISWIDTH-1
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"initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH-1, DISWIDTH-1, DISWIDTH-1
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#define OR1K_MEM_VERILOG_FOOTER "\n\
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#define OR1K_MEM_VERILOG_FOOTER "\n\
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end\n\n\
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end\n\n\
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always @(posedge clk) begin\n\
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always @(posedge clk) begin\n\
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if (ce && ~we) begin\n\
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if (ce && ~we) begin\n\
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dataout <= #1 mem[addr];\n\
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dataout <= #1 mem[addr];\n\
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disout <= #1 dis[addr];\n\
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disout <= #1 dis[addr];\n\
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$display(\"or1k_mem: reading mem[%%0d]:%%h dis: %%0s\", addr, dataout, dis[addr]);\n\
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$display(\"or1k_mem: reading mem[%%0d]:%%h dis: %%0s\", addr, dataout, dis[addr]);\n\
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end else\n\
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end else\n\
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if (ce && we) begin\n\
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if (ce && we) begin\n\
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mem[addr] <= #1 data;\n\
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mem[addr] <= #1 data;\n\
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dis[addr] <= #1 \"(data)\";\n\
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dis[addr] <= #1 \"(data)\";\n\
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$display(\"or1k_mem: writing mem[%%0d]:%%h dis: %%0s\", addr, mem[addr], dis[addr]);\n\
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$display(\"or1k_mem: writing mem[%%0d]:%%h dis: %%0s\", addr, mem[addr], dis[addr]);\n\
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end\n\
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end\n\
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end\n\n\
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end\n\n\
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endmodule\n"
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endmodule\n"
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#define LABELEND_CHAR ":"
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#define LABELEND_CHAR ":"
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void
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void
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dumpverilog (char *verilog_modname, oraddr_t from, oraddr_t to)
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dumpverilog (char *verilog_modname, oraddr_t from, oraddr_t to)
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{
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{
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unsigned int i, done = 0;
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unsigned int i, done = 0;
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struct label_entry *tmp;
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struct label_entry *tmp;
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char dis[DISWIDTH + 100];
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char dis[DISWIDTH + 100];
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uint32_t insn;
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uint32_t insn;
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int index;
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int index;
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PRINTF ("// This file was generated by or1ksim version %s\n",
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PRINTF ("// This file was generated by or1ksim version %s\n",
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PACKAGE_VERSION);
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PACKAGE_VERSION);
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PRINTF (OR1K_MEM_VERILOG_HEADER
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PRINTF (OR1K_MEM_VERILOG_HEADER
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(verilog_modname, from / DWQ, to / DWQ, (DISWIDTH * 8)));
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(verilog_modname, from / DWQ, to / DWQ, (DISWIDTH * 8)));
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for (i = from; i < to; i++)
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for (i = from; i < to; i++)
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{
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{
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if (!(i & 3))
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if (!(i & 3))
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{
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{
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insn = eval_direct32 (i, 0, 0);
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insn = eval_direct32 (i, 0, 0);
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index = insn_decode (insn);
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index = or1ksim_insn_decode (insn);
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if (index >= 0)
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if (index >= 0)
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{
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{
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if (verify_memoryarea (i) && (tmp = get_label (i)))
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if (verify_memoryarea (i) && (tmp = get_label (i)))
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if (tmp)
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if (tmp)
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PRINTF ("\n//\t%s%s", tmp->name, LABELEND_CHAR);
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PRINTF ("\n//\t%s%s", tmp->name, LABELEND_CHAR);
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PRINTF ("\n\tmem['h%x] = %d'h%.8" PRIx32 ";", i / DWQ, DW,
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PRINTF ("\n\tmem['h%x] = %d'h%.8" PRIx32 ";", i / DWQ, DW,
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eval_direct32 (i, 0, 0));
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eval_direct32 (i, 0, 0));
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disassemble_insn (insn);
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or1ksim_disassemble_insn (insn);
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strcpy (dis, disassembled);
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strcpy (dis, or1ksim_disassembled);
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if (strlen (dis) < DISWIDTH)
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if (strlen (dis) < DISWIDTH)
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memset (dis + strlen (dis), ' ', DISWIDTH);
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memset (dis + strlen (dis), ' ', DISWIDTH);
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dis[DISWIDTH] = '\0';
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dis[DISWIDTH] = '\0';
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PRINTF ("\n\tdis['h%x] = {\"%s\"};", i / DWQ, dis);
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PRINTF ("\n\tdis['h%x] = {\"%s\"};", i / DWQ, dis);
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dis[0] = '\0';
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dis[0] = '\0';
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i += insn_len (index) - 1;
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i += or1ksim_insn_len (index) - 1;
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done = 1;
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done = 1;
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continue;
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continue;
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}
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}
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}
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}
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if (i % 64 == 0)
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if (i % 64 == 0)
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PRINTF ("\n");
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PRINTF ("\n");
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PRINTF ("\n\tmem['h%x] = 'h%.2x;", i / DWQ, eval_direct8 (i, 0, 0));
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PRINTF ("\n\tmem['h%x] = 'h%.2x;", i / DWQ, eval_direct8 (i, 0, 0));
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done = 1;
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done = 1;
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}
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}
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if (done)
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if (done)
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{
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{
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PRINTF (OR1K_MEM_VERILOG_FOOTER);
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PRINTF (OR1K_MEM_VERILOG_FOOTER);
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return;
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return;
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}
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}
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/* this needs to be fixed */
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/* this needs to be fixed */
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for (i = from; i < to; i++)
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for (i = from; i < to; i++)
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{
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{
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if (i % 8 == 0)
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if (i % 8 == 0)
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PRINTF ("\n%.8x: ", i);
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PRINTF ("\n%.8x: ", i);
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/* don't print ascii chars below 0x20. */
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/* don't print ascii chars below 0x20. */
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if (eval_direct32 (i, 0, 0) < 0x20)
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if (eval_direct32 (i, 0, 0) < 0x20)
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PRINTF ("0x%.2x ", (uint8_t) eval_direct32 (i, 0, 0));
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PRINTF ("0x%.2x ", (uint8_t) eval_direct32 (i, 0, 0));
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else
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else
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PRINTF ("0x%.2x'%c' ", (uint8_t) eval_direct32 (i, 0, 0),
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PRINTF ("0x%.2x'%c' ", (uint8_t) eval_direct32 (i, 0, 0),
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(char) eval_direct32 (i, 0, 0));
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(char) eval_direct32 (i, 0, 0));
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}
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}
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PRINTF (OR1K_MEM_VERILOG_FOOTER);
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PRINTF (OR1K_MEM_VERILOG_FOOTER);
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}
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}
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void
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void
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dumphex (oraddr_t from, oraddr_t to)
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dumphex (oraddr_t from, oraddr_t to)
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{
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{
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oraddr_t i;
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oraddr_t i;
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uint32_t insn;
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uint32_t insn;
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int index;
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int index;
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for (i = from; i < to; i++)
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for (i = from; i < to; i++)
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{
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{
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if (!(i & 3))
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if (!(i & 3))
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{
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{
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insn = eval_direct32 (i, 0, 0);
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insn = eval_direct32 (i, 0, 0);
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index = insn_decode (insn);
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index = or1ksim_insn_decode (insn);
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if (index >= 0)
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if (index >= 0)
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{
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{
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PRINTF ("%.8" PRIx32 "\n", eval_direct32 (i, 0, 0));
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PRINTF ("%.8" PRIx32 "\n", eval_direct32 (i, 0, 0));
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i += insn_len (index) - 1;
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i += or1ksim_insn_len (index) - 1;
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continue;
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continue;
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}
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}
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}
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}
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PRINTF ("%.2x\n", eval_direct8 (i, 0, 0));
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PRINTF ("%.2x\n", eval_direct8 (i, 0, 0));
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}
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}
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}
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}
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