OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [libsim.tests/] [int-edge.cfg] - Diff between revs 434 and 458

Only display areas with differences | Details | Blame | View Log

Rev 434 Rev 458
/* int-edge.cfg -- Or1ksim configuration script file for edge triggered PIC
/* int-edge.cfg -- Or1ksim configuration script file for edge triggered PIC
   Copyright (C) 2001, Marko Mlinar 
   Copyright (C) 2001, Marko Mlinar 
   Copyright (C) 2010 Embecosm Limited
   Copyright (C) 2010 Embecosm Limited
   Contributor Marko Mlinar 
   Contributor Marko Mlinar 
   Contributor Jeremy Bennett 
   Contributor Jeremy Bennett 
   This file is part of OpenRISC 1000 Architectural Simulator.
   This file is part of OpenRISC 1000 Architectural Simulator.
   This program is free software; you can redistribute it and/or modify it
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
   any later version.
   This program is distributed in the hope that it will be useful, but WITHOUT
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
   more details.
   You should have received a copy of the GNU General Public License along
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
   with this program.  If not, see .  */
section memory
section memory
  /*random_seed = 12345
  /*random_seed = 12345
  type = random*/
  type = random*/
  pattern = 0x00
  pattern = 0x00
  type = unknown /* Fastest */
  type = unknown /* Fastest */
  name = "FLASH"
  name = "FLASH"
  ce = 0
  ce = 0
  mc = 0
  mc = 0
  baseaddr = 0xf0000000
  baseaddr = 0xf0000000
  size = 0x00200000
  size = 0x00200000
  delayr = 10
  delayr = 10
  delayw = -1
  delayw = -1
end
end
section memory
section memory
  /*random_seed = 12345
  /*random_seed = 12345
  type = random*/
  type = random*/
  pattern = 0x00
  pattern = 0x00
  type = unknown /* Fastest */
  type = unknown /* Fastest */
  name = "RAM"
  name = "RAM"
  ce = 1
  ce = 1
  mc = 0
  mc = 0
  baseaddr = 0x00000000
  baseaddr = 0x00000000
  size = 0x00200000
  size = 0x00200000
  delayr = 2
  delayr = 2
  delayw = 4
  delayw = 4
end
end
section immu
section immu
  enabled = 1
  enabled = 1
  nsets = 64
  nsets = 64
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
  pagesize = 8192
  pagesize = 8192
end
end
section dmmu
section dmmu
  enabled = 1
  enabled = 1
  nsets = 64
  nsets = 64
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
  pagesize = 8192
  pagesize = 8192
end
end
section ic
section ic
  enabled = 1
  enabled = 1
  nsets = 256
  nsets = 256
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
  blocksize = 16
  blocksize = 16
end
end
section dc
section dc
  enabled = 1
  enabled = 1
  nsets = 256
  nsets = 256
  nways = 1
  nways = 1
  ustates = 2
  ustates = 2
  blocksize = 16
  blocksize = 16
end
end
section cpu
section cpu
  ver =   0x12
  ver =   0x12
  rev = 0x0001
  rev = 0x0001
  /* upr = */
  /* upr = */
  superscalar = 0
  superscalar = 0
  hazards = 0
  hazards = 0
  dependstats = 0
  dependstats = 0
end
end
section bpb
section bpb
  enabled = 0
  enabled = 0
  btic = 0
  btic = 0
end
end
section debug
section debug
/*  enabled = 1
/*  enabled = 1
  rsp_enabled = 1
  rsp_enabled = 1
  rsp_port = 51000*/
  rsp_port = 51000*/
end
end
section sim
section sim
  debug = 0
  debug = 0
  profile = 0
  profile = 0
  prof_fn = "sim.profile"
  prof_fn = "sim.profile"
  exe_log = 0
  exe_log = 0
  exe_log_type = software
  exe_log_type = software
  exe_log_fn = "executed.log"
  exe_log_fn = "executed.log"
end
end
 
 
section mc
 
  enabled = 1
 
  baseaddr = 0x93000000
 
  POC = 0x00000008                 /* Power on configuration register */
 
  index = 0
 
end
 
 
 
section dma
section dma
  baseaddr = 0xB8000000
  baseaddr = 0xB8000000
  irq = 4
  irq = 4
end
end
section ethernet
section ethernet
  enabled = 0
  enabled = 0
  baseaddr = 0x92000000
  baseaddr = 0x92000000
  irq = 4
  irq = 4
  rtx_type = "file"
  rtx_type = "file"
end
end
section VAPI
section VAPI
  enabled = 0
  enabled = 0
  server_port = 9998
  server_port = 9998
end
end
section fb
section fb
  enabled = 1
  enabled = 1
  baseaddr = 0x97000000
  baseaddr = 0x97000000
  refresh_rate = 10000
  refresh_rate = 10000
  filename = "primary"
  filename = "primary"
end
end
section kbd
section kbd
  enabled = 0
  enabled = 0
end
end
section pic
section pic
  enabled = 1
  enabled = 1
  edge_trigger = 1
  edge_trigger = 1
end
end
section generic
section generic
  enabled = 1
  enabled = 1
  baseaddr = 0x98000000
  baseaddr = 0x98000000
  size = 8
  size = 8
end
end
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.