/* except.s. Exception handling support for Or1k tests
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/* except.s. Exception handling support for Or1k tests
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#define reset _reset
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#define reset reset
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#define MC_CSR (0x00)
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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.section .stack
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.section .stack
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.space 0x1000
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.space 0x1000
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_stack:
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stack:
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.extern _reset_support
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.extern reset_support
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.extern _c_reset
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.extern c_reset
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.extern _excpt_buserr
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.extern excpt_buserr
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.extern _excpt_dpfault
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.extern excpt_dpfault
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.extern _excpt_ipfault
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.extern excpt_ipfault
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.extern _excpt_tick
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.extern excpt_tick
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.extern _excpt_align
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.extern excpt_align
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.extern _excpt_illinsn
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.extern excpt_illinsn
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.extern _excpt_int
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.extern excpt_int
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.extern _excpt_dtlbmiss
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.extern excpt_dtlbmiss
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.extern _excpt_itlbmiss
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.extern excpt_itlbmiss
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.extern _excpt_range
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.extern excpt_range
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.extern _excpt_syscall
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.extern excpt_syscall
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.extern _excpt_break
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.extern excpt_break
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.extern _excpt_trap
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.extern excpt_trap
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.section .except, "ax"
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.section .except, "ax"
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_buserr_vector:
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buserr_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_buserr)
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l.movhi r10,hi(excpt_buserr)
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l.ori r10,r10,lo(_excpt_buserr)
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l.ori r10,r10,lo(excpt_buserr)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_buserr_vector_end:
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buserr_vector_end:
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_dpfault_vector:
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dpfault_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_dpfault)
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l.movhi r10,hi(excpt_dpfault)
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l.ori r10,r10,lo(_excpt_dpfault)
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l.ori r10,r10,lo(excpt_dpfault)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dpfault_vector_end:
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dpfault_vector_end:
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_ipfault_vector:
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ipfault_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_ipfault)
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l.movhi r10,hi(excpt_ipfault)
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l.ori r10,r10,lo(_excpt_ipfault)
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l.ori r10,r10,lo(excpt_ipfault)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_ipfault_vector_end:
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ipfault_vector_end:
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_lpint_vector:
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lpint_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_tick)
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l.movhi r10,hi(excpt_tick)
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l.ori r10,r10,lo(_excpt_tick)
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l.ori r10,r10,lo(excpt_tick)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_lpint_vector_end:
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lpint_vector_end:
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_align_vector:
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align_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_align)
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l.movhi r10,hi(excpt_align)
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l.ori r10,r10,lo(_excpt_align)
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l.ori r10,r10,lo(excpt_align)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_align_vector_end:
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align_vector_end:
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_illinsn_vector:
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illinsn_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_illinsn)
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l.movhi r10,hi(excpt_illinsn)
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l.ori r10,r10,lo(_excpt_illinsn)
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l.ori r10,r10,lo(excpt_illinsn)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_illinsn_vector_end:
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illinsn_vector_end:
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_hpint_vector:
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hpint_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_int)
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l.movhi r10,hi(excpt_int)
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l.ori r10,r10,lo(_excpt_int)
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l.ori r10,r10,lo(excpt_int)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_hpint_vector_end:
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hpint_vector_end:
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_dtlbmiss_vector:
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dtlbmiss_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_dtlbmiss)
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l.movhi r10,hi(excpt_dtlbmiss)
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l.ori r10,r10,lo(_excpt_dtlbmiss)
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l.ori r10,r10,lo(excpt_dtlbmiss)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dtlbmiss_vector_end:
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dtlbmiss_vector_end:
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_itlbmiss_vector:
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itlbmiss_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_itlbmiss)
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l.movhi r10,hi(excpt_itlbmiss)
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l.ori r10,r10,lo(_excpt_itlbmiss)
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l.ori r10,r10,lo(excpt_itlbmiss)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_itlbmiss_vector_end:
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itlbmiss_vector_end:
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_range_vector:
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range_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_range)
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l.movhi r10,hi(excpt_range)
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l.ori r10,r10,lo(_excpt_range)
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l.ori r10,r10,lo(excpt_range)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_range_vector_end:
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range_vector_end:
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_syscall_vector:
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syscall_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_syscall)
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l.movhi r10,hi(excpt_syscall)
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l.ori r10,r10,lo(_excpt_syscall)
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l.ori r10,r10,lo(excpt_syscall)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_syscall_vector_end:
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syscall_vector_end:
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|
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_break_vector:
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break_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_break)
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l.movhi r10,hi(excpt_break)
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l.ori r10,r10,lo(_excpt_break)
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l.ori r10,r10,lo(excpt_break)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_break_vector_end:
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break_vector_end:
|
|
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_trap_vector:
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trap_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(_excpt_trap)
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l.movhi r10,hi(excpt_trap)
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l.ori r10,r10,lo(_excpt_trap)
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l.ori r10,r10,lo(excpt_trap)
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l.jr r9
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l.jr r9
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l.nop
|
l.nop
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_trap_vector_end:
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trap_vector_end:
|
|
|
/* Our special text section is used to guarantee this code goes first
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/* Our special text section is used to guarantee this code goes first
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when linking. */
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when linking. */
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.section .except-text
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.section .except-text
|
|
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.org 0x100
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.org 0x100
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.align 4
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.align 4
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_reset_vector:
|
reset_vector:
|
l.addi r2,r0,0x0
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l.addi r2,r0,0x0
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l.addi r3,r0,0x0
|
l.addi r3,r0,0x0
|
l.addi r4,r0,0x0
|
l.addi r4,r0,0x0
|
l.addi r5,r0,0x0
|
l.addi r5,r0,0x0
|
l.addi r6,r0,0x0
|
l.addi r6,r0,0x0
|
l.addi r7,r0,0x0
|
l.addi r7,r0,0x0
|
l.addi r8,r0,0x0
|
l.addi r8,r0,0x0
|
l.addi r9,r0,0x0
|
l.addi r9,r0,0x0
|
l.addi r10,r0,0x0
|
l.addi r10,r0,0x0
|
l.addi r11,r0,0x0
|
l.addi r11,r0,0x0
|
l.addi r12,r0,0x0
|
l.addi r12,r0,0x0
|
l.addi r13,r0,0x0
|
l.addi r13,r0,0x0
|
l.addi r14,r0,0x0
|
l.addi r14,r0,0x0
|
l.addi r15,r0,0x0
|
l.addi r15,r0,0x0
|
l.addi r16,r0,0x0
|
l.addi r16,r0,0x0
|
l.addi r17,r0,0x0
|
l.addi r17,r0,0x0
|
l.addi r18,r0,0x0
|
l.addi r18,r0,0x0
|
l.addi r19,r0,0x0
|
l.addi r19,r0,0x0
|
l.addi r20,r0,0x0
|
l.addi r20,r0,0x0
|
l.addi r21,r0,0x0
|
l.addi r21,r0,0x0
|
l.addi r22,r0,0x0
|
l.addi r22,r0,0x0
|
l.addi r23,r0,0x0
|
l.addi r23,r0,0x0
|
l.addi r24,r0,0x0
|
l.addi r24,r0,0x0
|
l.addi r25,r0,0x0
|
l.addi r25,r0,0x0
|
l.addi r26,r0,0x0
|
l.addi r26,r0,0x0
|
l.addi r27,r0,0x0
|
l.addi r27,r0,0x0
|
l.addi r28,r0,0x0
|
l.addi r28,r0,0x0
|
l.addi r29,r0,0x0
|
l.addi r29,r0,0x0
|
l.addi r30,r0,0x0
|
l.addi r30,r0,0x0
|
l.addi r31,r0,0x0
|
l.addi r31,r0,0x0
|
|
|
l.movhi r3,hi(start)
|
l.movhi r3,hi(start)
|
l.ori r3,r3,lo(start)
|
l.ori r3,r3,lo(start)
|
l.jr r3
|
l.jr r3
|
l.nop
|
l.nop
|
.global start
|
.global start
|
start:
|
start:
|
l.jal _init_mc
|
l.jal init_mc
|
l.nop
|
l.nop
|
|
|
l.movhi r1,hi(_stack)
|
l.movhi r1,hi(stack)
|
l.ori r1,r1,lo(_stack)
|
l.ori r1,r1,lo(stack)
|
|
|
/* Setup exception wrappers */
|
/* Setup exception wrappers */
|
l.movhi r3,hi(_src_beg)
|
l.movhi r3,hi(_src_beg)
|
l.ori r3,r3,lo(_src_beg)
|
l.ori r3,r3,lo(_src_beg)
|
l.addi r7,r0,0x100
|
l.addi r7,r0,0x100
|
|
|
1: l.addi r7,r7,0x100
|
1: l.addi r7,r7,0x100
|
l.sfeqi r7,0xf00
|
l.sfeqi r7,0xf00
|
l.bf 1f
|
l.bf 1f
|
l.nop
|
l.nop
|
l.addi r4,r7,0
|
l.addi r4,r7,0
|
l.addi r5,r0,0
|
l.addi r5,r0,0
|
2:
|
2:
|
l.lwz r6,0(r3)
|
l.lwz r6,0(r3)
|
l.sw 0(r4),r6
|
l.sw 0(r4),r6
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
l.addi r4,r4,4
|
l.addi r4,r4,4
|
l.addi r5,r5,1
|
l.addi r5,r5,1
|
l.sfeqi r5,9
|
l.sfeqi r5,9
|
l.bf 1b
|
l.bf 1b
|
l.nop
|
l.nop
|
l.j 2b
|
l.j 2b
|
l.nop
|
l.nop
|
1:
|
1:
|
/* Copy data section */
|
/* Copy data section */
|
l.movhi r4,hi(_dst_beg)
|
l.movhi r4,hi(_dst_beg)
|
l.ori r4,r4,lo(_dst_beg)
|
l.ori r4,r4,lo(_dst_beg)
|
l.movhi r5,hi(_dst_end)
|
l.movhi r5,hi(_dst_end)
|
l.ori r5,r5,lo(_dst_end)
|
l.ori r5,r5,lo(_dst_end)
|
l.sub r5,r5,r4
|
l.sub r5,r5,r4
|
l.sfeqi r5,0
|
l.sfeqi r5,0
|
l.bf 2f
|
l.bf 2f
|
l.nop
|
l.nop
|
1: l.lwz r6,0(r3)
|
1: l.lwz r6,0(r3)
|
l.sw 0(r4),r6
|
l.sw 0(r4),r6
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
l.addi r4,r4,4
|
l.addi r4,r4,4
|
l.addi r5,r5,-4
|
l.addi r5,r5,-4
|
l.sfgtsi r5,0
|
l.sfgtsi r5,0
|
l.bf 1b
|
l.bf 1b
|
l.nop
|
l.nop
|
|
|
2:
|
2:
|
|
|
l.movhi r2,hi(reset)
|
l.movhi r2,hi(reset)
|
l.ori r2,r2,lo(reset)
|
l.ori r2,r2,lo(reset)
|
l.jr r2
|
l.jr r2
|
l.nop
|
l.nop
|
|
|
_init_mc:
|
init_mc:
|
|
|
l.movhi r3,hi(MC_BASE_ADDR)
|
l.movhi r3,hi(MC_BASE_ADDR)
|
l.ori r3,r3,lo(MC_BASE_ADDR)
|
l.ori r3,r3,lo(MC_BASE_ADDR)
|
|
|
l.addi r4,r3,MC_CSC(0)
|
l.addi r4,r3,MC_CSC(0)
|
l.movhi r5,hi(FLASH_BASE_ADDR)
|
l.movhi r5,hi(FLASH_BASE_ADDR)
|
l.srai r5,r5,6
|
l.srai r5,r5,6
|
l.ori r5,r5,0x0025
|
l.ori r5,r5,0x0025
|
l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.addi r4,r3,MC_TMS(0)
|
l.addi r4,r3,MC_TMS(0)
|
l.movhi r5,hi(FLASH_TMS_VAL)
|
l.movhi r5,hi(FLASH_TMS_VAL)
|
l.ori r5,r5,lo(FLASH_TMS_VAL)
|
l.ori r5,r5,lo(FLASH_TMS_VAL)
|
l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.addi r4,r3,MC_BA_MASK
|
l.addi r4,r3,MC_BA_MASK
|
l.addi r5,r0,MC_MASK_VAL
|
l.addi r5,r0,MC_MASK_VAL
|
l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.addi r4,r3,MC_CSR
|
l.addi r4,r3,MC_CSR
|
l.movhi r5,hi(MC_CSR_VAL)
|
l.movhi r5,hi(MC_CSR_VAL)
|
l.ori r5,r5,lo(MC_CSR_VAL)
|
l.ori r5,r5,lo(MC_CSR_VAL)
|
l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.addi r4,r3,MC_TMS(1)
|
l.addi r4,r3,MC_TMS(1)
|
l.movhi r5,hi(SDRAM_TMS_VAL)
|
l.movhi r5,hi(SDRAM_TMS_VAL)
|
l.ori r5,r5,lo(SDRAM_TMS_VAL)
|
l.ori r5,r5,lo(SDRAM_TMS_VAL)
|
l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.addi r4,r3,MC_CSC(1)
|
l.addi r4,r3,MC_CSC(1)
|
l.movhi r5,hi(SDRAM_BASE_ADDR)
|
l.movhi r5,hi(SDRAM_BASE_ADDR)
|
l.srai r5,r5,6
|
l.srai r5,r5,6
|
l.ori r5,r5,0x0411
|
l.ori r5,r5,0x0411
|
l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
store_regs:
|
store_regs:
|
l.sw 0x00(r1),r2
|
l.sw 0x00(r1),r2
|
l.sw 0x04(r1),r3
|
l.sw 0x04(r1),r3
|
l.sw 0x08(r1),r4
|
l.sw 0x08(r1),r4
|
l.sw 0x0c(r1),r5
|
l.sw 0x0c(r1),r5
|
l.sw 0x10(r1),r6
|
l.sw 0x10(r1),r6
|
l.sw 0x14(r1),r7
|
l.sw 0x14(r1),r7
|
l.sw 0x18(r1),r8
|
l.sw 0x18(r1),r8
|
l.sw 0x24(r1),r11
|
l.sw 0x24(r1),r11
|
l.sw 0x28(r1),r12
|
l.sw 0x28(r1),r12
|
l.sw 0x2c(r1),r13
|
l.sw 0x2c(r1),r13
|
l.sw 0x30(r1),r14
|
l.sw 0x30(r1),r14
|
l.sw 0x34(r1),r15
|
l.sw 0x34(r1),r15
|
l.sw 0x38(r1),r16
|
l.sw 0x38(r1),r16
|
l.sw 0x3c(r1),r17
|
l.sw 0x3c(r1),r17
|
l.sw 0x40(r1),r18
|
l.sw 0x40(r1),r18
|
l.sw 0x44(r1),r19
|
l.sw 0x44(r1),r19
|
l.sw 0x48(r1),r20
|
l.sw 0x48(r1),r20
|
l.sw 0x4c(r1),r21
|
l.sw 0x4c(r1),r21
|
l.sw 0x50(r1),r22
|
l.sw 0x50(r1),r22
|
l.sw 0x54(r1),r23
|
l.sw 0x54(r1),r23
|
l.sw 0x58(r1),r24
|
l.sw 0x58(r1),r24
|
l.sw 0x5c(r1),r25
|
l.sw 0x5c(r1),r25
|
l.sw 0x60(r1),r26
|
l.sw 0x60(r1),r26
|
l.sw 0x64(r1),r27
|
l.sw 0x64(r1),r27
|
l.sw 0x68(r1),r28
|
l.sw 0x68(r1),r28
|
l.sw 0x6c(r1),r29
|
l.sw 0x6c(r1),r29
|
l.sw 0x70(r1),r30
|
l.sw 0x70(r1),r30
|
l.sw 0x74(r1),r31
|
l.sw 0x74(r1),r31
|
l.movhi r9,hi(end_except)
|
l.movhi r9,hi(end_except)
|
l.ori r9,r9,lo(end_except)
|
l.ori r9,r9,lo(end_except)
|
l.lwz r10,0(r10)
|
l.lwz r10,0(r10)
|
l.jr r10
|
l.jr r10
|
l.nop
|
l.nop
|
|
|
end_except:
|
end_except:
|
l.lwz r2,0x00(r1)
|
l.lwz r2,0x00(r1)
|
l.lwz r3,0x04(r1)
|
l.lwz r3,0x04(r1)
|
l.lwz r4,0x08(r1)
|
l.lwz r4,0x08(r1)
|
l.lwz r5,0x0c(r1)
|
l.lwz r5,0x0c(r1)
|
l.lwz r6,0x10(r1)
|
l.lwz r6,0x10(r1)
|
l.lwz r7,0x14(r1)
|
l.lwz r7,0x14(r1)
|
l.lwz r8,0x18(r1)
|
l.lwz r8,0x18(r1)
|
l.lwz r9,0x1c(r1)
|
l.lwz r9,0x1c(r1)
|
l.lwz r10,0x20(r1)
|
l.lwz r10,0x20(r1)
|
l.lwz r11,0x24(r1)
|
l.lwz r11,0x24(r1)
|
l.lwz r12,0x28(r1)
|
l.lwz r12,0x28(r1)
|
l.lwz r13,0x2c(r1)
|
l.lwz r13,0x2c(r1)
|
l.lwz r14,0x30(r1)
|
l.lwz r14,0x30(r1)
|
l.lwz r15,0x34(r1)
|
l.lwz r15,0x34(r1)
|
l.lwz r16,0x38(r1)
|
l.lwz r16,0x38(r1)
|
l.lwz r17,0x3c(r1)
|
l.lwz r17,0x3c(r1)
|
l.lwz r18,0x40(r1)
|
l.lwz r18,0x40(r1)
|
l.lwz r19,0x44(r1)
|
l.lwz r19,0x44(r1)
|
l.lwz r20,0x48(r1)
|
l.lwz r20,0x48(r1)
|
l.lwz r21,0x4c(r1)
|
l.lwz r21,0x4c(r1)
|
l.lwz r22,0x50(r1)
|
l.lwz r22,0x50(r1)
|
l.lwz r23,0x54(r1)
|
l.lwz r23,0x54(r1)
|
l.lwz r24,0x58(r1)
|
l.lwz r24,0x58(r1)
|
l.lwz r25,0x5c(r1)
|
l.lwz r25,0x5c(r1)
|
l.lwz r26,0x60(r1)
|
l.lwz r26,0x60(r1)
|
l.lwz r27,0x64(r1)
|
l.lwz r27,0x64(r1)
|
l.lwz r28,0x68(r1)
|
l.lwz r28,0x68(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r31,0x74(r1)
|
l.lwz r31,0x74(r1)
|
l.addi r1,r1,120
|
l.addi r1,r1,120
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
