/* except-mc.ld. Linker script for Or1ksim memory controller test programs
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/* except-mc.ld. Linker script for Or1ksim memory controller test programs
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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MEMORY
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MEMORY
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{
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{
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except : ORIGIN = 0x00000000, LENGTH = 0x00002000
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except : ORIGIN = 0x00000000, LENGTH = 0x00002000
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flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000
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flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000
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ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
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ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
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}
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}
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ENTRY (_reset_vector)
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ENTRY (_reset_vector)
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SECTIONS
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SECTIONS
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{
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{
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.except :
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.except :
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{
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{
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*(.except)
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*(.except)
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_src_beg = .;
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_src_beg = .;
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} > except
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} > except
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.text :
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.text :
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AT ( ADDR (.except) + SIZEOF (.except) )
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AT ( ADDR (.except) + SIZEOF (.except) )
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{
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{
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_dst_beg = .;
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_dst_beg = .;
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*(.text)
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*(.text)
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*(.rodata)
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*(.rodata)
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*(.rodata.*)
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} > ram
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} > ram
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.data :
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.data :
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AT ( ADDR (.except) + SIZEOF (.except) + SIZEOF (.text))
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AT ( ADDR (.except) + SIZEOF (.except) + SIZEOF (.text))
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{
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{
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*(.data)
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*(.data)
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*(.data.rel)
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*(.data.rel)
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*(.data.rel.local)
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*(.data.rel.local)
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_dst_end = .;
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_dst_end = .;
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} > ram
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} > ram
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.bss :
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.bss :
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{
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{
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*(.bss)
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*(.bss)
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} > ram
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} > ram
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.stack ALIGN(0x10) (NOLOAD):
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.stack ALIGN(0x10) (NOLOAD):
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{
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{
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*(.stack)
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*(.stack)
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_ram_end = .;
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_ram_end = .;
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} > ram
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} > ram
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}
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}
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