/* except-test-s.S. Machine code support for test of Or1ksim exception handling
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/* except-test-s.S. Machine code support for test of Or1ksim exception handling
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#define reset main
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#define reset main
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.global except_basic
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.global except_basic
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.global lo_dmmu_en
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.global lo_dmmu_en
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.global lo_immu_en
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.global lo_immu_en
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.global call
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.global call
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.global call_with_int
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.global call_with_int
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.global load_acc_32
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.global load_acc_32
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.global load_acc_16
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.global load_acc_16
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.global store_acc_32
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.global store_acc_32
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.global store_acc_16
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.global store_acc_16
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.global load_b_acc_32
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.global load_b_acc_32
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.global trap
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.global trap
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.global b_trap
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.global b_trap
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.global range
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.global range
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.global b_range
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.global b_range
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.global int_trigger
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.global int_trigger
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.global int_loop
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.global int_loop
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.global jump_back
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.global jump_back
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|
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.section .stack
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.section .stack
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.space 0x1000
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.space 0x1000
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stack:
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stack:
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|
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.extern reset_support
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.extern reset_support
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.extern c_reset
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.extern c_reset
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.extern excpt_buserr
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.extern excpt_buserr
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.extern excpt_dpfault
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.extern excpt_dpfault
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.extern excpt_ipfault
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.extern excpt_ipfault
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.extern excpt_tick
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.extern excpt_tick
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.extern excpt_align
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.extern excpt_align
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.extern excpt_illinsn
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.extern excpt_illinsn
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.extern excpt_int
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.extern excpt_int
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.extern excpt_dtlbmiss
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.extern excpt_dtlbmiss
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.extern excpt_itlbmiss
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.extern excpt_itlbmiss
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.extern excpt_range
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.extern excpt_range
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.extern excpt_syscall
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.extern excpt_syscall
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.extern excpt_break
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.extern excpt_break
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.extern excpt_trap
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.extern excpt_trap
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/* Our special text section is used to guarantee this code goes first
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/* Our special text section is used to guarantee this code goes first
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when linking. */
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when linking. */
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.section .except,"ax"
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.section .except,"ax"
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.org 0x100
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.org 0x100
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reset_vector:
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reset_vector:
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l.nop
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l.nop
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l.nop
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l.nop
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// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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// and indeed it is not when simulating the or1200 Verilog core.
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l.andi r0,r0,0x0
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|
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l.addi r2,r0,0x0
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l.addi r2,r0,0x0
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l.addi r3,r0,0x0
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l.addi r3,r0,0x0
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l.addi r4,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r6,r0,0x0
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l.addi r7,r0,0x0
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l.addi r7,r0,0x0
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l.addi r8,r0,0x0
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l.addi r8,r0,0x0
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l.addi r9,r0,0x0
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l.addi r9,r0,0x0
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l.addi r10,r0,0x0
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l.addi r10,r0,0x0
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l.addi r11,r0,0x0
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l.addi r11,r0,0x0
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l.addi r12,r0,0x0
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l.addi r12,r0,0x0
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l.addi r13,r0,0x0
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l.addi r13,r0,0x0
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l.addi r14,r0,0x0
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l.addi r14,r0,0x0
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l.addi r15,r0,0x0
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l.addi r15,r0,0x0
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l.addi r16,r0,0x0
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l.addi r16,r0,0x0
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l.addi r17,r0,0x0
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l.addi r17,r0,0x0
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l.addi r18,r0,0x0
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l.addi r18,r0,0x0
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l.addi r19,r0,0x0
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l.addi r19,r0,0x0
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l.addi r20,r0,0x0
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l.addi r20,r0,0x0
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l.addi r21,r0,0x0
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l.addi r21,r0,0x0
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l.addi r22,r0,0x0
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l.addi r22,r0,0x0
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l.addi r23,r0,0x0
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l.addi r23,r0,0x0
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l.addi r24,r0,0x0
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l.addi r24,r0,0x0
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l.addi r25,r0,0x0
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l.addi r25,r0,0x0
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l.addi r26,r0,0x0
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l.addi r26,r0,0x0
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l.addi r27,r0,0x0
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l.addi r27,r0,0x0
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l.addi r28,r0,0x0
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l.addi r28,r0,0x0
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l.addi r29,r0,0x0
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l.addi r29,r0,0x0
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l.addi r30,r0,0x0
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l.addi r30,r0,0x0
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l.addi r31,r0,0x0
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l.addi r31,r0,0x0
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|
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l.movhi r3,hi(start)
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l.movhi r3,hi(start)
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l.ori r3,r3,lo(start)
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l.ori r3,r3,lo(start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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|
|
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.org 0x200
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.org 0x200
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buserr_vector:
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buserr_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_buserr)
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l.movhi r10,hi(excpt_buserr)
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l.ori r10,r10,lo(excpt_buserr)
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l.ori r10,r10,lo(excpt_buserr)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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l.nop
|
l.nop
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l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
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l.nop
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l.nop
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|
|
.org 0x300
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.org 0x300
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dpfault_vector:
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dpfault_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_dpfault)
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l.movhi r10,hi(excpt_dpfault)
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l.ori r10,r10,lo(excpt_dpfault)
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l.ori r10,r10,lo(excpt_dpfault)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.org 0x400
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.org 0x400
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ipfault_vector:
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ipfault_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_ipfault)
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l.movhi r10,hi(excpt_ipfault)
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l.ori r10,r10,lo(excpt_ipfault)
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l.ori r10,r10,lo(excpt_ipfault)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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|
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.org 0x500
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.org 0x500
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tick_vector:
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tick_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_tick)
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l.movhi r10,hi(excpt_tick)
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l.ori r10,r10,lo(excpt_tick)
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l.ori r10,r10,lo(excpt_tick)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
|
l.nop
|
l.nop
|
l.nop
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l.nop
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l.nop
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l.nop
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|
|
.org 0x600
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.org 0x600
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align_vector:
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align_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_align)
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l.movhi r10,hi(excpt_align)
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l.ori r10,r10,lo(excpt_align)
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l.ori r10,r10,lo(excpt_align)
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l.jr r9
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l.jr r9
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l.nop
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l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
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l.nop
|
|
|
.org 0x700
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.org 0x700
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illinsn_vector:
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illinsn_vector:
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l.addi r1,r1,-120
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l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_illinsn)
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l.movhi r10,hi(excpt_illinsn)
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l.ori r10,r10,lo(excpt_illinsn)
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l.ori r10,r10,lo(excpt_illinsn)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
.org 0x800
|
.org 0x800
|
int_vector:
|
int_vector:
|
l.addi r1,r1,-120
|
l.addi r1,r1,-120
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
|
l.sw 0x20(r1),r10
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l.movhi r9,hi(store_regs)
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l.movhi r9,hi(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.ori r9,r9,lo(store_regs)
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l.movhi r10,hi(excpt_int)
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l.movhi r10,hi(excpt_int)
|
l.ori r10,r10,lo(excpt_int)
|
l.ori r10,r10,lo(excpt_int)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
.org 0x900
|
.org 0x900
|
dtlbmiss_vector:
|
dtlbmiss_vector:
|
l.addi r1,r1,-120
|
l.addi r1,r1,-120
|
l.sw 0x1c(r1),r9
|
l.sw 0x1c(r1),r9
|
l.sw 0x20(r1),r10
|
l.sw 0x20(r1),r10
|
l.movhi r9,hi(store_regs)
|
l.movhi r9,hi(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.movhi r10,hi(excpt_dtlbmiss)
|
l.movhi r10,hi(excpt_dtlbmiss)
|
l.ori r10,r10,lo(excpt_dtlbmiss)
|
l.ori r10,r10,lo(excpt_dtlbmiss)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
.org 0xa00
|
.org 0xa00
|
itlbmiss_vector:
|
itlbmiss_vector:
|
l.addi r1,r1,-120
|
l.addi r1,r1,-120
|
l.sw 0x1c(r1),r9
|
l.sw 0x1c(r1),r9
|
l.sw 0x20(r1),r10
|
l.sw 0x20(r1),r10
|
l.movhi r9,hi(store_regs)
|
l.movhi r9,hi(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.movhi r10,hi(excpt_itlbmiss)
|
l.movhi r10,hi(excpt_itlbmiss)
|
l.ori r10,r10,lo(excpt_itlbmiss)
|
l.ori r10,r10,lo(excpt_itlbmiss)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
.org 0xb00
|
.org 0xb00
|
range_vector:
|
range_vector:
|
l.addi r1,r1,-120
|
l.addi r1,r1,-120
|
l.sw 0x1c(r1),r9
|
l.sw 0x1c(r1),r9
|
l.sw 0x20(r1),r10
|
l.sw 0x20(r1),r10
|
l.movhi r9,hi(store_regs)
|
l.movhi r9,hi(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.movhi r10,hi(excpt_range)
|
l.movhi r10,hi(excpt_range)
|
l.ori r10,r10,lo(excpt_range)
|
l.ori r10,r10,lo(excpt_range)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
.org 0xc00
|
.org 0xc00
|
syscall_vector:
|
syscall_vector:
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
|
|
l.mfspr r4,r0,SPR_SR
|
l.mfspr r4,r0,SPR_SR
|
l.andi r4,r4,7
|
l.andi r4,r4,7
|
l.add r6,r0,r4
|
l.add r6,r0,r4
|
|
|
l.mfspr r4,r0,SPR_EPCR_BASE
|
l.mfspr r4,r0,SPR_EPCR_BASE
|
l.movhi r5,hi(sys1)
|
l.movhi r5,hi(sys1)
|
l.ori r5,r5,lo(sys1)
|
l.ori r5,r5,lo(sys1)
|
l.sub r5,r4,r5
|
l.sub r5,r4,r5
|
|
|
l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */
|
l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */
|
l.ori r4,r4,SPR_SR_SM
|
l.ori r4,r4,SPR_SR_SM
|
l.mtspr r0,r4,SPR_ESR_BASE
|
l.mtspr r0,r4,SPR_ESR_BASE
|
|
|
l.movhi r4,hi(sys2)
|
l.movhi r4,hi(sys2)
|
l.ori r4,r4,lo(sys2)
|
l.ori r4,r4,lo(sys2)
|
l.mtspr r0,r4,SPR_EPCR_BASE
|
l.mtspr r0,r4,SPR_EPCR_BASE
|
|
|
l.rfe
|
l.rfe
|
l.addi r3,r3,8
|
l.addi r3,r3,8
|
|
|
.org 0xd00
|
.org 0xd00
|
break_vector:
|
break_vector:
|
l.addi r1,r1,-120
|
l.addi r1,r1,-120
|
l.sw 0x1c(r1),r9
|
l.sw 0x1c(r1),r9
|
l.sw 0x20(r1),r10
|
l.sw 0x20(r1),r10
|
l.movhi r9,hi(store_regs)
|
l.movhi r9,hi(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.movhi r10,hi(excpt_break)
|
l.movhi r10,hi(excpt_break)
|
l.ori r10,r10,lo(excpt_break)
|
l.ori r10,r10,lo(excpt_break)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
.org 0xe00
|
.org 0xe00
|
trap_vector:
|
trap_vector:
|
l.addi r1,r1,-120
|
l.addi r1,r1,-120
|
l.sw 0x1c(r1),r9
|
l.sw 0x1c(r1),r9
|
l.sw 0x20(r1),r10
|
l.sw 0x20(r1),r10
|
l.movhi r9,hi(store_regs)
|
l.movhi r9,hi(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.ori r9,r9,lo(store_regs)
|
l.movhi r10,hi(excpt_trap)
|
l.movhi r10,hi(excpt_trap)
|
l.ori r10,r10,lo(excpt_trap)
|
l.ori r10,r10,lo(excpt_trap)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
|
|
|
|
.section .text
|
.section .text
|
|
|
start:
|
start:
|
|
|
l.movhi r1,hi(stack)
|
l.movhi r1,hi(stack)
|
l.ori r1,r1,lo(stack)
|
l.ori r1,r1,lo(stack)
|
l.ori r2,r1,0
|
l.ori r2,r1,0
|
|
|
bss_clear:
|
bss_clear:
|
/* Clear BSS */
|
/* Clear BSS */
|
l.movhi r3, hi(_bstart)
|
l.movhi r3, hi(_bstart)
|
l.ori r3, r3, lo(_bstart)
|
l.ori r3, r3, lo(_bstart)
|
l.movhi r4, hi(_bend)
|
l.movhi r4, hi(_bend)
|
l.ori r4, r4, lo(_bend)
|
l.ori r4, r4, lo(_bend)
|
bss_clear_loop:
|
bss_clear_loop:
|
l.sw 0(r3), r0
|
l.sw 0(r3), r0
|
l.sfgtu r3, r4
|
l.sfgtu r3, r4
|
l.bnf bss_clear_loop
|
l.bnf bss_clear_loop
|
l.addi r3, r3, 4
|
l.addi r3, r3, 4
|
|
|
|
|
l.movhi r3,hi(reset)
|
l.movhi r3,hi(reset)
|
l.ori r3,r3,lo(reset)
|
l.ori r3,r3,lo(reset)
|
l.jr r3
|
l.jr r3
|
l.nop
|
l.nop
|
|
|
store_regs:
|
store_regs:
|
l.sw 0x00(r1),r2
|
l.sw 0x00(r1),r2
|
l.sw 0x04(r1),r3
|
l.sw 0x04(r1),r3
|
l.sw 0x08(r1),r4
|
l.sw 0x08(r1),r4
|
l.sw 0x0c(r1),r5
|
l.sw 0x0c(r1),r5
|
l.sw 0x10(r1),r6
|
l.sw 0x10(r1),r6
|
l.sw 0x14(r1),r7
|
l.sw 0x14(r1),r7
|
l.sw 0x18(r1),r8
|
l.sw 0x18(r1),r8
|
l.sw 0x24(r1),r11
|
l.sw 0x24(r1),r11
|
l.sw 0x28(r1),r12
|
l.sw 0x28(r1),r12
|
l.sw 0x2c(r1),r13
|
l.sw 0x2c(r1),r13
|
l.sw 0x30(r1),r14
|
l.sw 0x30(r1),r14
|
l.sw 0x34(r1),r15
|
l.sw 0x34(r1),r15
|
l.sw 0x38(r1),r16
|
l.sw 0x38(r1),r16
|
l.sw 0x3c(r1),r17
|
l.sw 0x3c(r1),r17
|
l.sw 0x40(r1),r18
|
l.sw 0x40(r1),r18
|
l.sw 0x44(r1),r19
|
l.sw 0x44(r1),r19
|
l.sw 0x48(r1),r20
|
l.sw 0x48(r1),r20
|
l.sw 0x4c(r1),r21
|
l.sw 0x4c(r1),r21
|
l.sw 0x50(r1),r22
|
l.sw 0x50(r1),r22
|
l.sw 0x54(r1),r23
|
l.sw 0x54(r1),r23
|
l.sw 0x58(r1),r24
|
l.sw 0x58(r1),r24
|
l.sw 0x5c(r1),r25
|
l.sw 0x5c(r1),r25
|
l.sw 0x60(r1),r26
|
l.sw 0x60(r1),r26
|
l.sw 0x64(r1),r27
|
l.sw 0x64(r1),r27
|
l.sw 0x68(r1),r28
|
l.sw 0x68(r1),r28
|
l.sw 0x6c(r1),r29
|
l.sw 0x6c(r1),r29
|
l.sw 0x70(r1),r30
|
l.sw 0x70(r1),r30
|
l.sw 0x74(r1),r31
|
l.sw 0x74(r1),r31
|
|
|
l.mfspr r3,r0,SPR_EPCR_BASE
|
l.mfspr r3,r0,SPR_EPCR_BASE
|
l.movhi r4,hi(except_pc)
|
l.movhi r4,hi(except_pc)
|
l.ori r4,r4,lo(except_pc)
|
l.ori r4,r4,lo(except_pc)
|
l.sw 0(r4),r3
|
l.sw 0(r4),r3
|
|
|
l.mfspr r3,r0,SPR_EEAR_BASE
|
l.mfspr r3,r0,SPR_EEAR_BASE
|
l.movhi r4,hi(except_ea)
|
l.movhi r4,hi(except_ea)
|
l.ori r4,r4,lo(except_ea)
|
l.ori r4,r4,lo(except_ea)
|
l.sw 0(r4),r3
|
l.sw 0(r4),r3
|
|
|
l.movhi r9,hi(end_except)
|
l.movhi r9,hi(end_except)
|
l.ori r9,r9,lo(end_except)
|
l.ori r9,r9,lo(end_except)
|
|
|
l.lwz r10,0(r10)
|
l.lwz r10,0(r10)
|
l.jr r10
|
l.jr r10
|
l.nop
|
l.nop
|
|
|
end_except:
|
end_except:
|
l.lwz r2,0x00(r1)
|
l.lwz r2,0x00(r1)
|
l.lwz r3,0x04(r1)
|
l.lwz r3,0x04(r1)
|
l.lwz r4,0x08(r1)
|
l.lwz r4,0x08(r1)
|
l.lwz r5,0x0c(r1)
|
l.lwz r5,0x0c(r1)
|
l.lwz r6,0x10(r1)
|
l.lwz r6,0x10(r1)
|
l.lwz r7,0x14(r1)
|
l.lwz r7,0x14(r1)
|
l.lwz r8,0x18(r1)
|
l.lwz r8,0x18(r1)
|
l.lwz r9,0x1c(r1)
|
l.lwz r9,0x1c(r1)
|
l.lwz r10,0x20(r1)
|
l.lwz r10,0x20(r1)
|
l.lwz r11,0x24(r1)
|
l.lwz r11,0x24(r1)
|
l.lwz r12,0x28(r1)
|
l.lwz r12,0x28(r1)
|
l.lwz r13,0x2c(r1)
|
l.lwz r13,0x2c(r1)
|
l.lwz r14,0x30(r1)
|
l.lwz r14,0x30(r1)
|
l.lwz r15,0x34(r1)
|
l.lwz r15,0x34(r1)
|
l.lwz r16,0x38(r1)
|
l.lwz r16,0x38(r1)
|
l.lwz r17,0x3c(r1)
|
l.lwz r17,0x3c(r1)
|
l.lwz r18,0x40(r1)
|
l.lwz r18,0x40(r1)
|
l.lwz r19,0x44(r1)
|
l.lwz r19,0x44(r1)
|
l.lwz r20,0x48(r1)
|
l.lwz r20,0x48(r1)
|
l.lwz r21,0x4c(r1)
|
l.lwz r21,0x4c(r1)
|
l.lwz r22,0x50(r1)
|
l.lwz r22,0x50(r1)
|
l.lwz r23,0x54(r1)
|
l.lwz r23,0x54(r1)
|
l.lwz r24,0x58(r1)
|
l.lwz r24,0x58(r1)
|
l.lwz r25,0x5c(r1)
|
l.lwz r25,0x5c(r1)
|
l.lwz r26,0x60(r1)
|
l.lwz r26,0x60(r1)
|
l.lwz r27,0x64(r1)
|
l.lwz r27,0x64(r1)
|
l.lwz r28,0x68(r1)
|
l.lwz r28,0x68(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r31,0x74(r1)
|
l.lwz r31,0x74(r1)
|
l.addi r1,r1,120
|
l.addi r1,r1,120
|
l.mtspr r0,r9,SPR_EPCR_BASE
|
l.mtspr r0,r9,SPR_EPCR_BASE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
except_basic:
|
except_basic:
|
sys1:
|
sys1:
|
l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */
|
l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */
|
l.mfspr r4,r0,SPR_SR
|
l.mfspr r4,r0,SPR_SR
|
l.and r4,r4,r3
|
l.and r4,r4,r3
|
l.ori r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
|
l.ori r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
|
l.mtspr r0,r4,SPR_SR
|
l.mtspr r0,r4,SPR_SR
|
|
|
l.addi r3,r0,0
|
l.addi r3,r0,0
|
l.sys 1
|
l.sys 1
|
l.addi r3,r3,2
|
l.addi r3,r3,2
|
|
|
sys2:
|
sys2:
|
l.addi r11,r0,0
|
l.addi r11,r0,0
|
|
|
l.mfspr r4,r0,SPR_SR /* Check SR */
|
l.mfspr r4,r0,SPR_SR /* Check SR */
|
l.andi r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
|
l.andi r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
|
l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
|
l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
|
l.bf 1f
|
l.bf 1f
|
l.nop
|
l.nop
|
l.addi r11,r11,1
|
l.addi r11,r11,1
|
1:
|
1:
|
l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */
|
l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */
|
l.bf 1f
|
l.bf 1f
|
l.nop
|
l.nop
|
l.addi r11,r11,2
|
l.addi r11,r11,2
|
1:
|
1:
|
l.sfeqi r5,0x1c /* Check the EPCR */
|
l.sfeqi r5,0x1c /* Check the EPCR */
|
l.bf 1f
|
l.bf 1f
|
l.nop
|
l.nop
|
l.addi r11,r11,4
|
l.addi r11,r11,4
|
1:
|
1:
|
l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */
|
l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */
|
l.bf 1f
|
l.bf 1f
|
l.nop
|
l.nop
|
l.addi r11,r11,8
|
l.addi r11,r11,8
|
1:
|
1:
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
lo_dmmu_en:
|
lo_dmmu_en:
|
l.mfspr r3,r0,SPR_SR
|
l.mfspr r3,r0,SPR_SR
|
l.ori r3,r3,SPR_SR_DME
|
l.ori r3,r3,SPR_SR_DME
|
l.mtspr r0,r3,SPR_ESR_BASE
|
l.mtspr r0,r3,SPR_ESR_BASE
|
l.mtspr r0,r9,SPR_EPCR_BASE
|
l.mtspr r0,r9,SPR_EPCR_BASE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
lo_immu_en:
|
lo_immu_en:
|
l.mfspr r3,r0,SPR_SR
|
l.mfspr r3,r0,SPR_SR
|
l.ori r3,r3,SPR_SR_IME
|
l.ori r3,r3,SPR_SR_IME
|
l.mtspr r0,r3,SPR_ESR_BASE
|
l.mtspr r0,r3,SPR_ESR_BASE
|
l.mtspr r0,r9,SPR_EPCR_BASE
|
l.mtspr r0,r9,SPR_EPCR_BASE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
call:
|
call:
|
l.addi r11,r0,0
|
l.addi r11,r0,0
|
l.jr r3
|
l.jr r3
|
l.nop
|
l.nop
|
|
|
call_with_int:
|
call_with_int:
|
l.mfspr r8,r0,SPR_SR
|
l.mfspr r8,r0,SPR_SR
|
l.ori r8,r8,SPR_SR_TEE
|
l.ori r8,r8,SPR_SR_TEE
|
l.mtspr r0,r8,SPR_ESR_BASE
|
l.mtspr r0,r8,SPR_ESR_BASE
|
l.mtspr r0,r3,SPR_EPCR_BASE
|
l.mtspr r0,r3,SPR_EPCR_BASE
|
l.rfe
|
l.rfe
|
|
|
load_acc_32:
|
load_acc_32:
|
l.movhi r11,hi(0x12345678)
|
l.movhi r11,hi(0x12345678)
|
l.ori r11,r11,lo(0x12345678)
|
l.ori r11,r11,lo(0x12345678)
|
l.lwz r11,0(r4)
|
l.lwz r11,0(r4)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
load_acc_16:
|
load_acc_16:
|
l.movhi r11,hi(0x12345678)
|
l.movhi r11,hi(0x12345678)
|
l.ori r11,r11,lo(0x12345678)
|
l.ori r11,r11,lo(0x12345678)
|
l.lhz r11,0(r4)
|
l.lhz r11,0(r4)
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
store_acc_32:
|
store_acc_32:
|
l.movhi r3,hi(0x12345678)
|
l.movhi r3,hi(0x12345678)
|
l.ori r3,r3,lo(0x12345678)
|
l.ori r3,r3,lo(0x12345678)
|
l.sw 0(r4),r3
|
l.sw 0(r4),r3
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
store_acc_16:
|
store_acc_16:
|
l.movhi r3,hi(0x12345678)
|
l.movhi r3,hi(0x12345678)
|
l.ori r3,r3,lo(0x12345678)
|
l.ori r3,r3,lo(0x12345678)
|
l.sh 0(r4),r3
|
l.sh 0(r4),r3
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
load_b_acc_32:
|
load_b_acc_32:
|
l.movhi r11,hi(0x12345678)
|
l.movhi r11,hi(0x12345678)
|
l.ori r11,r11,lo(0x12345678)
|
l.ori r11,r11,lo(0x12345678)
|
l.jr r9
|
l.jr r9
|
l.lwz r11,0(r4)
|
l.lwz r11,0(r4)
|
|
|
b_trap:
|
b_trap:
|
l.jr r9
|
l.jr r9
|
trap:
|
trap:
|
l.trap 15
|
l.trap 15
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
b_range:
|
b_range:
|
l.jr r9
|
l.jr r9
|
range:
|
range:
|
l.addi r3,r0,-1
|
l.addi r3,r0,-1
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
int_trigger:
|
int_trigger:
|
l.addi r11,r0,0
|
l.addi r11,r0,0
|
l.mfspr r3,r0,SPR_SR
|
l.mfspr r3,r0,SPR_SR
|
l.ori r3,r3,SPR_SR_TEE
|
l.ori r3,r3,SPR_SR_TEE
|
l.mtspr r0,r3,SPR_SR
|
l.mtspr r0,r3,SPR_SR
|
l.addi r11,r11,1
|
l.addi r11,r11,1
|
|
|
int_loop:
|
int_loop:
|
l.j int_loop
|
l.j int_loop
|
l.lwz r5,0(r4);
|
l.lwz r5,0(r4);
|
|
|
jump_back:
|
jump_back:
|
l.addi r11,r0,0
|
l.addi r11,r0,0
|
l.jr r9
|
l.jr r9
|
l.addi r11,r11,1
|
l.addi r11,r11,1
|
|
|