/* except-test.c. Test of Or1ksim exception handling
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/* except-test.c. Test of Or1ksim exception handling
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "support.h"
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#include "support.h"
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#include "int.h"
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#include "int.h"
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/* Define RAM physical location and size
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/* Define RAM physical location and size
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Bottom half will be used for this program, the rest
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Bottom half will be used for this program, the rest
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will be used for testing */
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will be used for testing */
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#define RAM_START 0x00000000
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#define RAM_START 0x00000000
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#define RAM_SIZE 0x00200000
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#define RAM_SIZE 0x00200000
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/* MMU page size */
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/* MMU page size */
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#define PAGE_SIZE 8192
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#define PAGE_SIZE 8192
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/* Number of DTLB sets used (power of 2, max is 256) */
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/* Number of DTLB sets used (power of 2, max is 256) */
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#define DTLB_SETS 32
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#define DTLB_SETS 32
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/* Number of DTLB ways (2, 2, 3 etc., max is 4). */
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/* Number of DTLB ways (2, 2, 3 etc., max is 4). */
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#define DTLB_WAYS 1
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#define DTLB_WAYS 1
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/* Number of ITLB sets used (power of 2, max is 256) */
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/* Number of ITLB sets used (power of 2, max is 256) */
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#define ITLB_SETS 32
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#define ITLB_SETS 32
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/* Number of ITLB ways (1, 2, 3 etc., max is 4). */
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/* Number of ITLB ways (1, 2, 3 etc., max is 4). */
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#define ITLB_WAYS 1
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#define ITLB_WAYS 1
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/* TLB mode codes */
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/* TLB mode codes */
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#define TLB_CODE_ONE_TO_ONE 0x00000000
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#define TLB_CODE_ONE_TO_ONE 0x00000000
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#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
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#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
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#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
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#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
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#define TLB_TEXT_SET_NB 8
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#define TLB_TEXT_SET_NB 8
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#define TLB_DATA_SET_NB 8
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#define TLB_DATA_SET_NB 8
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#define TLB_CODE_MASK 0xfffff000
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#define TLB_CODE_MASK 0xfffff000
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#define TLB_PR_MASK 0x00000fff
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#define TLB_PR_MASK 0x00000fff
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \
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#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_CI | \
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SPR_DTLBTR_URE | \
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SPR_DTLBTR_URE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SWE )
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SPR_DTLBTR_SWE )
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#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_CI | \
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#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_CI | \
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SPR_ITLBTR_SXE | \
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SPR_ITLBTR_SXE | \
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SPR_ITLBTR_UXE )
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SPR_ITLBTR_UXE )
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/* fails if x is false */
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/* fails if x is false */
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
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/* Exception vectors */
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/* Exception vectors */
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#define V_RESET 1
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#define V_RESET 1
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#define V_BERR 2
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#define V_BERR 2
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#define V_DPF 3
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#define V_DPF 3
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#define V_IPF 4
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#define V_IPF 4
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#define V_TICK 5
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#define V_TICK 5
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#define V_ALIGN 6
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#define V_ALIGN 6
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#define V_ILLINSN 7
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#define V_ILLINSN 7
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#define V_INT 8
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#define V_INT 8
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#define V_DTLB_MISS 9
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#define V_DTLB_MISS 9
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#define V_ITLB_MISS 10
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#define V_ITLB_MISS 10
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#define V_RANGE 11
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#define V_RANGE 11
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#define V_SYS 12
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#define V_SYS 12
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#define V_TRAP 14
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#define V_TRAP 14
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#define debug printf
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#define debug printf
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/* Extern functions */
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/* Extern functions */
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extern void lo_dmmu_en (void);
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extern void lo_dmmu_en (void);
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extern void lo_immu_en (void);
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extern void lo_immu_en (void);
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extern unsigned long call (unsigned long add, unsigned long val);
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extern unsigned long call (unsigned long add, unsigned long val);
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extern unsigned long call_with_int (unsigned long add, unsigned long val);
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extern unsigned long call_with_int (unsigned long add, unsigned long val);
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extern void trap (void);
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extern void trap (void);
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extern void b_trap (void);
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extern void b_trap (void);
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extern void range (void);
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extern void range (void);
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extern void b_range (void);
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extern void b_range (void);
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extern int except_basic (void);
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extern int except_basic (void);
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extern void (*test)(void);
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extern void (*test)(void);
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extern int load_acc_32 (unsigned long add);
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extern int load_acc_32 (unsigned long add);
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extern int load_acc_16 (unsigned long add);
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extern int load_acc_16 (unsigned long add);
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extern int store_acc_32 (unsigned long add);
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extern int store_acc_32 (unsigned long add);
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extern int store_acc_16 (unsigned long add);
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extern int store_acc_16 (unsigned long add);
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extern int load_b_acc_32 (unsigned long add);
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extern int load_b_acc_32 (unsigned long add);
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extern int int_trigger (void);
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extern int int_trigger (void);
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extern int int_loop (void);
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extern int int_loop (void);
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extern int jump_back (void);
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extern int jump_back (void);
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/* Local functions prototypes */
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/* Local functions prototypes */
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void dmmu_disable (void);
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void dmmu_disable (void);
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void immu_disable (void);
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void immu_disable (void);
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/* DTLB mode status */
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/* DTLB mode status */
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volatile unsigned long dtlb_val;
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volatile unsigned long dtlb_val;
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/* ITLB mode status */
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/* ITLB mode status */
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volatile unsigned long itlb_val;
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volatile unsigned long itlb_val;
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/* Exception counter */
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/* Exception counter */
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volatile int except_count;
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volatile int except_count;
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/* Exception mask */
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/* Exception mask */
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volatile unsigned long except_mask;
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volatile unsigned long except_mask;
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/* Exception efective address */
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/* Exception efective address */
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volatile unsigned long except_ea;
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volatile unsigned long except_ea;
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/* Eception PC */
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/* Eception PC */
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volatile unsigned long except_pc;
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volatile unsigned long except_pc;
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unsigned long excpt_buserr;
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unsigned long excpt_buserr;
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unsigned long excpt_dpfault;
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unsigned long excpt_dpfault;
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unsigned long excpt_ipfault;
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unsigned long excpt_ipfault;
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unsigned long excpt_tick;
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unsigned long excpt_tick;
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unsigned long excpt_align;
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unsigned long excpt_align;
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unsigned long excpt_illinsn;
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unsigned long excpt_illinsn;
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unsigned long excpt_int;
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unsigned long excpt_int;
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unsigned long excpt_dtlbmiss;
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unsigned long excpt_dtlbmiss;
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unsigned long excpt_itlbmiss;
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unsigned long excpt_itlbmiss;
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unsigned long excpt_range;
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unsigned long excpt_range;
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unsigned long excpt_syscall;
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unsigned long excpt_syscall;
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unsigned long excpt_break;
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unsigned long excpt_break;
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unsigned long excpt_trap;
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unsigned long excpt_trap;
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void fail (char *func, int line)
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void fail (char *func, int line)
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{
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{
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#ifndef __FUNCTION__
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#ifndef __FUNCTION__
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#define __FUNCTION__ "?"
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#define __FUNCTION__ "?"
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#endif
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#endif
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immu_disable ();
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immu_disable ();
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dmmu_disable ();
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dmmu_disable ();
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debug("Test failed in %s:%i\n", func, line);
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debug("Test failed in %s:%i\n", func, line);
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report (0xeeeeeeee);
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report (0xeeeeeeee);
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exit (1);
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exit (1);
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}
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}
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void test_dummy (void)
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void test_dummy (void)
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{
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{
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asm("test:");
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asm("test:");
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asm("l.addi\t\tr3,r3,1") ;
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asm("l.addi\t\tr3,r3,1") ;
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asm("l.nop" : :);
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asm("l.nop" : :);
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}
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}
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void copy_test (unsigned long phy_add)
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void copy_test (unsigned long phy_add)
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{
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{
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memcpy((void *)phy_add, (void *)&test, 8);
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memcpy((void *)phy_add, (void *)&test, 8);
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}
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}
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/* Bus error handler */
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/* Bus error handler */
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void bus_err_handler (void)
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void bus_err_handler (void)
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{
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{
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except_mask |= 1 << V_BERR;
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except_mask |= 1 << V_BERR;
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except_count++;
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except_count++;
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}
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}
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/* Illegal insn handler */
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/* Illegal insn handler */
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void ill_insn_handler (void)
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void ill_insn_handler (void)
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{
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{
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except_mask |= 1 << V_ILLINSN;
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except_mask |= 1 << V_ILLINSN;
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except_count++;
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except_count++;
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}
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}
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/* Low priority interrupt handler */
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/* Low priority interrupt handler */
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void tick_handler (void)
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void tick_handler (void)
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{
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{
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/* Disable interrupt recognition */
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/* Disable interrupt recognition */
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_TEE);
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_TEE);
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except_mask |= 1 << V_TICK;
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except_mask |= 1 << V_TICK;
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except_count++;
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except_count++;
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}
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}
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/* High priority interrupt handler */
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/* High priority interrupt handler */
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void int_handler (void)
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void int_handler (void)
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{
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{
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/* Disable interrupt recognition */
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/* Disable interrupt recognition */
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_IEE);
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mtspr(SPR_ESR_BASE, mfspr(SPR_ESR_BASE) & ~SPR_SR_IEE);
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except_mask |= 1 << V_INT;
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except_mask |= 1 << V_INT;
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except_count++;
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except_count++;
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}
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}
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/* Trap handler */
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/* Trap handler */
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void trap_handler (void)
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void trap_handler (void)
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{
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{
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except_mask |= 1 << V_TRAP;
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except_mask |= 1 << V_TRAP;
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except_count++;
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except_count++;
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}
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}
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/* Align handler */
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/* Align handler */
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void align_handler (void)
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void align_handler (void)
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{
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{
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except_mask |= 1 << V_ALIGN;
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except_mask |= 1 << V_ALIGN;
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except_count++;
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except_count++;
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}
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}
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/* Range handler */
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/* Range handler */
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void range_handler (void)
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void range_handler (void)
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{
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{
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/* Disable range exception */
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/* Disable range exception */
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mtspr (SPR_ESR_BASE, mfspr (SPR_ESR_BASE) & ~SPR_SR_OVE);
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mtspr (SPR_ESR_BASE, mfspr (SPR_ESR_BASE) & ~SPR_SR_OVE);
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except_mask |= 1 << V_RANGE;
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except_mask |= 1 << V_RANGE;
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except_count++;
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except_count++;
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}
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}
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/* DTLB miss exception handler */
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/* DTLB miss exception handler */
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void dtlb_miss_handler (void)
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void dtlb_miss_handler (void)
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{
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{
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unsigned long ea;
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unsigned long ea;
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int set, way = 0;
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int set, way = 0;
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int i;
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int i;
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/* Get EA that cause the exception */
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/* Get EA that cause the exception */
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ea = mfspr (SPR_EEAR_BASE);
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ea = mfspr (SPR_EEAR_BASE);
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/* Find TLB set and LRU way */
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/* Find TLB set and LRU way */
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set = (ea / PAGE_SIZE) % DTLB_SETS;
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set = (ea / PAGE_SIZE) % DTLB_SETS;
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for (i = 0; i < DTLB_WAYS; i++) {
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for (i = 0; i < DTLB_WAYS; i++) {
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if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {
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if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {
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way = i;
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way = i;
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break;
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break;
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}
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}
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}
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}
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
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mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | dtlb_val);
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mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | dtlb_val);
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except_mask |= 1 << V_DTLB_MISS;
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except_mask |= 1 << V_DTLB_MISS;
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except_count++;
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except_count++;
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}
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}
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/* ITLB miss exception handler */
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/* ITLB miss exception handler */
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void itlb_miss_handler (void)
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void itlb_miss_handler (void)
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{
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{
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unsigned long ea;
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unsigned long ea;
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int set, way = 0;
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int set, way = 0;
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int i;
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int i;
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/* Get EA that cause the exception */
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/* Get EA that cause the exception */
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ea = mfspr (SPR_EEAR_BASE);
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ea = mfspr (SPR_EEAR_BASE);
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/* Find TLB set and LRU way */
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/* Find TLB set and LRU way */
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set = (ea / PAGE_SIZE) % ITLB_SETS;
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set = (ea / PAGE_SIZE) % ITLB_SETS;
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for (i = 0; i < ITLB_WAYS; i++) {
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for (i = 0; i < ITLB_WAYS; i++) {
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if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {
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if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {
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way = i;
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way = i;
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break;
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break;
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}
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}
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}
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}
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mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
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mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | itlb_val);
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mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | itlb_val);
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except_mask |= 1 << V_ITLB_MISS;
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except_mask |= 1 << V_ITLB_MISS;
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except_count++;
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except_count++;
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}
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}
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|
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/* Data page fault exception handler */
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/* Data page fault exception handler */
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void dpage_fault_handler (void)
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void dpage_fault_handler (void)
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{
|
{
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unsigned long ea;
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unsigned long ea;
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int set, way = 0;
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int set, way = 0;
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int i;
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int i;
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|
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/* Get EA that cause the exception */
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/* Get EA that cause the exception */
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ea = mfspr (SPR_EEAR_BASE);
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ea = mfspr (SPR_EEAR_BASE);
|
|
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/* Find TLB set and way */
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/* Find TLB set and way */
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set = (ea / PAGE_SIZE) % DTLB_SETS;
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set = (ea / PAGE_SIZE) % DTLB_SETS;
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for (i = 0; i < DTLB_WAYS; i++) {
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for (i = 0; i < DTLB_WAYS; i++) {
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if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_VPN) == (ea & SPR_DTLBMR_VPN)) {
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if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_VPN) == (ea & SPR_DTLBMR_VPN)) {
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way = i;
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way = i;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
/* Give permission */
|
/* Give permission */
|
mtspr (SPR_DTLBTR_BASE(way) + set, (mfspr (SPR_DTLBTR_BASE(way) + set) & ~DTLB_PR_NOLIMIT) | dtlb_val);
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mtspr (SPR_DTLBTR_BASE(way) + set, (mfspr (SPR_DTLBTR_BASE(way) + set) & ~DTLB_PR_NOLIMIT) | dtlb_val);
|
|
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except_mask |= 1 << V_DPF;
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except_mask |= 1 << V_DPF;
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except_count++;
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except_count++;
|
}
|
}
|
|
|
/* Intstruction page fault exception handler */
|
/* Intstruction page fault exception handler */
|
void ipage_fault_handler (void)
|
void ipage_fault_handler (void)
|
{
|
{
|
unsigned long ea;
|
unsigned long ea;
|
int set, way = 0;
|
int set, way = 0;
|
int i;
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int i;
|
|
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/* Get EA that cause the exception */
|
/* Get EA that cause the exception */
|
ea = mfspr (SPR_EEAR_BASE);
|
ea = mfspr (SPR_EEAR_BASE);
|
|
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/* Find TLB set and way */
|
/* Find TLB set and way */
|
set = (ea / PAGE_SIZE) % ITLB_SETS;
|
set = (ea / PAGE_SIZE) % ITLB_SETS;
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_VPN) == (ea & SPR_ITLBMR_VPN)) {
|
if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_VPN) == (ea & SPR_ITLBMR_VPN)) {
|
way = i;
|
way = i;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
/* Give permission */
|
/* Give permission */
|
mtspr (SPR_ITLBTR_BASE(way) + set, (mfspr (SPR_ITLBTR_BASE(way) + set) & ~ITLB_PR_NOLIMIT) | itlb_val);
|
mtspr (SPR_ITLBTR_BASE(way) + set, (mfspr (SPR_ITLBTR_BASE(way) + set) & ~ITLB_PR_NOLIMIT) | itlb_val);
|
|
|
except_mask |= 1 << V_IPF;
|
except_mask |= 1 << V_IPF;
|
except_count++;
|
except_count++;
|
}
|
}
|
|
|
/*Enable DMMU */
|
/*Enable DMMU */
|
void dmmu_enable (void)
|
void dmmu_enable (void)
|
{
|
{
|
/* Enable DMMU */
|
/* Enable DMMU */
|
lo_dmmu_en ();
|
lo_dmmu_en ();
|
}
|
}
|
|
|
/* Disable DMMU */
|
/* Disable DMMU */
|
void dmmu_disable (void)
|
void dmmu_disable (void)
|
{
|
{
|
mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_DME);
|
mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_DME);
|
}
|
}
|
|
|
/* Enable IMMU */
|
/* Enable IMMU */
|
void immu_enable (void)
|
void immu_enable (void)
|
{
|
{
|
/* Enable IMMU */
|
/* Enable IMMU */
|
lo_immu_en ();
|
lo_immu_en ();
|
}
|
}
|
|
|
/* Disable IMMU */
|
/* Disable IMMU */
|
void immu_disable (void)
|
void immu_disable (void)
|
{
|
{
|
mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_IME);
|
mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_IME);
|
}
|
}
|
|
|
/* Tick timer init */
|
/* Tick timer init */
|
void tick_init (int period, int hp_int)
|
void tick_init (int period, int hp_int)
|
{
|
{
|
/* Disable tick timer exception recognition */
|
/* Disable tick timer exception recognition */
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
|
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
|
|
|
/* Set period of one cycle, restartable mode */
|
/* Set period of one cycle, restartable mode */
|
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD));
|
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_TP));
|
|
|
/* Reset counter */
|
/* Reset counter */
|
mtspr(SPR_TTCR, 0);
|
mtspr(SPR_TTCR, 0);
|
}
|
}
|
|
|
/* Interrupt test */
|
/* Interrupt test */
|
int interrupt_test (void)
|
int interrupt_test (void)
|
{
|
{
|
unsigned long ret;
|
unsigned long ret;
|
int i;
|
int i;
|
|
|
/* Init tick timer */
|
/* Init tick timer */
|
tick_init (1, 1);
|
tick_init (1, 1);
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Test normal high priority interrupt trigger */
|
/* Test normal high priority interrupt trigger */
|
ret = call ((unsigned long)&int_trigger, 0);
|
ret = call ((unsigned long)&int_trigger, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_TICK));
|
ASSERT(except_mask == (1 << V_TICK));
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
ASSERT(except_pc == (unsigned long)int_trigger + 16);
|
ASSERT(except_pc == (unsigned long)int_trigger + 16);
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Test inetrrupt in delay slot */
|
/* Test inetrrupt in delay slot */
|
tick_init (100, 1);
|
tick_init (100, 1);
|
|
|
/* Hopefully we will have interrupt recognition between branch insn and delay slot */
|
/* Hopefully we will have interrupt recognition between branch insn and delay slot */
|
except_pc = (unsigned long)&int_loop;
|
except_pc = (unsigned long)&int_loop;
|
for (i = 0; i < 10; i++) {
|
for (i = 0; i < 10; i++) {
|
call_with_int (except_pc, RAM_START);
|
call_with_int (except_pc, RAM_START);
|
ASSERT(except_pc == (unsigned long)&int_loop);
|
ASSERT(except_pc == (unsigned long)&int_loop);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* ITLB miss test */
|
/* ITLB miss test */
|
int itlb_test (void)
|
int itlb_test (void)
|
{
|
{
|
int i, j, ret;
|
int i, j, ret;
|
unsigned long ea, ta;
|
unsigned long ea, ta;
|
|
|
/* Invalidate all entries in ITLB */
|
/* Invalidate all entries in ITLB */
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (j = 0; j < ITLB_SETS; j++) {
|
for (j = 0; j < ITLB_SETS; j++) {
|
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
|
}
|
}
|
}
|
}
|
|
|
/* Set one to one translation for the use of this program */
|
/* Set one to one translation for the use of this program */
|
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
|
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
|
ea = RAM_START + (i*PAGE_SIZE);
|
ea = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI;
|
itlb_val = SPR_ITLBTR_CI;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Enable IMMU */
|
/* Enable IMMU */
|
immu_enable ();
|
immu_enable ();
|
|
|
/* Copy jump instruction to last location of a page */
|
/* Copy jump instruction to last location of a page */
|
ea = RAM_START + (RAM_SIZE/2) + ((TLB_TEXT_SET_NB + 1)*PAGE_SIZE) - 8;
|
ea = RAM_START + (RAM_SIZE/2) + ((TLB_TEXT_SET_NB + 1)*PAGE_SIZE) - 8;
|
memcpy((void *)ea, (void *)&jump_back, 12);
|
memcpy((void *)ea, (void *)&jump_back, 12);
|
|
|
/* Check if there was ITLB miss exception */
|
/* Check if there was ITLB miss exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ITLB_MISS));
|
ASSERT(except_mask == (1 << V_ITLB_MISS));
|
ASSERT(except_pc == ea);
|
ASSERT(except_pc == ea);
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was IPF miss exception */
|
/* Check if there was IPF miss exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_pc == ea);
|
ASSERT(except_pc == ea);
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI;
|
itlb_val = SPR_ITLBTR_CI;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was ITLB miss exception */
|
/* Check if there was ITLB miss exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ITLB_MISS));
|
ASSERT(except_mask == (1 << V_ITLB_MISS));
|
ASSERT(except_pc == ea + 4);
|
ASSERT(except_pc == ea + 4);
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was IPF exception */
|
/* Check if there was IPF exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_pc == ea + 4);
|
ASSERT(except_pc == ea + 4);
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 0);
|
ASSERT(except_count == 0);
|
ASSERT(ret == 1);
|
ASSERT(ret == 1);
|
|
|
/* Disable IMMU */
|
/* Disable IMMU */
|
immu_disable ();
|
immu_disable ();
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* DTLB miss test */
|
/* DTLB miss test */
|
int dtlb_test (void)
|
int dtlb_test (void)
|
{
|
{
|
int i, j, ret;
|
int i, j, ret;
|
unsigned long ea, ta;
|
unsigned long ea, ta;
|
|
|
/* Invalidate all entries in DTLB */
|
/* Invalidate all entries in DTLB */
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
|
}
|
}
|
}
|
}
|
|
|
/* Set one to one translation for the use of this program */
|
/* Set one to one translation for the use of this program */
|
for (i = 0; i < TLB_DATA_SET_NB; i++) {
|
for (i = 0; i < TLB_DATA_SET_NB; i++) {
|
ea = RAM_START + (i*PAGE_SIZE);
|
ea = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
|
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
dtlb_val = SPR_DTLBTR_CI;
|
dtlb_val = SPR_DTLBTR_CI;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Set pattern */
|
/* Set pattern */
|
ea = RAM_START + (RAM_SIZE/2) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
|
ea = RAM_START + (RAM_SIZE/2) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
|
REG32(ea) = 0x87654321;
|
REG32(ea) = 0x87654321;
|
|
|
/* Enable DMMU */
|
/* Enable DMMU */
|
dmmu_enable ();
|
dmmu_enable ();
|
|
|
/* Check if there was DTLB miss exception */
|
/* Check if there was DTLB miss exception */
|
ret = call ((unsigned long)&load_b_acc_32, ea);
|
ret = call ((unsigned long)&load_b_acc_32, ea);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_DTLB_MISS));
|
ASSERT(except_mask == (1 << V_DTLB_MISS));
|
ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
|
ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
|
ASSERT(except_ea == ea);
|
ASSERT(except_ea == ea);
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
|
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was DPF miss exception */
|
/* Check if there was DPF miss exception */
|
ret = call ((unsigned long)&load_b_acc_32, ea);
|
ret = call ((unsigned long)&load_b_acc_32, ea);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_DPF));
|
ASSERT(except_mask == (1 << V_DPF));
|
ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
|
ASSERT(except_pc == (unsigned long)load_b_acc_32 + 8);
|
ASSERT(except_ea == ea);
|
ASSERT(except_ea == ea);
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
ret = call ((unsigned long)&load_b_acc_32, ea);
|
ret = call ((unsigned long)&load_b_acc_32, ea);
|
ASSERT(except_count == 0);
|
ASSERT(except_count == 0);
|
ASSERT(ret == 0x87654321);
|
ASSERT(ret == 0x87654321);
|
|
|
/* Disable DMMU */
|
/* Disable DMMU */
|
dmmu_disable ();
|
dmmu_disable ();
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Bus error test */
|
/* Bus error test */
|
int buserr_test (void)
|
int buserr_test (void)
|
{
|
{
|
int i, j, ret;
|
int i, j, ret;
|
unsigned long ea, ta;
|
unsigned long ea, ta;
|
|
|
/* Invalidate all entries in ITLB */
|
/* Invalidate all entries in ITLB */
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (j = 0; j < ITLB_SETS; j++) {
|
for (j = 0; j < ITLB_SETS; j++) {
|
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
|
}
|
}
|
}
|
}
|
|
|
/* Set one to one translation for the use of this program */
|
/* Set one to one translation for the use of this program */
|
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
|
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
|
ea = RAM_START + (i*PAGE_SIZE);
|
ea = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Invalidate all entries in DTLB */
|
/* Invalidate all entries in DTLB */
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
|
}
|
}
|
}
|
}
|
|
|
/* Set one to one translation for the use of this program */
|
/* Set one to one translation for the use of this program */
|
for (i = 0; i < TLB_DATA_SET_NB; i++) {
|
for (i = 0; i < TLB_DATA_SET_NB; i++) {
|
ea = RAM_START + (i*PAGE_SIZE);
|
ea = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
|
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Set IMMU translation */
|
/* Set IMMU translation */
|
ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
|
ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
|
mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) |
|
mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) |
|
SPR_ITLBMR_V);
|
SPR_ITLBMR_V);
|
// Set translate to invalid address: 0xee000000
|
// Set translate to invalid address: 0xee000000
|
mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, (0xee000000 & SPR_ITLBTR_PPN) |
|
mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, (0xee000000 & SPR_ITLBTR_PPN) |
|
itlb_val);
|
itlb_val);
|
|
|
/* Enable IMMU */
|
/* Enable IMMU */
|
immu_enable ();
|
immu_enable ();
|
|
|
/* Check if there was bus error exception */
|
/* Check if there was bus error exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_pc == ea);
|
ASSERT(except_pc == ea);
|
ASSERT(except_ea == ea);
|
ASSERT(except_ea == ea);
|
|
|
/* Disable IMMU */
|
/* Disable IMMU */
|
immu_disable ();
|
immu_disable ();
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Set EA as an invalid memory location */
|
/* Set EA as an invalid memory location */
|
ea = 0xee000000;
|
ea = 0xee000000;
|
|
|
/* Check if there was bus error exception */
|
/* Check if there was bus error exception */
|
ret = call (ea, 0);
|
ret = call (ea, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_pc == ea);
|
ASSERT(except_pc == ea);
|
ASSERT(except_ea == ea);
|
ASSERT(except_ea == ea);
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Set DMMU translation */
|
/* Set DMMU translation */
|
ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
|
ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
|
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
|
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
|
mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) |
|
mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) |
|
SPR_DTLBMR_V);
|
SPR_DTLBMR_V);
|
// Set translate to invalid address: 0xee000000
|
// Set translate to invalid address: 0xee000000
|
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, (0xee000000 & SPR_DTLBTR_PPN) |
|
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, (0xee000000 & SPR_DTLBTR_PPN) |
|
dtlb_val);
|
dtlb_val);
|
|
|
/* Enable DMMU */
|
/* Enable DMMU */
|
dmmu_enable ();
|
dmmu_enable ();
|
|
|
/* Check if there was bus error exception */
|
/* Check if there was bus error exception */
|
ret = call ((unsigned long)&load_acc_32, ea );
|
ret = call ((unsigned long)&load_acc_32, ea );
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
|
ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
|
ASSERT(except_ea == ea);
|
ASSERT(except_ea == ea);
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
|
|
/* Disable DMMU */
|
/* Disable DMMU */
|
dmmu_disable ();
|
dmmu_disable ();
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
// Set ea to invalid address
|
// Set ea to invalid address
|
ea = 0xee000000;
|
ea = 0xee000000;
|
|
|
/* Check if there was bus error exception */
|
/* Check if there was bus error exception */
|
ret = call ((unsigned long)&load_acc_32, ea );
|
ret = call ((unsigned long)&load_acc_32, ea );
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_mask == (1 << V_BERR));
|
ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
|
ASSERT(except_pc == (unsigned long)load_acc_32 + 8);
|
ASSERT(except_ea == ea);
|
ASSERT(except_ea == ea);
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Illegal instruction test */
|
/* Illegal instruction test */
|
int illegal_insn_test (void)
|
int illegal_insn_test (void)
|
{
|
{
|
int ret;
|
int ret;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Set illegal insn code.
|
/* Set illegal insn code.
|
|
|
Original code had two bugs. First it jumped to the illegal instruction,
|
Original code had two bugs. First it jumped to the illegal instruction,
|
rather than the immediately preceding l.jr r9 (allowing us to
|
rather than the immediately preceding l.jr r9 (allowing us to
|
recover). Secondly it used 0xffffffff as an illegal instruction. Except
|
recover). Secondly it used 0xffffffff as an illegal instruction. Except
|
it isn't - it's l.cust8 0x3ffffff.
|
it isn't - it's l.cust8 0x3ffffff.
|
|
|
Fixed by a) jumping to the correct location and b) really using an
|
Fixed by a) jumping to the correct location and b) really using an
|
illegal instruction (opcode 0x3a. */
|
illegal instruction (opcode 0x3a. */
|
REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
|
REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
|
REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe8000000;
|
REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe8000000;
|
|
|
/* Check if there was illegal insn exception. Note that if an illegal
|
/* Check if there was illegal insn exception. Note that if an illegal
|
instruction occurs in a delay slot (like this one), then the exception
|
instruction occurs in a delay slot (like this one), then the exception
|
PC is the address of the jump instruction. */
|
PC is the address of the jump instruction. */
|
ret = call (RAM_START + (RAM_SIZE/2), 0 ); /* JPB */
|
ret = call (RAM_START + (RAM_SIZE/2), 0 ); /* JPB */
|
|
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE/2)));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE/2)));
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Align test */
|
/* Align test */
|
int align_test (void)
|
int align_test (void)
|
{
|
{
|
int ret;
|
int ret;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was alignment exception on read insn */
|
/* Check if there was alignment exception on read insn */
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
|
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 2);
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 2);
|
ASSERT(except_count == 2);
|
ASSERT(except_count == 2);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 2)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 2)));
|
|
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 3);
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 3);
|
ASSERT(except_count == 3);
|
ASSERT(except_count == 3);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 3)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 3)));
|
|
|
ret = call ((unsigned long)&load_acc_16, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ret = call ((unsigned long)&load_acc_16, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ASSERT(except_count == 4);
|
ASSERT(except_count == 4);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_16) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_16) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
|
|
/* Check alignment exception on write insn */
|
/* Check alignment exception on write insn */
|
call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ASSERT(except_count == 5);
|
ASSERT(except_count == 5);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
|
|
call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 2);
|
call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 2);
|
ASSERT(except_count == 6);
|
ASSERT(except_count == 6);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 2)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 2)));
|
|
|
call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 3);
|
call ((unsigned long)&store_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 3);
|
ASSERT(except_count == 7);
|
ASSERT(except_count == 7);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(store_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 3)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 3)));
|
|
|
call ((unsigned long)&store_acc_16, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
call ((unsigned long)&store_acc_16, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ASSERT(except_count == 8);
|
ASSERT(except_count == 8);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_pc == ((unsigned long)(store_acc_16) + 8));
|
ASSERT(except_pc == ((unsigned long)(store_acc_16) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
|
|
|
|
ret = call ((unsigned long)&load_b_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ret = call ((unsigned long)&load_b_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ASSERT(except_count == 9);
|
ASSERT(except_count == 9);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_b_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_b_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
|
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Trap test */
|
/* Trap test */
|
int trap_test (void)
|
int trap_test (void)
|
{
|
{
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was trap exception */
|
/* Check if there was trap exception */
|
call ((unsigned long)&trap, 0);
|
call ((unsigned long)&trap, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_TRAP));
|
ASSERT(except_mask == (1 << V_TRAP));
|
ASSERT(except_pc == (unsigned long)(trap));
|
ASSERT(except_pc == (unsigned long)(trap));
|
|
|
/* Check if there was trap exception */
|
/* Check if there was trap exception */
|
call ((unsigned long)&b_trap, 0);
|
call ((unsigned long)&b_trap, 0);
|
ASSERT(except_count == 2);
|
ASSERT(except_count == 2);
|
ASSERT(except_mask == (1 << V_TRAP));
|
ASSERT(except_mask == (1 << V_TRAP));
|
ASSERT(except_pc == (unsigned long)(b_trap));
|
ASSERT(except_pc == (unsigned long)(b_trap));
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Range test */
|
/* Range test */
|
int range_test (void)
|
int range_test (void)
|
{
|
{
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was range exception */
|
/* Check if there was range exception */
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
|
call ((unsigned long)&range, 0);
|
call ((unsigned long)&range, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_RANGE));
|
ASSERT(except_mask == (1 << V_RANGE));
|
ASSERT(except_pc == (unsigned long)(range));
|
ASSERT(except_pc == (unsigned long)(range));
|
ASSERT(except_ea == 0);
|
ASSERT(except_ea == 0);
|
|
|
/* Check if there was range exception */
|
/* Check if there was range exception */
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
|
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_OVE);
|
call ((unsigned long)&b_range, 0);
|
call ((unsigned long)&b_range, 0);
|
ASSERT(except_count == 2);
|
ASSERT(except_count == 2);
|
ASSERT(except_mask == (1 << V_RANGE));
|
ASSERT(except_mask == (1 << V_RANGE));
|
ASSERT(except_pc == (unsigned long)(b_range));
|
ASSERT(except_pc == (unsigned long)(b_range));
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Exception priority test */
|
/* Exception priority test */
|
void except_priority_test (void)
|
void except_priority_test (void)
|
{
|
{
|
int i, j;
|
int i, j;
|
unsigned long ea, ta, ret;
|
unsigned long ea, ta, ret;
|
|
|
/* Invalidate all entries in ITLB */
|
/* Invalidate all entries in ITLB */
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (i = 0; i < ITLB_WAYS; i++) {
|
for (j = 0; j < ITLB_SETS; j++) {
|
for (j = 0; j < ITLB_SETS; j++) {
|
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
|
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
|
}
|
}
|
}
|
}
|
|
|
/* Set one to one translation for the use of this program */
|
/* Set one to one translation for the use of this program */
|
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
|
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
|
ea = RAM_START + (i*PAGE_SIZE);
|
ea = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
itlb_val = SPR_ITLBTR_CI;
|
itlb_val = SPR_ITLBTR_CI;
|
|
|
/* Invalidate all entries in DTLB */
|
/* Invalidate all entries in DTLB */
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (i = 0; i < DTLB_WAYS; i++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
for (j = 0; j < DTLB_SETS; j++) {
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBMR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
|
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
|
}
|
}
|
}
|
}
|
|
|
/* Set one to one translation for the use of this program */
|
/* Set one to one translation for the use of this program */
|
for (i = 0; i < TLB_DATA_SET_NB; i++) {
|
for (i = 0; i < TLB_DATA_SET_NB; i++) {
|
ea = RAM_START + (i*PAGE_SIZE);
|
ea = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
ta = RAM_START + (i*PAGE_SIZE);
|
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
|
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
|
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
|
}
|
}
|
|
|
/* Init tick timer */
|
/* Init tick timer */
|
tick_init (1, 1);
|
tick_init (1, 1);
|
|
|
/* Set dtlb no permisions */
|
/* Set dtlb no permisions */
|
dtlb_val = SPR_DTLBTR_CI;
|
dtlb_val = SPR_DTLBTR_CI;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Enable IMMU */
|
/* Enable IMMU */
|
immu_enable ();
|
immu_enable ();
|
|
|
/* The following is currently disabled due to differing behavior between
|
/* The following is currently disabled due to differing behavior between
|
or1ksim and the OR1200 RTL. Or1ksim appears to receive only 1 exception
|
or1ksim and the OR1200 RTL. Or1ksim appears to receive only 1 exception
|
during the call_with_int() call. The OR1200 correctly, in my opionion,
|
during the call_with_int() call. The OR1200 correctly, in my opionion,
|
reports 2 exceptions - ITLB miss and tick timer. -- Julius
|
reports 2 exceptions - ITLB miss and tick timer. -- Julius
|
|
|
TODO: Investigate why or1ksim isn't reporting ITLB miss.
|
TODO: Investigate why or1ksim isn't reporting ITLB miss.
|
|
|
*/
|
*/
|
|
|
#if 0
|
#if 0
|
/* Check if there was INT exception */
|
/* Check if there was INT exception */
|
call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
|
call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
|
printf("ec:%d 0x%lx\n",except_count,except_mask); ASSERT(except_count == 2);
|
printf("ec:%d 0x%lx\n",except_count,except_mask); ASSERT(except_count == 2);
|
ASSERT(except_mask == ((1 << V_TICK) | (1 << V_ITLB_MISS)));
|
ASSERT(except_mask == ((1 << V_TICK) | (1 << V_ITLB_MISS)));
|
printf("epc %8lx\n",except_pc);
|
printf("epc %8lx\n",except_pc);
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
#endif
|
#endif
|
|
|
/* Check if there was ITLB exception */
|
/* Check if there was ITLB exception */
|
call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
|
call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ITLB_MISS));
|
ASSERT(except_mask == (1 << V_ITLB_MISS));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
|
|
/* Set dtlb permisions */
|
/* Set dtlb permisions */
|
itlb_val |= SPR_ITLBTR_SXE;
|
itlb_val |= SPR_ITLBTR_SXE;
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was IPF exception */
|
/* Check if there was IPF exception */
|
call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
|
call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_mask == (1 << V_IPF));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Disable MMU */
|
/* Disable MMU */
|
immu_disable ();
|
immu_disable ();
|
|
|
/* Set illegal instruction. JPB. Use a really illegal instruction, not
|
/* Set illegal instruction. JPB. Use a really illegal instruction, not
|
l.cust8 0x3ffffff. */
|
l.cust8 0x3ffffff. */
|
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 0) = 0x00000000;
|
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 0) = 0x00000000;
|
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xe8000000;
|
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xe8000000;
|
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 8) = 0x00000000;
|
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 8) = 0x00000000;
|
|
|
/* Check if there was illegal insn exception */
|
/* Check if there was illegal insn exception */
|
call (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4, 0);
|
call (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_mask == (1 << V_ILLINSN));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4));
|
ASSERT(except_pc == (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4 ));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4 ));
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Enable DMMU */
|
/* Enable DMMU */
|
dmmu_enable ();
|
dmmu_enable ();
|
|
|
/* Check if there was alignment exception on read insn */
|
/* Check if there was alignment exception on read insn */
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE) + 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(except_mask == (1 << V_ALIGN));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE + 1)));
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was DTLB exception */
|
/* Check if there was DTLB exception */
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_DTLB_MISS));
|
ASSERT(except_mask == (1 << V_DTLB_MISS));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Set dtlb permisions */
|
/* Set dtlb permisions */
|
dtlb_val |= SPR_DTLBTR_SRE;
|
dtlb_val |= SPR_DTLBTR_SRE;
|
|
|
/* Check if there was DPF exception */
|
/* Check if there was DPF exception */
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
|
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_DPF));
|
ASSERT(except_mask == (1 << V_DPF));
|
ASSERT(ret == 0x12345678);
|
ASSERT(ret == 0x12345678);
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
|
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
|
|
|
/* Reset except counter */
|
/* Reset except counter */
|
except_count = 0;
|
except_count = 0;
|
except_mask = 0;
|
except_mask = 0;
|
except_pc = 0;
|
except_pc = 0;
|
except_ea = 0;
|
except_ea = 0;
|
|
|
/* Check if there was trap exception */
|
/* Check if there was trap exception */
|
call ((unsigned long)&trap, 0);
|
call ((unsigned long)&trap, 0);
|
ASSERT(except_count == 1);
|
ASSERT(except_count == 1);
|
ASSERT(except_mask == (1 << V_TRAP));
|
ASSERT(except_mask == (1 << V_TRAP));
|
ASSERT(except_pc == (unsigned long)(trap));
|
ASSERT(except_pc == (unsigned long)(trap));
|
|
|
}
|
}
|
|
|
int main (void)
|
int main (void)
|
{
|
{
|
int ret;
|
int ret;
|
|
|
printf("except_test\n");
|
printf("except_test\n");
|
|
|
/* Register bus error handler */
|
/* Register bus error handler */
|
excpt_buserr = (unsigned long)bus_err_handler;
|
excpt_buserr = (unsigned long)bus_err_handler;
|
|
|
/* Register illegal insn handler */
|
/* Register illegal insn handler */
|
excpt_illinsn = (unsigned long)ill_insn_handler;
|
excpt_illinsn = (unsigned long)ill_insn_handler;
|
|
|
/* Register tick timer exception handler */
|
/* Register tick timer exception handler */
|
excpt_tick = (unsigned long)tick_handler;
|
excpt_tick = (unsigned long)tick_handler;
|
|
|
/* Register external interrupt handler */
|
/* Register external interrupt handler */
|
excpt_int = (unsigned long)int_handler;
|
excpt_int = (unsigned long)int_handler;
|
|
|
/* Register ITLB miss handler */
|
/* Register ITLB miss handler */
|
excpt_itlbmiss = (unsigned long)itlb_miss_handler;
|
excpt_itlbmiss = (unsigned long)itlb_miss_handler;
|
|
|
/* Register instruction page fault handler */
|
/* Register instruction page fault handler */
|
excpt_ipfault = (unsigned long)ipage_fault_handler;
|
excpt_ipfault = (unsigned long)ipage_fault_handler;
|
|
|
/* Register DTLB miss handler */
|
/* Register DTLB miss handler */
|
excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;
|
excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;
|
|
|
/* Register data page fault handler */
|
/* Register data page fault handler */
|
excpt_dpfault = (unsigned long)dpage_fault_handler;
|
excpt_dpfault = (unsigned long)dpage_fault_handler;
|
|
|
/* Register trap handler */
|
/* Register trap handler */
|
excpt_trap = (unsigned long)trap_handler;
|
excpt_trap = (unsigned long)trap_handler;
|
|
|
/* Register align handler */
|
/* Register align handler */
|
excpt_align = (unsigned long)align_handler;
|
excpt_align = (unsigned long)align_handler;
|
|
|
/* Register range handler */
|
/* Register range handler */
|
excpt_range = (unsigned long)range_handler;
|
excpt_range = (unsigned long)range_handler;
|
|
|
/* Exception basic test */
|
/* Exception basic test */
|
ret = except_basic ();
|
ret = except_basic ();
|
ASSERT(ret == 0);
|
ASSERT(ret == 0);
|
printf("interupt_test\n");
|
printf("interupt_test\n");
|
/* Interrupt exception test */
|
/* Interrupt exception test */
|
interrupt_test ();
|
interrupt_test ();
|
|
|
printf("itlb_test\n");
|
printf("itlb_test\n");
|
/* ITLB exception test */
|
/* ITLB exception test */
|
itlb_test ();
|
itlb_test ();
|
|
|
printf("dtlb_test\n");
|
printf("dtlb_test\n");
|
/* DTLB exception test */
|
/* DTLB exception test */
|
dtlb_test ();
|
dtlb_test ();
|
|
|
printf("buserr_test\n");
|
printf("buserr_test\n");
|
/* Bus error exception test */
|
/* Bus error exception test */
|
buserr_test ();
|
buserr_test ();
|
|
|
printf("illegal_insn_test\n");
|
printf("illegal_insn_test\n");
|
/* Bus error exception test */
|
/* Bus error exception test */
|
/* Illegal insn test */
|
/* Illegal insn test */
|
illegal_insn_test ();
|
illegal_insn_test ();
|
|
|
printf("align_test\n");
|
printf("align_test\n");
|
/* Alignment test */
|
/* Alignment test */
|
align_test ();
|
align_test ();
|
|
|
printf("trap_test\n");
|
printf("trap_test\n");
|
/* Trap test */
|
/* Trap test */
|
trap_test ();
|
trap_test ();
|
|
|
printf("except_priority_test\n");
|
printf("except_priority_test\n");
|
/* Range test */
|
/* Range test */
|
// range_test ();
|
// range_test ();
|
|
|
/* Exception priority test */
|
/* Exception priority test */
|
except_priority_test ();
|
except_priority_test ();
|
|
|
report (0xdeaddead);
|
report (0xdeaddead);
|
exit (0);
|
exit (0);
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
