/* int-test.S. Test of Or1ksim interrupt handling
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/* int-test.S. Test of Or1ksim interrupt handling
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 1999-2006 OpenCores
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributors various OpenCores participants
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Contributors various OpenCores participants
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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/* NOTE. This is not a test of the Programmable Interrupt Controller.
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/* NOTE. This is not a test of the Programmable Interrupt Controller.
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Within the test we'll use following global variables:
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Within the test we'll use following global variables:
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r16 interrupt counter
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r16 interrupt counter
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r17 current tick timer comparison counter
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r17 current tick timer comparison counter
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r18 sanity counter
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r18 sanity counter
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r19 loop counter
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r19 loop counter
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r20 temp value of SR reg
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r20 temp value of SR reg
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r21 temp value of TTMR reg.
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r21 temp value of TTMR reg.
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r23 RAM_START
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r23 RAM_START
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r25-r31 used by int handler
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r25-r31 used by int handler
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The test do the following:
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The test do the following:
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We set up the tick timer to trigger once and then we trigger interrupts
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We set up the tick timer to trigger once and then we trigger interrupts
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incrementally on every cycle in the specified test program; on interrupt
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incrementally on every cycle in the specified test program; on interrupt
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handler we check if data computed so far exactly matches precalculated
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handler we check if data computed so far exactly matches precalculated
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values. If interrupt has returned incorreclty, we can detect this using
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values. If interrupt has returned incorreclty, we can detect this using
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assertion routine at the end.
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assertion routine at the end.
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*/
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*/
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#define RAM_START 0x00000000
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#define RAM_START 0x00000000
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.section .except,"ax"
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.section .except,"ax"
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.org 0x100
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.org 0x100
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_reset_vector:
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_reset_vector:
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// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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// and indeed it is not when simulating the or1200 Verilog core.
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l.andi r0,r0,0x0
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l.addi r2,r0,0x0
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l.addi r2,r0,0x0
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l.addi r3,r0,0x0
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l.addi r3,r0,0x0
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l.addi r4,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r6,r0,0x0
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l.addi r7,r0,0x0
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l.addi r7,r0,0x0
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l.addi r8,r0,0x0
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l.addi r8,r0,0x0
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l.addi r9,r0,0x0
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l.addi r9,r0,0x0
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l.addi r10,r0,0x0
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l.addi r10,r0,0x0
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l.addi r11,r0,0x0
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l.addi r11,r0,0x0
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l.addi r12,r0,0x0
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l.addi r12,r0,0x0
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l.addi r13,r0,0x0
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l.addi r13,r0,0x0
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l.addi r14,r0,0x0
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l.addi r14,r0,0x0
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l.addi r15,r0,0x0
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l.addi r15,r0,0x0
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l.addi r16,r0,0x0
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l.addi r16,r0,0x0
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l.addi r17,r0,0x0
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l.addi r17,r0,0x0
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l.addi r18,r0,0x0
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l.addi r18,r0,0x0
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l.addi r19,r0,0x0
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l.addi r19,r0,0x0
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l.addi r20,r0,0x0
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l.addi r20,r0,0x0
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l.addi r21,r0,0x0
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l.addi r21,r0,0x0
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l.addi r22,r0,0x0
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l.addi r22,r0,0x0
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l.addi r23,r0,0x0
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l.addi r23,r0,0x0
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l.addi r24,r0,0x0
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l.addi r24,r0,0x0
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l.addi r25,r0,0x0
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l.addi r25,r0,0x0
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l.addi r26,r0,0x0
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l.addi r26,r0,0x0
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l.addi r27,r0,0x0
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l.addi r27,r0,0x0
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l.addi r28,r0,0x0
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l.addi r28,r0,0x0
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l.addi r29,r0,0x0
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l.addi r29,r0,0x0
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l.addi r30,r0,0x0
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l.addi r30,r0,0x0
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l.addi r31,r0,0x0
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l.addi r31,r0,0x0
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l.movhi r3,hi(_start)
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l.movhi r3,hi(_start)
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l.ori r3,r3,lo(_start)
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l.ori r3,r3,lo(_start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.org 0x500
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.org 0x500
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_tick_handler:
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_tick_handler:
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#
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#
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# Tick timer exception handler
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# Tick timer exception handler
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#
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#
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l.addi r31,r3,0
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l.addi r31,r3,0
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# get interrupted program pc
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# get interrupted program pc
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l.mfspr r25,r0,SPR_EPCR_BASE
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l.mfspr r25,r0,SPR_EPCR_BASE
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# calculate instruction address
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# calculate instruction address
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l.movhi r26,hi(_ie_start)
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l.movhi r26,hi(_ie_start)
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l.ori r26,r26,lo(_ie_start)
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l.ori r26,r26,lo(_ie_start)
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l.addi r3,r25,0 #print insn index
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l.addi r3,r25,0 #print insn index
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l.nop 2
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l.nop 2
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l.sub r25,r25,r26
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l.sub r25,r25,r26
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l.addi r3,r25,0 #print insn index
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l.addi r3,r25,0 #print insn index
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l.nop 2
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l.nop 2
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l.addi r3,r31,0 # restore r3
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l.addi r3,r31,0 # restore r3
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l.sfeqi r25, 0x00
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l.sfeqi r25, 0x00
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l.bf _i00
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l.bf _i00
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l.sfeqi r25, 0x04
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l.sfeqi r25, 0x04
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l.bf _i04
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l.bf _i04
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l.sfeqi r25, 0x08
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l.sfeqi r25, 0x08
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l.bf _i08
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l.bf _i08
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l.sfeqi r25, 0x0c
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l.sfeqi r25, 0x0c
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l.bf _i0c
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l.bf _i0c
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l.sfeqi r25, 0x10
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l.sfeqi r25, 0x10
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l.bf _i10
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l.bf _i10
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l.sfeqi r25, 0x14
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l.sfeqi r25, 0x14
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l.bf _i14
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l.bf _i14
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l.sfeqi r25, 0x18
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l.sfeqi r25, 0x18
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l.bf _i18
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l.bf _i18
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l.sfeqi r25, 0x1c
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l.sfeqi r25, 0x1c
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l.bf _i1c
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l.bf _i1c
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l.sfeqi r25, 0x20
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l.sfeqi r25, 0x20
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l.bf _i20
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l.bf _i20
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l.sfeqi r25, 0x24
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l.sfeqi r25, 0x24
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l.bf _i24
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l.bf _i24
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l.sfeqi r25, 0x28
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l.sfeqi r25, 0x28
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l.bf _i28
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l.bf _i28
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l.sfeqi r25, 0x2c
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l.sfeqi r25, 0x2c
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l.bf _i2c
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l.bf _i2c
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l.sfeqi r25, 0x30
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l.sfeqi r25, 0x30
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l.bf _i30
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l.bf _i30
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l.sfeqi r25, 0x34
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l.sfeqi r25, 0x34
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l.bf _i34
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l.bf _i34
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l.sfeqi r25, 0x38
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l.sfeqi r25, 0x38
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l.bf _i38
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l.bf _i38
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l.nop
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l.nop
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# value not defined
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# value not defined
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_die:
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_die:
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l.nop 2 #print r3
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l.nop 2 #print r3
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l.addi r3,r0,0xeeee
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l.addi r3,r0,0xeeee
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l.nop 2
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l.nop 2
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l.addi r3,r0,1
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l.addi r3,r0,1
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l.nop 1
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l.nop 1
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1:
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1:
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l.j 1b
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l.j 1b
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l.nop
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l.nop
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.section .text
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.section .text
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_start:
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_start:
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l.movhi r3,hi(_main)
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l.movhi r3,hi(_main)
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l.ori r3,r3,lo(_main)
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l.ori r3,r3,lo(_main)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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_main:
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_main:
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l.nop
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l.nop
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l.addi r3,r0,SPR_SR_SM
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l.addi r3,r0,SPR_SR_SM
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l.mtspr r0,r3,SPR_SR
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l.mtspr r0,r3,SPR_SR
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l.nop
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l.nop
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#
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#
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# set tick counter to initial 3 cycles
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# set tick counter to initial 3 cycles
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#
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#
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l.addi r16,r0,0
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l.addi r16,r0,0
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l.addi r17,r0,1
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l.addi r17,r0,1
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l.addi r18,r0,0
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l.addi r18,r0,0
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l.addi r19,r0,0
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l.addi r19,r0,0
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l.addi r22,r0,0
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l.addi r22,r0,0
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l.movhi r23,hi(RAM_START)
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l.movhi r23,hi(RAM_START)
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l.ori r23,r23,lo(RAM_START)
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l.ori r23,r23,lo(RAM_START)
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# Set r20 to hold enable tick exception
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# Set r20 to hold enable tick exception
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l.mfspr r20,r0,SPR_SR
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l.mfspr r20,r0,SPR_SR
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l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
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l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
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# Set r21 to hold value of TTMR
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# Set r21 to hold value of TTMR
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l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
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l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
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l.add r21,r5,r17
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l.add r21,r5,r17
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#
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#
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# MAIN LOOP
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# MAIN LOOP
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#
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#
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_main_loop:
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_main_loop:
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# reinitialize memory and registers
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# reinitialize memory and registers
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l.addi r3,r0,0xaaaa
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l.addi r3,r0,0xaaaa
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l.addi r9,r0,0xbbbb
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l.addi r9,r0,0xbbbb
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l.sw 0(r23),r3
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l.sw 0(r23),r3
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l.sw 4(r23),r9
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l.sw 4(r23),r9
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l.sw 8(r23),r3
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l.sw 8(r23),r3
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# Reinitializes tick timer
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# Reinitializes tick timer
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l.addi r17,r17,1
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l.addi r17,r17,1
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l.mtspr r0,r0,SPR_TTCR # set TTCR
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l.mtspr r0,r0,SPR_TTCR # set TTCR
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l.mtspr r0,r21,SPR_TTMR # set TTMR
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l.mtspr r0,r21,SPR_TTMR # set TTMR
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l.mtspr r0,r0,SPR_TTCR # set TTCR
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l.mtspr r0,r0,SPR_TTCR # set TTCR
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l.addi r21,r21,1
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l.addi r21,r21,1
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|
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# Enable exceptions and interrupts
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# Enable exceptions and interrupts
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l.mtspr r0,r20,SPR_SR # set SR
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l.mtspr r0,r20,SPR_SR # set SR
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|
|
##### TEST CODE #####
|
##### TEST CODE #####
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_ie_start:
|
_ie_start:
|
l.movhi r3,0x1234 #00
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l.movhi r3,0x1234 #00
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l.sw 0(r23),r3 #04
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l.sw 0(r23),r3 #04
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l.movhi r3,hi(RAM_START) #08
|
l.movhi r3,hi(RAM_START) #08
|
l.lwz r3,0(r3) #0c
|
l.lwz r3,0(r3) #0c
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l.movhi r3,hi(RAM_START) #10
|
l.movhi r3,hi(RAM_START) #10
|
l.addi r3,r3,4 #14
|
l.addi r3,r3,4 #14
|
l.j 1f #18
|
l.j 1f #18
|
l.lwz r3,0(r3) #1c
|
l.lwz r3,0(r3) #1c
|
l.addi r3,r3,1 #20
|
l.addi r3,r3,1 #20
|
1:
|
1:
|
l.sfeqi r3,0xdead #24
|
l.sfeqi r3,0xdead #24
|
l.jal 2f #28
|
l.jal 2f #28
|
l.addi r3,r0,0x5678 #2c
|
l.addi r3,r0,0x5678 #2c
|
|
|
_return_addr:
|
_return_addr:
|
2:
|
2:
|
l.bf _die #30
|
l.bf _die #30
|
l.sw 8(r23),r3 #34
|
l.sw 8(r23),r3 #34
|
_ie_end:
|
_ie_end:
|
l.nop #38
|
l.nop #38
|
##### END OF TEST CODE #####
|
##### END OF TEST CODE #####
|
|
|
# do some testing
|
# do some testing
|
|
|
l.j _main_loop
|
l.j _main_loop
|
l.nop
|
l.nop
|
|
|
_i00:
|
_i00:
|
l.sfeqi r3,0xaaaa
|
l.sfeqi r3,0xaaaa
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i04:
|
_i04:
|
l.movhi r26,0x1234
|
l.movhi r26,0x1234
|
l.sfeq r3,r26
|
l.sfeq r3,r26
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.lwz r26,0(r23)
|
l.lwz r26,0(r23)
|
l.sfeqi r26,0xaaaa
|
l.sfeqi r26,0xaaaa
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i08:
|
_i08:
|
l.movhi r26,0x1234
|
l.movhi r26,0x1234
|
l.sfeq r3,r26
|
l.sfeq r3,r26
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.lwz r27,0(r23)
|
l.lwz r27,0(r23)
|
l.sfeq r27,r26
|
l.sfeq r27,r26
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i0c:
|
_i0c:
|
l.sfeq r3,r23
|
l.sfeq r3,r23
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i10:
|
_i10:
|
l.movhi r26,0x1234
|
l.movhi r26,0x1234
|
l.sfeq r26,r3
|
l.sfeq r26,r3
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i14:
|
_i14:
|
l.sfeq r3,r23
|
l.sfeq r3,r23
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i18:
|
_i18:
|
l.addi r26,r23,4
|
l.addi r26,r23,4
|
l.sfeq r3,r26
|
l.sfeq r3,r26
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i1c:
|
_i1c:
|
l.j _die
|
l.j _die
|
l.nop
|
l.nop
|
_i20:
|
_i20:
|
l.j _die
|
l.j _die
|
l.nop
|
l.nop
|
_i24:
|
_i24:
|
l.mfspr r26,r0,SPR_ESR_BASE
|
l.mfspr r26,r0,SPR_ESR_BASE
|
l.addi r30,r3,0
|
l.addi r30,r3,0
|
l.addi r3,r26,0
|
l.addi r3,r26,0
|
l.nop 2
|
l.nop 2
|
l.addi r3,r30,0
|
l.addi r3,r30,0
|
l.andi r26,r26,SPR_SR_F
|
l.andi r26,r26,SPR_SR_F
|
l.sfeq r26,r0
|
l.sfeq r26,r0
|
/* l.bnf _die */
|
/* l.bnf _die */
|
l.nop
|
l.nop
|
l.sfeqi r3,0xbbbb
|
l.sfeqi r3,0xbbbb
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i28:
|
_i28:
|
l.mfspr r26,r0,SPR_ESR_BASE
|
l.mfspr r26,r0,SPR_ESR_BASE
|
l.addi r30,r3,0
|
l.addi r30,r3,0
|
l.addi r3,r26,0
|
l.addi r3,r26,0
|
l.nop 2
|
l.nop 2
|
l.addi r3,r30,0
|
l.addi r3,r30,0
|
l.andi r26,r26,SPR_SR_F
|
l.andi r26,r26,SPR_SR_F
|
l.sfeq r26,r0
|
l.sfeq r26,r0
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.sfeqi r22,1
|
l.sfeqi r22,1
|
l.bf _resume
|
l.bf _resume
|
l.addi r22,r0,1
|
l.addi r22,r0,1
|
l.sfeqi r9,0xbbbb
|
l.sfeqi r9,0xbbbb
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i2c:
|
_i2c:
|
l.movhi r26,hi(_return_addr)
|
l.movhi r26,hi(_return_addr)
|
l.ori r26,r26,lo(_return_addr)
|
l.ori r26,r26,lo(_return_addr)
|
l.sfeq r9,r26
|
l.sfeq r9,r26
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.sfeqi r3,0xbbbb
|
l.sfeqi r3,0xbbbb
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i30:
|
_i30:
|
l.sfeqi r3,0x5678
|
l.sfeqi r3,0x5678
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i34:
|
_i34:
|
l.sfeqi r3,0x5678
|
l.sfeqi r3,0x5678
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.lwz r26,8(r23)
|
l.lwz r26,8(r23)
|
l.sfeqi r26,0xaaaa
|
l.sfeqi r26,0xaaaa
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
l.j _resume
|
l.j _resume
|
l.nop
|
l.nop
|
_i38:
|
_i38:
|
l.lwz r26,8(r23)
|
l.lwz r26,8(r23)
|
l.sfeqi r26,0x5678
|
l.sfeqi r26,0x5678
|
l.bnf _die
|
l.bnf _die
|
l.nop
|
l.nop
|
#
|
#
|
# mark finished ok
|
# mark finished ok
|
#
|
#
|
l.movhi r3,hi(0xdeaddead)
|
l.movhi r3,hi(0xdeaddead)
|
l.ori r3,r3,lo(0xdeaddead)
|
l.ori r3,r3,lo(0xdeaddead)
|
l.nop 2
|
l.nop 2
|
l.addi r3,r0,0
|
l.addi r3,r0,0
|
l.nop 1
|
l.nop 1
|
_ok:
|
_ok:
|
l.j _ok
|
l.j _ok
|
l.nop
|
l.nop
|
|
|
_resume:
|
_resume:
|
l.mfspr r27,r0,SPR_ESR_BASE
|
l.mfspr r27,r0,SPR_ESR_BASE
|
l.addi r26,r0,SPR_SR_TEE
|
l.addi r26,r0,SPR_SR_TEE
|
l.addi r28,r0,-1
|
l.addi r28,r0,-1
|
l.xor r26,r26,r28
|
l.xor r26,r26,r28
|
l.and r26,r26,r27
|
l.and r26,r26,r27
|
l.mtspr r0,r26,SPR_ESR_BASE
|
l.mtspr r0,r26,SPR_ESR_BASE
|
|
|
l.rfe
|
l.rfe
|
l.addi r3,r3,5 # should not be executed
|
l.addi r3,r3,5 # should not be executed
|
|
|
