/* mc_ssram.c - Memory Controller testbench SSRAM test
|
/* mc_ssram.c - Memory Controller testbench SSRAM test
|
|
|
Copyright (C) 2001 Ivan Guzvinec
|
Copyright (C) 2001 Ivan Guzvinec
|
Copyright (C) 2010 Embecosm Limited
|
Copyright (C) 2010 Embecosm Limited
|
|
|
Contributor Ivan Guzvinec <ivang@opencores.org>
|
Contributor Ivan Guzvinec <ivang@opencores.org>
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
|
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
|
|
This program is free software; you can redistribute it and/or modify it
|
This program is free software; you can redistribute it and/or modify it
|
under the terms of the GNU General Public License as published by the Free
|
under the terms of the GNU General Public License as published by the Free
|
Software Foundation; either version 3 of the License, or (at your option)
|
Software Foundation; either version 3 of the License, or (at your option)
|
any later version.
|
any later version.
|
|
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
This program is distributed in the hope that it will be useful, but WITHOUT
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
more details.
|
more details.
|
|
|
You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see <http: www.gnu.org/licenses/>. */
|
with this program. If not, see <http: www.gnu.org/licenses/>. */
|
|
|
/* ----------------------------------------------------------------------------
|
/* ----------------------------------------------------------------------------
|
This code is commented throughout for use with Doxygen.
|
This code is commented throughout for use with Doxygen.
|
--------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------*/
|
|
|
#include "support.h"
|
#include "support.h"
|
|
|
#include "mc-common.h"
|
#include "mc-common.h"
|
#include "mc-ssram.h"
|
#include "mc-ssram.h"
|
|
|
#include "config.h"
|
#include "config.h"
|
#include "mc-defines.h"
|
#include "mc-defines.h"
|
#include "gpio.h"
|
#include "gpio.h"
|
#include "fields.h"
|
#include "fields.h"
|
|
|
typedef volatile unsigned long *REGISTER;
|
typedef volatile unsigned long *REGISTER;
|
|
|
REGISTER mc_poc = (unsigned long*)(MC_BASE + MC_POC);
|
REGISTER mc_poc = (unsigned long*)(MC_BASE + MC_POC);
|
REGISTER mc_csr = (unsigned long*)(MC_BASE + MC_CSR);
|
REGISTER mc_csr = (unsigned long*)(MC_BASE + MC_CSR);
|
REGISTER mc_ba_mask = (unsigned long*)(MC_BASE + MC_BA_MASK);
|
REGISTER mc_ba_mask = (unsigned long*)(MC_BASE + MC_BA_MASK);
|
|
|
REGISTER rgpio_out = (unsigned long*)(GPIO_BASE + RGPIO_OUT);
|
REGISTER rgpio_out = (unsigned long*)(GPIO_BASE + RGPIO_OUT);
|
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
|
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
|
|
|
unsigned long lpoc;
|
unsigned long lpoc;
|
unsigned char mc_cs;
|
unsigned char mc_cs;
|
|
|
unsigned long set_config()
|
unsigned long set_config()
|
{
|
{
|
REGISTER mc_csc;
|
REGISTER mc_csc;
|
unsigned char ch;
|
unsigned char ch;
|
|
|
lpoc = *mc_poc;
|
lpoc = *mc_poc;
|
|
|
for (ch=0; ch<8; ch++) {
|
for (ch=0; ch<8; ch++) {
|
if (MC_SSRAM_CSMASK && (0x01 << ch) ) {
|
if (MC_SSRAM_CSMASK && (0x01 << ch) ) {
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
SET_FIELD(*mc_csc, MC_CSC, SEL, mc_ssram_cs[ch].M);
|
SET_FIELD(*mc_csc, MC_CSC, SEL, mc_ssram_cs[ch].M);
|
SET_FLAG(*mc_csc, MC_CSC, EN);
|
SET_FLAG(*mc_csc, MC_CSC, EN);
|
printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
|
printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
|
}
|
}
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
unsigned long get_config()
|
unsigned long get_config()
|
{
|
{
|
REGISTER mc_csc;
|
REGISTER mc_csc;
|
REGISTER mc_tms;
|
REGISTER mc_tms;
|
unsigned char ch;
|
unsigned char ch;
|
|
|
mc_cs = 0;
|
mc_cs = 0;
|
for (ch=0; ch<8; ch++) {
|
for (ch=0; ch<8; ch++) {
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
|
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
|
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 1) &&
|
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 1) &&
|
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
|
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
|
mc_ssram_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
|
mc_ssram_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
|
mc_cs |= (1 << ch);
|
mc_cs |= (1 << ch);
|
|
|
printf("get_config(%d) : M=0x%0lx\n", ch,
|
printf("get_config(%d) : M=0x%0lx\n", ch,
|
mc_ssram_cs[ch].M);
|
mc_ssram_cs[ch].M);
|
}
|
}
|
}
|
}
|
printf("get_config() : cs=0x%0x\n", mc_cs);
|
printf("get_config() : cs=0x%0x\n", mc_cs);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
int main()
|
int main()
|
{
|
{
|
unsigned long ret;
|
unsigned long ret;
|
unsigned char ch;
|
unsigned char ch;
|
|
|
unsigned long test;
|
unsigned long test;
|
unsigned long gpio_pat;
|
unsigned long gpio_pat = 0;
|
|
|
unsigned long nAddress;
|
unsigned long nAddress;
|
unsigned long nMemSize;
|
unsigned long nMemSize;
|
unsigned long mc_sel;
|
unsigned long mc_sel;
|
|
|
REGISTER mc_tms;
|
REGISTER mc_tms;
|
REGISTER mc_csc;
|
REGISTER mc_csc;
|
|
|
*rgpio_out = 0xFFFFFFFF;
|
*rgpio_out = 0xFFFFFFFF;
|
|
|
#ifdef MC_READ_CONF
|
#ifdef MC_READ_CONF
|
if (get_config()) {
|
if (get_config()) {
|
printf("Error reading MC configuration\n");
|
printf("Error reading MC configuration\n");
|
report(0x000000001);
|
report(0x000000001);
|
return(1);
|
return(1);
|
}
|
}
|
#else
|
#else
|
mc_cs = MC_SSRAM_CSMASK;
|
mc_cs = MC_SSRAM_CSMASK;
|
#endif
|
#endif
|
|
|
*rgpio_out = 0;
|
*rgpio_out = 0;
|
for (ch=0; ch<8; ch++) {
|
for (ch=0; ch<8; ch++) {
|
if (mc_cs & (0x01 << ch) ) {
|
if (mc_cs & (0x01 << ch) ) {
|
printf ("--- Begin Test on CS%d ---\n", ch);
|
printf ("--- Begin Test on CS%d ---\n", ch);
|
|
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
|
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
|
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
|
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
|
|
|
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
|
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
|
*mc_csc, *mc_tms);
|
*mc_csc, *mc_tms);
|
|
|
for (test=0; test<4; test++) {
|
for (test=0; test<4; test++) {
|
/* configure MC*/
|
/* configure MC*/
|
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
|
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
|
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
|
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
|
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
|
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
|
|
|
switch (test) {
|
switch (test) {
|
case 0:
|
case 0:
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST0) != MC_SSRAM_TEST0)
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST0) != MC_SSRAM_TEST0)
|
continue;
|
continue;
|
break;
|
break;
|
case 1:
|
case 1:
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST1) != MC_SSRAM_TEST1)
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST1) != MC_SSRAM_TEST1)
|
continue;
|
continue;
|
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
|
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
|
break;
|
break;
|
case 2:
|
case 2:
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST2) != MC_SSRAM_TEST2)
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST2) != MC_SSRAM_TEST2)
|
continue;
|
continue;
|
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
|
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
|
break;
|
break;
|
case 3:
|
case 3:
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST3) != MC_SSRAM_TEST3)
|
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST3) != MC_SSRAM_TEST3)
|
continue;
|
continue;
|
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
|
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
|
break;
|
break;
|
} /*switch test*/
|
} /*switch test*/
|
|
|
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
|
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
|
|
|
nAddress = mc_sel << 21;
|
nAddress = mc_sel << 21;
|
nAddress |= MC_MEM_BASE;
|
nAddress |= MC_MEM_BASE;
|
nMemSize = ( ((*mc_ba_mask && 0x000000FF) + 1) << 21);
|
nMemSize = ( ((*mc_ba_mask && 0x000000FF) + 1) << 21);
|
|
|
gpio_pat ^= 0x00000008;
|
gpio_pat ^= 0x00000008;
|
*rgpio_out = gpio_pat;
|
*rgpio_out = gpio_pat;
|
ret = mc_test_row(nAddress, nAddress + nMemSize, MC_SSRAM_FLAGS);
|
ret = mc_test_row(nAddress, nAddress + nMemSize, MC_SSRAM_FLAGS);
|
|
|
printf("\trow tested: nAddress = 0x%08lX, ret = 0x%08lX\n", nAddress, ret);
|
printf("\trow tested: nAddress = 0x%08lX, ret = 0x%08lX\n", nAddress, ret);
|
|
|
if (ret) {
|
if (ret) {
|
gpio_pat ^= 0x00000080;
|
gpio_pat ^= 0x00000080;
|
*rgpio_out = gpio_pat;
|
*rgpio_out = gpio_pat;
|
report(ret);
|
report(ret);
|
return ret;
|
return ret;
|
}
|
}
|
|
|
} /*for test*/
|
} /*for test*/
|
} /*if*/
|
} /*if*/
|
} /*for CS*/
|
} /*for CS*/
|
printf("--- End SSRAM tests ---\n");
|
printf("--- End SSRAM tests ---\n");
|
report(0xDEADDEAD);
|
report(0xDEADDEAD);
|
|
|
gpio_pat ^= 0x00000020;
|
gpio_pat ^= 0x00000020;
|
*rgpio_out = gpio_pat;
|
*rgpio_out = gpio_pat;
|
|
|
return 0;
|
return 0;
|
} /* main */
|
} /* main */
|
|
|
