/* except-or32.S Microkernel exception handler for Or1ksim
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/* except-or32.S Microkernel exception handler for Or1ksim
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Copyright (C) 2000 Damjan Lampret
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Copyright (C) 2000 Damjan Lampret
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Copyright (C) 2010 Embecosm Limited
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Copyright (C) 2010 Embecosm Limited
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Contributor Damjan Lampret
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Contributor Damjan Lampret
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* ----------------------------------------------------------------------------
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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--------------------------------------------------------------------------*/
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/* This file is part of test microkernel for OpenRISC 1000. */
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/* This file is part of test microkernel for OpenRISC 1000. */
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#define MC_CSR (0x00)
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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/*
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/*
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* Context is saved to area pointed by pointer in R3. Original
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* Context is saved to area pointed by pointer in R3. Original
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* R3 is at memory location 0 and task's PC is at memory location 4.
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* R3 is at memory location 0 and task's PC is at memory location 4.
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*/
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*/
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#define SAVEREGS \
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#define SAVEREGS \
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l.lwz r3,0(r3); \
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l.lwz r3,0(r3); \
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l.sw 4(r3),r1; \
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l.sw 4(r3),r1; \
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l.sw 8(r3),r2; \
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l.sw 8(r3),r2; \
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l.lwz r2,0(r0); /* saving original r3*/ \
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l.lwz r2,0(r0); /* saving original r3*/ \
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l.sw 12(r3),r2; \
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l.sw 12(r3),r2; \
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l.sw 16(r3),r4; \
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l.sw 16(r3),r4; \
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l.sw 20(r3),r5; \
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l.sw 20(r3),r5; \
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l.sw 24(r3),r6; \
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l.sw 24(r3),r6; \
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l.sw 28(r3),r7; \
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l.sw 28(r3),r7; \
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l.sw 32(r3),r8; \
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l.sw 32(r3),r8; \
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l.sw 36(r3),r9; \
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l.sw 36(r3),r9; \
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l.sw 40(r3),r10; \
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l.sw 40(r3),r10; \
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l.sw 44(r3),r11; \
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l.sw 44(r3),r11; \
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l.sw 48(r3),r12; \
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l.sw 48(r3),r12; \
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l.sw 52(r3),r13; \
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l.sw 52(r3),r13; \
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l.sw 56(r3),r14; \
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l.sw 56(r3),r14; \
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l.sw 60(r3),r15; \
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l.sw 60(r3),r15; \
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l.sw 64(r3),r16; \
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l.sw 64(r3),r16; \
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l.sw 68(r3),r17; \
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l.sw 68(r3),r17; \
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l.sw 72(r3),r18; \
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l.sw 72(r3),r18; \
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l.sw 76(r3),r19; \
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l.sw 76(r3),r19; \
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l.sw 80(r3),r20; \
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l.sw 80(r3),r20; \
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l.sw 84(r3),r21; \
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l.sw 84(r3),r21; \
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l.sw 88(r3),r22; \
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l.sw 88(r3),r22; \
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l.sw 92(r3),r23; \
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l.sw 92(r3),r23; \
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l.sw 96(r3),r24; \
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l.sw 96(r3),r24; \
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l.sw 100(r3),r25; \
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l.sw 100(r3),r25; \
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l.sw 104(r3),r26; \
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l.sw 104(r3),r26; \
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l.sw 108(r3),r27; \
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l.sw 108(r3),r27; \
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l.sw 112(r3),r28; \
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l.sw 112(r3),r28; \
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l.sw 116(r3),r29; \
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l.sw 116(r3),r29; \
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l.sw 120(r3),r30; \
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l.sw 120(r3),r30; \
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l.sw 124(r3),r31; \
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l.sw 124(r3),r31; \
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l.lwz r2,4(r0); /* saving original PC*/ \
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l.lwz r2,4(r0); /* saving original PC*/ \
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l.sw 0(r3),r2; \
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l.sw 0(r3),r2; \
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\
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\
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l.mfspr r2,r0,SPR_ESR_BASE; \
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l.mfspr r2,r0,SPR_ESR_BASE; \
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l.sw 128(r3),r2 /* saving SR */
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l.sw 128(r3),r2 /* saving SR */
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/*
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/*
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* Pointer to context is in R3. All registers are loaded and execution is
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* Pointer to context is in R3. All registers are loaded and execution is
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* transfered to the loaded context's task
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* transfered to the loaded context's task
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*/
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*/
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#define LOADREGS_N_GO \
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#define LOADREGS_N_GO \
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l.lwz r3,0(r3); \
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l.lwz r3,0(r3); \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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\
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\
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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\
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\
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l.lwz r1,4(r3); \
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l.lwz r1,4(r3); \
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l.lwz r2,8(r3); \
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l.lwz r2,8(r3); \
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l.lwz r4,16(r3); \
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l.lwz r4,16(r3); \
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l.lwz r5,20(r3); \
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l.lwz r5,20(r3); \
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l.lwz r6,24(r3); \
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l.lwz r6,24(r3); \
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l.lwz r7,28(r3); \
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l.lwz r7,28(r3); \
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l.lwz r8,32(r3); \
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l.lwz r8,32(r3); \
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l.lwz r9,36(r3); \
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l.lwz r9,36(r3); \
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l.lwz r10,40(r3); \
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l.lwz r10,40(r3); \
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l.lwz r11,44(r3); \
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l.lwz r11,44(r3); \
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l.lwz r12,48(r3); \
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l.lwz r12,48(r3); \
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l.lwz r13,52(r3); \
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l.lwz r13,52(r3); \
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l.lwz r14,56(r3); \
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l.lwz r14,56(r3); \
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l.lwz r15,60(r3); \
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l.lwz r15,60(r3); \
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l.lwz r16,64(r3); \
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l.lwz r16,64(r3); \
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l.lwz r17,68(r3); \
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l.lwz r17,68(r3); \
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l.lwz r18,72(r3); \
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l.lwz r18,72(r3); \
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l.lwz r19,76(r3); \
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l.lwz r19,76(r3); \
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l.lwz r20,80(r3); \
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l.lwz r20,80(r3); \
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l.lwz r21,84(r3); \
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l.lwz r21,84(r3); \
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l.lwz r22,88(r3); \
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l.lwz r22,88(r3); \
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l.lwz r23,92(r3); \
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l.lwz r23,92(r3); \
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l.lwz r24,96(r3); \
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l.lwz r24,96(r3); \
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l.lwz r25,100(r3); \
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l.lwz r25,100(r3); \
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l.lwz r26,104(r3); \
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l.lwz r26,104(r3); \
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l.lwz r27,108(r3); \
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l.lwz r27,108(r3); \
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l.lwz r28,112(r3); \
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l.lwz r28,112(r3); \
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l.lwz r29,116(r3); \
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l.lwz r29,116(r3); \
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l.lwz r30,120(r3); \
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l.lwz r30,120(r3); \
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l.lwz r31,124(r3); \
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l.lwz r31,124(r3); \
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\
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\
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l.lwz r3,12(r3); /* prepare r3*/ \
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l.lwz r3,12(r3); /* prepare r3*/ \
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\
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\
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l.rfe; /* Call task */ \
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l.rfe; /* Call task */ \
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l.nop
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l.nop
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/*
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/*
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* All registers are loaded from save area.
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* All registers are loaded from save area.
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*/
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*/
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#define LOADREGS \
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#define LOADREGS \
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l.lwz r3,0(r3); \
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l.lwz r3,0(r3); \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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\
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\
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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\
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\
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l.lwz r1,4(r3); \
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l.lwz r1,4(r3); \
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l.lwz r2,8(r3); \
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l.lwz r2,8(r3); \
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l.lwz r4,16(r3); \
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l.lwz r4,16(r3); \
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l.lwz r5,20(r3); \
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l.lwz r5,20(r3); \
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l.lwz r6,24(r3); \
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l.lwz r6,24(r3); \
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l.lwz r7,28(r3); \
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l.lwz r7,28(r3); \
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l.lwz r8,32(r3); \
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l.lwz r8,32(r3); \
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l.lwz r9,36(r3); \
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l.lwz r9,36(r3); \
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l.lwz r10,40(r3); \
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l.lwz r10,40(r3); \
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l.lwz r11,44(r3); \
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l.lwz r11,44(r3); \
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l.lwz r12,48(r3); \
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l.lwz r12,48(r3); \
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l.lwz r13,52(r3); \
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l.lwz r13,52(r3); \
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l.lwz r14,56(r3); \
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l.lwz r14,56(r3); \
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l.lwz r15,60(r3); \
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l.lwz r15,60(r3); \
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l.lwz r16,64(r3); \
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l.lwz r16,64(r3); \
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l.lwz r17,68(r3); \
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l.lwz r17,68(r3); \
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l.lwz r18,72(r3); \
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l.lwz r18,72(r3); \
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l.lwz r19,76(r3); \
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l.lwz r19,76(r3); \
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l.lwz r20,80(r3); \
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l.lwz r20,80(r3); \
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l.lwz r21,84(r3); \
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l.lwz r21,84(r3); \
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l.lwz r22,88(r3); \
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l.lwz r22,88(r3); \
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l.lwz r23,92(r3); \
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l.lwz r23,92(r3); \
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l.lwz r24,96(r3); \
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l.lwz r24,96(r3); \
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l.lwz r25,100(r3); \
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l.lwz r25,100(r3); \
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l.lwz r26,104(r3); \
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l.lwz r26,104(r3); \
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l.lwz r27,108(r3); \
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l.lwz r27,108(r3); \
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l.lwz r28,112(r3); \
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l.lwz r28,112(r3); \
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l.lwz r29,116(r3); \
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l.lwz r29,116(r3); \
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l.lwz r30,120(r3); \
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l.lwz r30,120(r3); \
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l.lwz r31,124(r3); \
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l.lwz r31,124(r3); \
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\
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\
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l.lwz r3,12(r3); /* prepare r3*/
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l.lwz r3,12(r3); /* prepare r3*/
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/*
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/*
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* Set new PC in saved context
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* Set new PC in saved context
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*/
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*/
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#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \
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#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \
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l.lwz AREA,0(AREA); \
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l.lwz AREA,0(AREA); \
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l.movhi TMPREG,hi(SUBROUTINE); \
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l.movhi TMPREG,hi(SUBROUTINE); \
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l.addi TMPREG,r0,lo(SUBROUTINE); \
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l.addi TMPREG,r0,lo(SUBROUTINE); \
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l.sw 0(AREA),TMPREG;
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l.sw 0(AREA),TMPREG;
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/*
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/*
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* Printf via or1ksim hook
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* Printf via or1ksim hook
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*/
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*/
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#if KERNEL_OUTPUT
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#if KERNEL_OUTPUT
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#define PRINTF(REG,STR) \
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#define PRINTF(REG,STR) \
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l.movhi REG,hi(STR); \
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l.movhi REG,hi(STR); \
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l.addi REG,r0,lo(STR); \
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l.addi REG,r0,lo(STR); \
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l.nop NOP_PRINTF
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l.nop NOP_PRINTF
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#else
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#else
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#define PRINTF(REG,STR)
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#define PRINTF(REG,STR)
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#endif
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#endif
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/*
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/*
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* Reset Exception handler
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* Reset Exception handler
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*/
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*/
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.org 0x100
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.org 0x100
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reset_vector:
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reset_vector:
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// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
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// and indeed it is not when simulating the or1200 Verilog core.
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l.andi r0,r0,0x0
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|
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l.movhi r3,hi(MC_BASE_ADDR)
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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|
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l.addi r4,r3,MC_CSC(0)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0025
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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|
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l.addi r4,r3,MC_TMS(0)
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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|
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l.addi r4,r3,MC_BA_MASK
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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|
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l.addi r4,r3,MC_CSR
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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|
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l.addi r4,r3,MC_TMS(1)
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
|
|
|
l.addi r4,r3,MC_CSC(1)
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0411
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
|
l.sw 0(r4),r5
|
|
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
/* Copy data section */
|
/* Copy data section */
|
l.movhi r3,hi(_src_beg)
|
l.movhi r3,hi(_src_beg)
|
l.ori r3,r3,lo(_src_beg)
|
l.ori r3,r3,lo(_src_beg)
|
l.addi r4,r0,0x200
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l.addi r4,r0,0x200
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l.movhi r5,hi(_except_end)
|
l.movhi r5,hi(_except_end)
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l.ori r5,r5,lo(_except_end)
|
l.ori r5,r5,lo(_except_end)
|
l.movhi r6,hi(_except_beg)
|
l.movhi r6,hi(_except_beg)
|
l.ori r6,r6,lo(_except_beg)
|
l.ori r6,r6,lo(_except_beg)
|
l.sub r5,r6,r5
|
l.sub r5,r6,r5
|
1:
|
1:
|
l.lwz r6,0(r3)
|
l.lwz r6,0(r3)
|
l.sw 0(r4),r6
|
l.sw 0(r4),r6
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
l.addi r4,r4,4
|
l.addi r4,r4,4
|
l.addi r5,r5,-4
|
l.addi r5,r5,-4
|
l.sfgtsi r5,0
|
l.sfgtsi r5,0
|
l.bf 1b
|
l.bf 1b
|
l.nop
|
l.nop
|
|
|
l.movhi r4,hi(_dst_beg)
|
l.movhi r4,hi(_dst_beg)
|
l.ori r4,r4,lo(_dst_beg)
|
l.ori r4,r4,lo(_dst_beg)
|
l.movhi r5,hi(_dst_end)
|
l.movhi r5,hi(_dst_end)
|
l.ori r5,r5,lo(_dst_end)
|
l.ori r5,r5,lo(_dst_end)
|
l.sub r5,r5,r4
|
l.sub r5,r5,r4
|
l.sfeqi r5,0
|
l.sfeqi r5,0
|
l.bf 2f
|
l.bf 2f
|
l.nop
|
l.nop
|
1:
|
1:
|
l.lwz r6,0(r3)
|
l.lwz r6,0(r3)
|
l.sw 0(r4),r6
|
l.sw 0(r4),r6
|
l.addi r3,r3,4
|
l.addi r3,r3,4
|
l.addi r4,r4,4
|
l.addi r4,r4,4
|
l.addi r5,r5,-4
|
l.addi r5,r5,-4
|
l.sfgtsi r5,0
|
l.sfgtsi r5,0
|
l.bf 1b
|
l.bf 1b
|
l.nop
|
l.nop
|
|
|
2:
|
2:
|
|
|
|
|
l.movhi r2,hi(reset)
|
l.movhi r2,hi(reset)
|
l.ori r2,r2,lo(reset)
|
l.ori r2,r2,lo(reset)
|
l.jr r2
|
l.jr r2
|
l.nop
|
l.nop
|
|
|
/*
|
/*
|
* Switch to a new context pointed by task_context
|
* Switch to a new context pointed by task_context
|
*/
|
*/
|
.global dispatch
|
.global dispatch
|
.align 4
|
.align 4
|
dispatch:
|
dispatch:
|
/* load user task GPRs and PC */
|
/* load user task GPRs and PC */
|
l.movhi r3,hi(task_context)
|
l.movhi r3,hi(task_context)
|
l.addi r3,r0,lo(task_context)
|
l.addi r3,r0,lo(task_context)
|
LOADREGS_N_GO
|
LOADREGS_N_GO
|
|
|
.section .except, "ax"
|
.section .except, "ax"
|
|
|
/*
|
/*
|
* Bus Error Exception handler
|
* Bus Error Exception handler
|
*/
|
*/
|
.org 0x0200
|
.org 0x0200
|
buserr:
|
buserr:
|
l.nop
|
l.nop
|
l.sw 0(r0),r3 /* Save r3 */
|
l.sw 0(r0),r3 /* Save r3 */
|
PRINTF(r3, buserr_str)
|
PRINTF(r3, buserr_str)
|
hang:
|
hang:
|
l.j hang
|
l.j hang
|
l.nop
|
l.nop
|
|
|
buserr_str:
|
buserr_str:
|
.ascii "Bus error exception.\n\000"
|
.ascii "Bus error exception.\n\000"
|
|
|
/*
|
/*
|
* External Interrupt Exception handler
|
* External Interrupt Exception handler
|
*/
|
*/
|
.org 0x800
|
.org 0x800
|
extint:
|
extint:
|
l.nop
|
l.nop
|
l.sw 0(r0),r3 /* Save r3 */
|
l.sw 0(r0),r3 /* Save r3 */
|
PRINTF(r3,extint_str)
|
PRINTF(r3,extint_str)
|
l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
|
l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
|
l.sw 4(r0),r3 /* and save it */
|
l.sw 4(r0),r3 /* and save it */
|
|
|
/* now save user task context */
|
/* now save user task context */
|
l.movhi r3,hi(task_context)
|
l.movhi r3,hi(task_context)
|
l.addi r3,r0,lo(task_context)
|
l.addi r3,r0,lo(task_context)
|
SAVEREGS
|
SAVEREGS
|
|
|
/* set kernel context's PC to kernel's scheduler */
|
/* set kernel context's PC to kernel's scheduler */
|
l.movhi r3,hi(kernel_context)
|
l.movhi r3,hi(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
SET_CONTEXTPC(r3,int_main,r4)
|
SET_CONTEXTPC(r3,int_main,r4)
|
|
|
/* load kernel context */
|
/* load kernel context */
|
l.movhi r3,hi(kernel_context)
|
l.movhi r3,hi(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
LOADREGS
|
LOADREGS
|
|
|
l.movhi r3,hi(int_main)
|
l.movhi r3,hi(int_main)
|
l.addi r3,r0,lo(int_main)
|
l.addi r3,r0,lo(int_main)
|
l.jr r3
|
l.jr r3
|
l.nop
|
l.nop
|
|
|
extint_str:
|
extint_str:
|
.ascii "External interrupt exception.\n\000"
|
.ascii "External interrupt exception.\n\000"
|
|
|
/*
|
/*
|
* System Call Exception handler
|
* System Call Exception handler
|
*/
|
*/
|
.org 0x0c00
|
.org 0x0c00
|
syscall:
|
syscall:
|
l.nop
|
l.nop
|
l.sw 0(r0),r3 /* Save r3 */
|
l.sw 0(r0),r3 /* Save r3 */
|
PRINTF(r3,syscall_str)
|
PRINTF(r3,syscall_str)
|
l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
|
l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
|
l.addi r3,r3,4 /* increment because EPCR instruction was already executed */
|
l.addi r3,r3,4 /* increment because EPCR instruction was already executed */
|
l.sw 4(r0),r3 /* and save it */
|
l.sw 4(r0),r3 /* and save it */
|
|
|
/* now save user task context */
|
/* now save user task context */
|
l.movhi r3,hi(task_context)
|
l.movhi r3,hi(task_context)
|
l.addi r3,r0,lo(task_context)
|
l.addi r3,r0,lo(task_context)
|
SAVEREGS
|
SAVEREGS
|
|
|
/* set kernel context's PC to kernel's syscall entry */
|
/* set kernel context's PC to kernel's syscall entry */
|
l.movhi r3,hi(kernel_context)
|
l.movhi r3,hi(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
SET_CONTEXTPC(r3,kernel_syscall,r4)
|
SET_CONTEXTPC(r3,kernel_syscall,r4)
|
|
|
/* load kernel context */
|
/* load kernel context */
|
l.movhi r3,hi(kernel_context)
|
l.movhi r3,hi(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
l.addi r3,r0,lo(kernel_context)
|
LOADREGS_N_GO
|
LOADREGS_N_GO
|
|
|
syscall_str:
|
syscall_str:
|
.ascii "System call exception.\n\000"
|
.ascii "System call exception.\n\000"
|
|
|
|
|
|
|
