/* tick.c -- Simulation of OpenRISC 1000 tick timer
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/* tick.c -- Simulation of OpenRISC 1000 tick timer
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* This is functional simulation of OpenRISC 1000 architectural tick timer */
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/* This is functional simulation of OpenRISC 1000 architectural tick timer */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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/* Package includes */
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/* Package includes */
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "tick.h"
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#include "tick.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "pic.h"
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#include "pic.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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/*! When did the timer start to count */
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/*! When did the timer start to count */
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static long long cycles_start = 0;
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static long long cycle_count_at_tick_start = 0;
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/*! Indicates if the timer is actually counting. Needed to simulate one-shot
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/*! Indicates if the timer is actually counting. Needed to simulate one-shot
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mode correctly */
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mode correctly */
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int tick_count;
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int tick_counting;
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/*! Reset. It initializes TTCR register. */
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/*! Reset. It initializes TTCR register. */
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void
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void
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tick_reset (void)
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tick_reset (void)
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{
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{
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if (config.sim.verbose)
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if (config.sim.verbose)
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{
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{
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PRINTF ("Resetting Tick Timer.\n");
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PRINTF ("Resetting Tick Timer.\n");
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}
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}
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cpu_state.sprs[SPR_TTCR] = 0;
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cpu_state.sprs[SPR_TTCR] = 0;
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cpu_state.sprs[SPR_TTMR] = 0;
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cpu_state.sprs[SPR_TTMR] = 0;
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tick_count = 0;
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tick_counting = 0;
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}
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}
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/*! Raises a timer exception */
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/*! Raises a timer exception */
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static void
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static void
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tick_raise_except (void *dat)
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tick_raise_except (void *dat)
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{
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{
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cpu_state.sprs[SPR_TTMR] |= SPR_TTMR_IP;
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cpu_state.sprs[SPR_TTMR] |= SPR_TTMR_IP;
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/* Reschedule unconditionally, since we have to raise the exception until
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/* Reschedule unconditionally, since we have to raise the exception until
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* TTMR_IP has been cleared */
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* TTMR_IP has been cleared */
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sched_next_insn (tick_raise_except, NULL);
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sched_next_insn (tick_raise_except, NULL);
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/* be sure not to issue a timer exception if an exception occured before it */
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/* be sure not to issue a timer exception if an exception occured before it */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_TEE)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_TEE)
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{
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{
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except_handle (EXCEPT_TICK, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle (EXCEPT_TICK, cpu_state.sprs[SPR_EEAR_BASE]);
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}
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}
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}
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}
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/*! Restarts the tick timer */
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/*! Restarts the tick timer */
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static void
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static void
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tick_restart (void *dat)
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tick_restart (void *dat)
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{
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{
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cpu_state.sprs[SPR_TTCR] = 0;
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cpu_state.sprs[SPR_TTCR] = 0;
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cycles_start = runtime.sim.cycles;
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cycle_count_at_tick_start = runtime.sim.cycles;
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SCHED_ADD (tick_restart, NULL, cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP);
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SCHED_ADD (tick_restart, NULL, cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP);
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}
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}
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/*! Stops the timer */
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/*! Stops the timer */
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static void
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static void
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tick_one_shot (void *dat)
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tick_one_shot (void *dat)
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{
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{
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cpu_state.sprs[SPR_TTCR] = cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP;
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cpu_state.sprs[SPR_TTCR] = cpu_state.sprs[SPR_TTMR] & SPR_TTMR_TP;
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tick_count = 0;
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tick_counting = 0;
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}
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}
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/*! Schedules the timer jobs */
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/*! Schedules the timer jobs */
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static void
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static void
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sched_timer_job (uorreg_t prev_ttmr)
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sched_timer_job (uorreg_t prev_ttmr)
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{
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{
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uorreg_t ttmr = cpu_state.sprs[SPR_TTMR];
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uorreg_t ttmr = cpu_state.sprs[SPR_TTMR];
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uint32_t match_time = ttmr & SPR_TTMR_TP;
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uint32_t match_ttmr = ttmr & SPR_TTMR_TP;
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uint32_t ttcr_period = spr_read_ttcr () & SPR_TTCR_CNT;
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/* TTCR register, only concerned with part of TTCR which will trigger int */
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uint32_t match_ttcr = spr_read_ttcr () & SPR_TTMR_TP;
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uint32_t cycles_until_except;
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/* Remove previous jobs if they exists */
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/* On clearing TTMR interrupt signal bit remove previous jobs if they
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exist */
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if ((prev_ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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if ((prev_ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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{
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{
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SCHED_FIND_REMOVE (tick_raise_except, NULL);
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SCHED_FIND_REMOVE (tick_raise_except, NULL);
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}
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}
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switch (prev_ttmr & SPR_TTMR_M)
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switch (prev_ttmr & SPR_TTMR_M)
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{
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{
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case SPR_TTMR_RT:
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case SPR_TTMR_RT:
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SCHED_FIND_REMOVE (tick_restart, NULL);
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SCHED_FIND_REMOVE (tick_restart, NULL);
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break;
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break;
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case SPR_TTMR_SR:
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case SPR_TTMR_SR:
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SCHED_FIND_REMOVE (tick_one_shot, NULL);
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SCHED_FIND_REMOVE (tick_one_shot, NULL);
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break;
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break;
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}
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}
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if (match_time >= ttcr_period)
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/* Calculate cycles until next tick exception, based on current TTCR value */
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if (match_ttmr >= match_ttcr)
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{
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{
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match_time -= ttcr_period;
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cycles_until_except = match_ttmr - match_ttcr;
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}
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}
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else
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else
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{
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{
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match_time += (0xfffffffu - ttcr_period) + 1;
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/* Cycles after "wrap" of section of TTCR which will cause a match and,
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potentially, an exception */
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cycles_until_except = match_ttmr + (0x0fffffffu - match_ttcr) + 1;
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}
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}
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switch (ttmr & SPR_TTMR_M)
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switch (ttmr & SPR_TTMR_M)
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{
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{
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case 0: /* Disabled timer */
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case 0: /* Disabled timer */
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if (!match_time && (ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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if (!cycles_until_except && (ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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SCHED_ADD (tick_raise_except, NULL, 0);
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SCHED_ADD (tick_raise_except, NULL, 0);
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break;
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break;
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case SPR_TTMR_RT: /* Auto-restart timer */
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case SPR_TTMR_RT: /* Auto-restart timer */
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SCHED_ADD (tick_restart, NULL, match_time);
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SCHED_ADD (tick_restart, NULL, cycles_until_except);
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if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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SCHED_ADD (tick_raise_except, NULL, match_time);
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SCHED_ADD (tick_raise_except, NULL, cycles_until_except);
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break;
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break;
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case SPR_TTMR_SR: /* One-shot timer */
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case SPR_TTMR_SR: /* One-shot timer */
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if (tick_count)
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if (tick_counting)
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{
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{
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SCHED_ADD (tick_one_shot, NULL, match_time);
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SCHED_ADD (tick_one_shot, NULL, cycles_until_except);
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if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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SCHED_ADD (tick_raise_except, NULL, match_time);
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SCHED_ADD (tick_raise_except, NULL, cycles_until_except);
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}
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}
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break;
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break;
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case SPR_TTMR_CR: /* Continuos timer */
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case SPR_TTMR_CR: /* Continuos timer */
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if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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if ((ttmr & SPR_TTMR_IE) && !(ttmr & SPR_TTMR_IP))
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SCHED_ADD (tick_raise_except, NULL, match_time);
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SCHED_ADD (tick_raise_except, NULL, cycles_until_except);
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}
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}
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}
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}
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/*! Handles a write to the ttcr spr */
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/*! Handles a write to the ttcr spr */
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void
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void
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spr_write_ttcr (uorreg_t value)
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spr_write_ttcr (uorreg_t value)
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{
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{
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cycles_start = runtime.sim.cycles - value;
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cycle_count_at_tick_start = runtime.sim.cycles - value;
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sched_timer_job (cpu_state.sprs[SPR_TTMR]);
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sched_timer_job (cpu_state.sprs[SPR_TTMR]);
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}
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}
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/*! Value is the *previous* value of SPR_TTMR. The new one can be found in
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/*! prev_val is the *previous* value of SPR_TTMR. The new one can be found in
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cpu_state.sprs[SPR_TTMR] */
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cpu_state.sprs[SPR_TTMR] */
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void
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void
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spr_write_ttmr (uorreg_t prev_val)
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spr_write_ttmr (uorreg_t prev_val)
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{
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{
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uorreg_t value = cpu_state.sprs[SPR_TTMR];
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uorreg_t value = cpu_state.sprs[SPR_TTMR];
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/* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
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/* Code running on or1k can't set SPR_TTMR_IP so make sure it isn't */
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cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
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cpu_state.sprs[SPR_TTMR] &= ~SPR_TTMR_IP;
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/* If the timer was already disabled, ttcr should not be updated */
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/* If the timer was already disabled, ttcr should not be updated */
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if (tick_count)
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if (tick_counting)
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{
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{
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cpu_state.sprs[SPR_TTCR] = runtime.sim.cycles - cycles_start;
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cpu_state.sprs[SPR_TTCR] = runtime.sim.cycles - cycle_count_at_tick_start;
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}
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}
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cycles_start = runtime.sim.cycles - cpu_state.sprs[SPR_TTCR];
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cycle_count_at_tick_start = runtime.sim.cycles - cpu_state.sprs[SPR_TTCR];
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tick_count = value & SPR_TTMR_M;
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tick_counting = value & SPR_TTMR_M;
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if ((tick_count == 0xc0000000) &&
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/* If TTCR==TTMR_TP when setting MR, we disable counting??
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I think this should be looked at - Julius */
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if ((tick_counting == SPR_TTMR_CR) &&
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(cpu_state.sprs[SPR_TTCR] == (value & SPR_TTMR_TP)))
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(cpu_state.sprs[SPR_TTCR] == (value & SPR_TTMR_TP)))
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{
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{
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tick_count = 0;
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tick_counting = 0;
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}
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}
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sched_timer_job (prev_val);
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sched_timer_job (prev_val);
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}
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}
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uorreg_t
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uorreg_t
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spr_read_ttcr ()
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spr_read_ttcr ()
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{
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{
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uorreg_t ret;
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uorreg_t ret;
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if (!tick_count)
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if (!tick_counting)
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{
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{
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/* Report the time when the counter stoped (and don't carry on
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/* Report the time when the counter stopped (and don't carry on
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counting) */
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counting) */
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ret = cpu_state.sprs[SPR_TTCR];
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ret = cpu_state.sprs[SPR_TTCR];
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}
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}
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else
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else
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{
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{
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ret = runtime.sim.cycles - cycles_start;
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ret = runtime.sim.cycles - cycle_count_at_tick_start;
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}
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}
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return ret;
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return ret;
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}
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}
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