// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// SystemC GDB RSP server: definition
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// SystemC GDB RSP server: definition
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// This file is part of the GDB interface to the cycle accurate model of the
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// This file is part of the GDB interface to the cycle accurate model of the
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// This program is free software: you can redistribute it and/or modify it
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// This program is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or (at your
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// the Free Software Foundation, either version 3 of the License, or (at your
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// option) any later version.
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// option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// $Id$
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// $Id$
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#ifndef GDB_SERVER_SC__H
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#ifndef GDB_SERVER_SC__H
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#define GDB_SERVER_SC__H
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#define GDB_SERVER_SC__H
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#include <stdint.h>
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#include <stdint.h>
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#include "systemc"
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#include "systemc"
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#include "JtagSC_includes.h"
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#include "JtagSC_includes.h"
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#include "OrpsocAccess.h"
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#include "OrpsocAccess.h"
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#include "RspConnection.h"
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#include "RspConnection.h"
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#include "MpHash.h"
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#include "MpHash.h"
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#include "RspPacket.h"
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#include "RspPacket.h"
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#include "DebugUnitSC.h"
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#include "DebugUnitSC.h"
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//! Module implementing a GDB RSP server.
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//! Module implementing a GDB RSP server.
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//! A thread listens for RSP requests, which are converted to requests to read
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//! A thread listens for RSP requests, which are converted to requests to read
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//! and write registers, memory or control the CPU in the debug unit
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//! and write registers, memory or control the CPU in the debug unit
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class GdbServerSC
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class GdbServerSC:public sc_core::sc_module {
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: public sc_core::sc_module
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{
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public:
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public:
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// Constructor and destructor
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// Constructor and destructor
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GdbServerSC (sc_core::sc_module_name name,
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GdbServerSC(sc_core::sc_module_name name,
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uint32_t _flashStart,
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uint32_t _flashStart,
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uint32_t _flashEnd,
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uint32_t _flashEnd,
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int rspPort,
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int rspPort,
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sc_core::sc_fifo<TapAction *> *tapActionQueue);
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sc_core::sc_fifo < TapAction * >*tapActionQueue);
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~GdbServerSC ();
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~GdbServerSC ();
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private:
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private:
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//! Definition of GDB target signals.
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//! Definition of GDB target signals.
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//! Data taken from the GDB 6.8 source. Only those we use defined here.
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//! Data taken from the GDB 6.8 source. Only those we use defined here.
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enum TargetSignal {
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enum TargetSignal {
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TARGET_SIGNAL_NONE = 0,
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TARGET_SIGNAL_NONE = 0,
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TARGET_SIGNAL_INT = 2,
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TARGET_SIGNAL_INT = 2,
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TARGET_SIGNAL_ILL = 4,
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TARGET_SIGNAL_ILL = 4,
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TARGET_SIGNAL_TRAP = 5,
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TARGET_SIGNAL_TRAP = 5,
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TARGET_SIGNAL_FPE = 8,
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TARGET_SIGNAL_FPE = 8,
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TARGET_SIGNAL_BUS = 10,
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TARGET_SIGNAL_BUS = 10,
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TARGET_SIGNAL_SEGV = 11,
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TARGET_SIGNAL_SEGV = 11,
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TARGET_SIGNAL_ALRM = 14,
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TARGET_SIGNAL_ALRM = 14,
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TARGET_SIGNAL_USR2 = 31,
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TARGET_SIGNAL_USR2 = 31,
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TARGET_SIGNAL_PWR = 32
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TARGET_SIGNAL_PWR = 32
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};
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};
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// Register numbering. Matches GDB client
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// Register numbering. Matches GDB client
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static const int MAX_SPRS = 0x10000; //!< Max number of OR1K SPRs
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static const int MAX_SPRS = 0x10000; //!< Max number of OR1K SPRs
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static const int max_gprs = 32; //!< Max number of OR1K GPRs
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static const int max_gprs = 32; //!< Max number of OR1K GPRs
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static const int PPC_REGNUM = max_gprs + 0; //!< Previous PC
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static const int PPC_REGNUM = max_gprs + 0; //!< Previous PC
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static const int NPC_REGNUM = max_gprs + 1; //!< Next PC
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static const int NPC_REGNUM = max_gprs + 1; //!< Next PC
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static const int SR_REGNUM = max_gprs + 2; //!< Supervision Register
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static const int SR_REGNUM = max_gprs + 2; //!< Supervision Register
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static const int NUM_REGS = max_gprs + 3; //!< Total GDB registers
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static const int NUM_REGS = max_gprs + 3; //!< Total GDB registers
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//! Maximum size of a GDB RSP packet
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//! Maximum size of a GDB RSP packet
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//static const int RSP_PKT_MAX = NUM_REGS * 8 + 1;
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//static const int RSP_PKT_MAX = NUM_REGS * 8 + 1;
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static const int RSP_PKT_MAX = 1024*16;
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static const int RSP_PKT_MAX = 1024 * 16;
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// OpenRISC exception addresses. Only the ones we need to know about
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// OpenRISC exception addresses. Only the ones we need to know about
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static const uint32_t EXCEPT_NONE = 0x000; //!< No exception
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static const uint32_t EXCEPT_NONE = 0x000; //!< No exception
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static const uint32_t EXCEPT_RESET = 0x100; //!< Reset
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static const uint32_t EXCEPT_RESET = 0x100; //!< Reset
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// SPR numbers
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// SPR numbers
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static const uint16_t SPR_NPC = 0x0010; //!< Next program counter
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static const uint16_t SPR_NPC = 0x0010; //!< Next program counter
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static const uint16_t SPR_SR = 0x0011; //!< Supervision register
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static const uint16_t SPR_SR = 0x0011; //!< Supervision register
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static const uint16_t SPR_PPC = 0x0012; //!< Previous program counter
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static const uint16_t SPR_PPC = 0x0012; //!< Previous program counter
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static const uint16_t SPR_GPR0 = 0x0400; //!< GPR 0
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static const uint16_t SPR_GPR0 = 0x0400; //!< GPR 0
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static const uint16_t SPR_DVR0 = 0x3000; //!< Debug value register 0
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static const uint16_t SPR_DVR0 = 0x3000; //!< Debug value register 0
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static const uint16_t SPR_DVR1 = 0x3001; //!< Debug value register 1
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static const uint16_t SPR_DVR1 = 0x3001; //!< Debug value register 1
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static const uint16_t SPR_DVR2 = 0x3002; //!< Debug value register 2
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static const uint16_t SPR_DVR2 = 0x3002; //!< Debug value register 2
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static const uint16_t SPR_DVR3 = 0x3003; //!< Debug value register 3
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static const uint16_t SPR_DVR3 = 0x3003; //!< Debug value register 3
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static const uint16_t SPR_DVR4 = 0x3004; //!< Debug value register 4
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static const uint16_t SPR_DVR4 = 0x3004; //!< Debug value register 4
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static const uint16_t SPR_DVR5 = 0x3005; //!< Debug value register 5
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static const uint16_t SPR_DVR5 = 0x3005; //!< Debug value register 5
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static const uint16_t SPR_DVR6 = 0x3006; //!< Debug value register 6
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static const uint16_t SPR_DVR6 = 0x3006; //!< Debug value register 6
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static const uint16_t SPR_DVR7 = 0x3007; //!< Debug value register 7
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static const uint16_t SPR_DVR7 = 0x3007; //!< Debug value register 7
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static const uint16_t SPR_DCR0 = 0x3008; //!< Debug control register 0
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static const uint16_t SPR_DCR0 = 0x3008; //!< Debug control register 0
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static const uint16_t SPR_DCR1 = 0x3009; //!< Debug control register 1
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static const uint16_t SPR_DCR1 = 0x3009; //!< Debug control register 1
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static const uint16_t SPR_DCR2 = 0x300a; //!< Debug control register 2
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static const uint16_t SPR_DCR2 = 0x300a; //!< Debug control register 2
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static const uint16_t SPR_DCR3 = 0x300b; //!< Debug control register 3
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static const uint16_t SPR_DCR3 = 0x300b; //!< Debug control register 3
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static const uint16_t SPR_DCR4 = 0x300c; //!< Debug control register 4
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static const uint16_t SPR_DCR4 = 0x300c; //!< Debug control register 4
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static const uint16_t SPR_DCR5 = 0x300d; //!< Debug control register 5
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static const uint16_t SPR_DCR5 = 0x300d; //!< Debug control register 5
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static const uint16_t SPR_DCR6 = 0x300e; //!< Debug control register 6
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static const uint16_t SPR_DCR6 = 0x300e; //!< Debug control register 6
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static const uint16_t SPR_DCR7 = 0x300f; //!< Debug control register 7
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static const uint16_t SPR_DCR7 = 0x300f; //!< Debug control register 7
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static const uint16_t SPR_DMR1 = 0x3010; //!< Debug mode register 1
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static const uint16_t SPR_DMR1 = 0x3010; //!< Debug mode register 1
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static const uint16_t SPR_DMR2 = 0x3011; //!< Debug mode register 2
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static const uint16_t SPR_DMR2 = 0x3011; //!< Debug mode register 2
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static const uint16_t SPR_DSR = 0x3014; //!< Debug stop register
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static const uint16_t SPR_DSR = 0x3014; //!< Debug stop register
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static const uint16_t SPR_DRR = 0x3015; //!< Debug reason register
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static const uint16_t SPR_DRR = 0x3015; //!< Debug reason register
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// SPR masks and offsets
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// SPR masks and offsets
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static const uint32_t SPR_DMR1_ST = 0x00400000; //!< Single-step trace
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static const uint32_t SPR_DMR1_ST = 0x00400000; //!< Single-step trace
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static const uint32_t SPR_DMR2_WGB = 0x003ff000; //!< W/pt generating B/pt
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static const uint32_t SPR_DMR2_WGB = 0x003ff000; //!< W/pt generating B/pt
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static const uint32_t SPR_DMR2_WBS = 0xffc00000; //!< W/pt B/pt status
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static const uint32_t SPR_DMR2_WBS = 0xffc00000; //!< W/pt B/pt status
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static const uint32_t SPR_DSR_TE = 0x00002000; //!< Trap
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static const uint32_t SPR_DSR_TE = 0x00002000; //!< Trap
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static const uint32_t SPR_DCR_DP_MASK = 0x00000001; //!< Debug Pair Present
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static const uint32_t SPR_DCR_DP_MASK = 0x00000001; //!< Debug Pair Present
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static const uint32_t SPR_DCR_CC_MASK = 0x0000000e; //!< Compare Condition
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static const uint32_t SPR_DCR_CC_MASK = 0x0000000e; //!< Compare Condition
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static const uint32_t SPR_DCR_SC_MASK = 0x00000010; //!< Signed Comparison
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static const uint32_t SPR_DCR_SC_MASK = 0x00000010; //!< Signed Comparison
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static const uint32_t SPR_DCR_CT_MASK = 0x000000e0; //!< Compare To
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static const uint32_t SPR_DCR_CT_MASK = 0x000000e0; //!< Compare To
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static const uint32_t SPR_DMR2_WGB_SHIFT = 12; //!< W/pt Generate B/pt
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static const uint32_t SPR_DMR2_WGB_SHIFT = 12; //!< W/pt Generate B/pt
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// DRR (Debug Reason Register) Bits
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// DRR (Debug Reason Register) Bits
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static const uint32_t SPR_DRR_RSTE = 0x00000001; //!< Reset
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static const uint32_t SPR_DRR_RSTE = 0x00000001; //!< Reset
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static const uint32_t SPR_DRR_BUSEE = 0x00000002; //!< Bus error
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static const uint32_t SPR_DRR_BUSEE = 0x00000002; //!< Bus error
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static const uint32_t SPR_DRR_DPFE = 0x00000004; //!< Data page fault
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static const uint32_t SPR_DRR_DPFE = 0x00000004; //!< Data page fault
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static const uint32_t SPR_DRR_IPFE = 0x00000008; //!< Insn page fault
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static const uint32_t SPR_DRR_IPFE = 0x00000008; //!< Insn page fault
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static const uint32_t SPR_DRR_TTE = 0x00000010; //!< Tick timer
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static const uint32_t SPR_DRR_TTE = 0x00000010; //!< Tick timer
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static const uint32_t SPR_DRR_AE = 0x00000020; //!< Alignment
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static const uint32_t SPR_DRR_AE = 0x00000020; //!< Alignment
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static const uint32_t SPR_DRR_IIE = 0x00000040; //!< Illegal instruction
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static const uint32_t SPR_DRR_IIE = 0x00000040; //!< Illegal instruction
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static const uint32_t SPR_DRR_IE = 0x00000080; //!< Interrupt
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static const uint32_t SPR_DRR_IE = 0x00000080; //!< Interrupt
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static const uint32_t SPR_DRR_DME = 0x00000100; //!< DTLB miss
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static const uint32_t SPR_DRR_DME = 0x00000100; //!< DTLB miss
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static const uint32_t SPR_DRR_IME = 0x00000200; //!< ITLB miss
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static const uint32_t SPR_DRR_IME = 0x00000200; //!< ITLB miss
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static const uint32_t SPR_DRR_RE = 0x00000400; //!< Range fault
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static const uint32_t SPR_DRR_RE = 0x00000400; //!< Range fault
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static const uint32_t SPR_DRR_SCE = 0x00000800; //!< System call
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static const uint32_t SPR_DRR_SCE = 0x00000800; //!< System call
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static const uint32_t SPR_DRR_FPE = 0x00001000; //!< Floating point
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static const uint32_t SPR_DRR_FPE = 0x00001000; //!< Floating point
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static const uint32_t SPR_DRR_TE = 0x00002000; //!< Trap
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static const uint32_t SPR_DRR_TE = 0x00002000; //!< Trap
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//! RSP Signal valu
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//! RSP Signal valu
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uint32_t rsp_sigval;
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uint32_t rsp_sigval;
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//! Trap instruction for OR32
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//! Trap instruction for OR32
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static const uint32_t OR1K_TRAP_INSTR = 0x21000001;
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static const uint32_t OR1K_TRAP_INSTR = 0x21000001;
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//! Thread ID used by Or1ksim
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//! Thread ID used by Or1ksim
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static const int OR1KSIM_TID = 1;
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static const int OR1KSIM_TID = 1;
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// The bounds of flash memory
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// The bounds of flash memory
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uint32_t flashStart; //<! Start of flash memory
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uint32_t flashStart; //<! Start of flash memory
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uint32_t flashEnd; //<! End of flash memory
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uint32_t flashEnd; //<! End of flash memory
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//! Our associated Debug Unit
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//! Our associated Debug Unit
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DebugUnitSC *debugUnit;
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DebugUnitSC *debugUnit;
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//! Our associated RSP interface (which we create)
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//! Our associated RSP interface (which we create)
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RspConnection *rsp;
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RspConnection *rsp;
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//! The packet pointer. There is only ever one packet in use at one time, so
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//! The packet pointer. There is only ever one packet in use at one time, so
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//! there is no need to repeatedly allocate and delete it.
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//! there is no need to repeatedly allocate and delete it.
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RspPacket *pkt;
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RspPacket *pkt;
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//! Hash table for matchpoints
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//! Hash table for matchpoints
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MpHash *mpHash;
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MpHash *mpHash;
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//! Is the target stopped
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//! Is the target stopped
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bool targetStopped;
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bool targetStopped;
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// SystemC thread to listen for and service RSP requests
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// SystemC thread to listen for and service RSP requests
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void rspServer ();
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void rspServer();
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// Main RSP request handler
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// Main RSP request handler
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void rspClientRequest ();
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void rspClientRequest();
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// Handle the various RSP requests
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// Handle the various RSP requests
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void rspCheckForException();
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void rspCheckForException();
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void rspReportException ();
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void rspReportException();
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void rspContinue ();
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void rspContinue();
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void rspContinue (uint32_t except);
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void rspContinue (uint32_t except);
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void rspContinue (uint32_t addr,
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void rspContinue(uint32_t addr, uint32_t except);
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uint32_t except);
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void rspInterrupt ();
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void rspInterrupt ();
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void rspReadAllRegs ();
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void rspReadAllRegs();
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void rspWriteAllRegs ();
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void rspWriteAllRegs();
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void rspReadMem ();
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void rspReadMem();
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void rspWriteMem ();
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void rspWriteMem();
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void rspReadReg ();
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void rspReadReg();
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void rspWriteReg ();
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void rspWriteReg();
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void rspQuery ();
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void rspQuery();
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void rspCommand ();
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void rspCommand();
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void rspSet ();
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void rspSet();
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void rspRestart ();
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void rspRestart();
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void rspStep ();
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void rspStep();
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void rspStep (uint32_t except);
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void rspStep (uint32_t except);
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void rspStep (uint32_t addr,
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void rspStep(uint32_t addr, uint32_t except);
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uint32_t except);
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void rspVpkt ();
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void rspVpkt ();
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void rspWriteMemBin ();
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void rspWriteMemBin();
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void rspRemoveMatchpoint ();
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void rspRemoveMatchpoint();
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void rspInsertMatchpoint ();
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void rspInsertMatchpoint();
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// Convenience wrappers for getting particular registers, which are really
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// Convenience wrappers for getting particular registers, which are really
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// SPRs.
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// SPRs.
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uint32_t readNpc ();
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uint32_t readNpc();
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void writeNpc (uint32_t addr);
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void writeNpc(uint32_t addr);
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uint32_t readGpr (int regNum);
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uint32_t readGpr (int regNum);
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void writeGpr (int regNum,
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void writeGpr(int regNum, uint32_t value);
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uint32_t value);
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// Check if we got a message from the or1200 monitor module telling us
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// Check if we got a message from the or1200 monitor module telling us
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// to stall
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// to stall
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bool checkMonitorPipe ();
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bool checkMonitorPipe();
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}; // GdbServerSC ()
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}; // GdbServerSC ()
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#endif // GDB_SERVER_SC__H
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#endif // GDB_SERVER_SC__H
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