//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ORPSoC SystemC Testbench header ////
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//// ORPSoC SystemC Testbench header ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ORPSoC Testbench header file ////
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//// ORPSoC Testbench header file ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
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//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
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//// - Julius Baxter jb@orsoc.se ////
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//// - Julius Baxter jb@orsoc.se ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// SystemC declarations that should be visible anywhere. These should be
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// SystemC declarations that should be visible anywhere. These should be
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// consistent with the values used in the Verilog
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// consistent with the values used in the Verilog
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#ifndef ORPSOC_MAIN__H
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#ifndef ORPSOC_MAIN__H
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#define ORPSOC_MAIN__H
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#define ORPSOC_MAIN__H
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/* Globals used by other C modules */
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extern bool gQuiet;
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extern int gSimRunning;
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//! The Verilog timescale unit (as SystemC timescale unit)
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//! The Verilog timescale unit (as SystemC timescale unit)
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#define TIMESCALE_UNIT SC_NS
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#define TIMESCALE_UNIT SC_NS
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//! The number of cycles of reset required
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//! The number of cycles of reset required
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#define BENCH_RESET_TIME 10
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#define BENCH_RESET_TIME 10
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//! CPU clock Half period in timescale units
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//! CPU clock Half period in timescale units
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#define BENCH_CLK_HALFPERIOD 10
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#define BENCH_CLK_HALFPERIOD 10
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//! System's internal RAM size in byes - found in rtl/verilog/orpsoc_top.v, param for ram_wb module
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//! Currently is 32MB (8M words)
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#define ORPSOC_SRAM_SIZE (8388608*4)
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//! Ratio of JTAG clock period to CPU clock period
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//! Ratio of JTAG clock period to CPU clock period
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#define CLOCK_RATIO 10
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#define CLOCK_RATIO 10
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//! JTAG clock half period in timescale units
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//! JTAG clock half period in timescale units
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#define JTAG_CLK_HALFPERIOD (CLOCK_RATIO * BENCH_CLK_HALFPERIOD)
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#define JTAG_CLK_HALFPERIOD (CLOCK_RATIO * BENCH_CLK_HALFPERIOD)
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//! Start of 2MB Flash memory
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//! Start of 2MB Flash memory
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#define FLASH_START 0xf0000000
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#define FLASH_START 0xf0000000
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//! End of 2MB Flash memory
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//! End of 2MB Flash memory
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#define FLASH_END 0xf01fffff
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#define FLASH_END 0xf01fffff
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//! Default port for RSP to listen on
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//! Default port for RSP to listen on
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#define DEFAULT_RSP_PORT 50003
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#define DEFAULT_RSP_PORT 50003
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//! FIFO size for talking to the RSP connection
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//! FIFO size for talking to the RSP connection
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#define RSP_FIFO_SIZE 8
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#define RSP_FIFO_SIZE 8
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//! Maximum size of a RSP packet is used to return the value of all the
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//! Maximum size of a RSP packet is used to return the value of all the
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//! registers, each of which takes 8 chars. There are a total of 32 GPRs plus
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//! registers, each of which takes 8 chars. There are a total of 32 GPRs plus
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//! PPC, SR and NPC. Plus one byte for end of string marker.
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//! PPC, SR and NPC. Plus one byte for end of string marker.
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#define RSP_MAX_PKT_SIZE ((32 + 3) * 8 + 1)
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#define RSP_MAX_PKT_SIZE ((32 + 3) * 8 + 1)
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#endif // ORPSOC_MAIN__H
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#endif // ORPSOC_MAIN__H
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