// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// SystemC reset signal generator header
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// SystemC reset signal generator header
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// This file is part of the cycle accurate model of the OpenRISC 1000 based
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// This file is part of the cycle accurate model of the OpenRISC 1000 based
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// system-on-chip, ORPSoC, built using Verilator.
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// system-on-chip, ORPSoC, built using Verilator.
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// This program is free software: you can redistribute it and/or modify it
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// This program is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or (at your
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// the Free Software Foundation, either version 3 of the License, or (at your
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// option) any later version.
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// option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// $Id: ResetSC.h 286 2009-02-03 11:19:30Z jeremy $
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// $Id: ResetSC.h 286 2009-02-03 11:19:30Z jeremy $
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#ifndef RESET_SC__H
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#ifndef RESET_SC__H
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#define RESET_SC__H
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#define RESET_SC__H
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#include "systemc"
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#include "systemc"
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//! Provide a SystemC reset signal at startup
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//! Provide a SystemC reset signal at startup
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//! The reset signal is driven for a specified number of cycles after
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//! The reset signal is driven for a specified number of cycles after
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//! creation. For convenience synchronous versions of the reset signal are
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//! creation. For convenience synchronous versions of the reset signal are
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//! provided in both active high and active low formats.
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//! provided in both active high and active low formats.
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class ResetSC
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class ResetSC:public sc_core::sc_module {
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: public sc_core::sc_module
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{
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public:
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public:
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// Constructor
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// Constructor
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ResetSC (sc_core::sc_module_name name,
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ResetSC(sc_core::sc_module_name name, int _resetCounter = 5);
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int _resetCounter = 5);
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// Method to drive the reset
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// Method to drive the reset
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void driveReset();
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void driveReset();
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// The ports
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// The ports
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sc_core::sc_in<bool> clk;
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sc_core::sc_in < bool > clk;
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sc_core::sc_out<bool> rst; // Active high reset
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sc_core::sc_out < bool > rst; // Active high reset
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sc_core::sc_out<bool> rstn; // Active low reset
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sc_core::sc_out < bool > rstn; // Active low reset
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private:
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private:
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int resetCounter;
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int resetCounter;
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}; // ResetSC ()
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}; // ResetSC ()
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#endif // RESET_SC__H
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#endif // RESET_SC__H
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