// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Debug Unit SPR cache: definition
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// Debug Unit SPR cache: definition
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// This file is part of the GDB interface to the cycle accurate model of the
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// This file is part of the GDB interface to the cycle accurate model of the
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// This program is free software: you can redistribute it and/or modify it
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// This program is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or (at your
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// the Free Software Foundation, either version 3 of the License, or (at your
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// option) any later version.
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// option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// $Id: SprCache.h 331 2009-03-12 17:01:48Z jeremy $
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// $Id: SprCache.h 331 2009-03-12 17:01:48Z jeremy $
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#ifndef SPR_CACHE__H
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#ifndef SPR_CACHE__H
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#define SPR_CACHE__H
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#define SPR_CACHE__H
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#include <stdint.h>
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#include <stdint.h>
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Module for cacheing SPR accesses by the debug unit
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//! Module for cacheing SPR accesses by the debug unit
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//! SPR reads and writes through the Debug Unit via JTAG are time
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//! SPR reads and writes through the Debug Unit via JTAG are time
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//! consuming - of the order of 1000 CPU clock cycles. However when the
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//! consuming - of the order of 1000 CPU clock cycles. However when the
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//! processor is stalled the values cannot change, other than through the
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//! processor is stalled the values cannot change, other than through the
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//! debug unit, so it makes sense to cache values.
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//! debug unit, so it makes sense to cache values.
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//! @note It is not strictly true that SPRs do not change. If the NPC is
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//! @note It is not strictly true that SPRs do not change. If the NPC is
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//! written, it flushes the pipeline, and subsequent reads will return
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//! written, it flushes the pipeline, and subsequent reads will return
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//! zero until the processor is unstalled and the pipeline has
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//! zero until the processor is unstalled and the pipeline has
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//! refilled. However for our purposes, it is convenient to return the
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//! refilled. However for our purposes, it is convenient to return the
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//! value written into the NPC in such circumstances.
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//! value written into the NPC in such circumstances.
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//!
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//!
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//! The cache is represented as a closed hash table, which is generally
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//! The cache is represented as a closed hash table, which is generally
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//! allowed to be no more than 70% full (however NPC is always
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//! allowed to be no more than 70% full (however NPC is always
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//! cacheable). The hash function is a simple modulo function, stepping
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//! cacheable). The hash function is a simple modulo function, stepping
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//! forward to the first free slot. This works because there is no function to
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//! forward to the first free slot. This works because there is no function to
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//! delete an entry - just to clear the whole table, so holes cannot appear.
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//! delete an entry - just to clear the whole table, so holes cannot appear.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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class SprCache
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class SprCache {
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{
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public:
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public:
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// Constructor and destructor
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// Constructor and destructor
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SprCache (int _tableSize = 257);
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SprCache(int _tableSize = 257);
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~SprCache ();
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~SprCache();
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// Functions
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// Functions
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void clear ();
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void clear ();
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void write (uint16_t sprNum,
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void write(uint16_t sprNum, uint32_t value, bool force);
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uint32_t value,
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bool read(uint16_t sprNum, uint32_t & value);
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bool force);
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bool read (uint16_t sprNum,
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uint32_t &value);
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private:
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private:
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//! The size of the hash table
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//! The size of the hash table
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int tableSize;
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int tableSize;
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//! Maximum amount of cache left to use, before cacheing is rejected.
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//! Maximum amount of cache left to use, before cacheing is rejected.
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int maxToUse;
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int maxToUse;
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// The cache, keyed by sprNum. Done as two parallel vectors,
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// The cache, keyed by sprNum. Done as two parallel vectors,
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// allowing unambiguous clearing by use of memset for efficiency.
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// allowing unambiguous clearing by use of memset for efficiency.
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bool *sprIsValid;
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bool *sprIsValid;
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uint16_t *sprKeyNum;
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uint16_t *sprKeyNum;
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uint32_t *sprValue;
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uint32_t *sprValue;
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}; // SprCache ()
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}; // SprCache ()
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#endif // SPR_CACHE__H
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#endif // SPR_CACHE__H
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