// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// SystemC OpenRISC 1000 Debug Unit: implementation
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// SystemC OpenRISC 1000 Debug Unit: implementation
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Copyright (C) 2009 ORSoC
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// Copyright (C) 2009 ORSoC
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// Contributor Julius Baxter <julius@orsoc.se>
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// Contributor Julius Baxter <julius@orsoc.se>
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// This file is part of the GDB interface to the cycle accurate model of the
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// This file is part of the GDB interface to the cycle accurate model of the
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// This program is free software: you can redistribute it and/or modify it
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// This program is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or (at your
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// the Free Software Foundation, either version 3 of the License, or (at your
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// option) any later version.
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// option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// $Id$
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// $Id$
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#include <iostream>
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#include <iostream>
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#include <iomanip>
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#include <iomanip>
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#include "DebugUnitSC.h"
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#include "DebugUnitSC.h"
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#include "Utils.h"
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#include "Utils.h"
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using sc_core::sc_event;
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using sc_core::sc_event;
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using sc_core::sc_fifo;
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using sc_core::sc_fifo;
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using sc_core::sc_module_name;
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using sc_core::sc_module_name;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Constructor for the Debug Unit
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//! Constructor for the Debug Unit
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//! This module is entirely subservient to the GDB server. It has no SystemC
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//! This module is entirely subservient to the GDB server. It has no SystemC
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//! processes of its own. It provides services via calls to its API.
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//! processes of its own. It provides services via calls to its API.
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//! The current scan chain is marked as undefined, and the current JTAG scan
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//! The current scan chain is marked as undefined, and the current JTAG scan
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//! chain is maked as undefined.
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//! chain is maked as undefined.
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//! Caches for SPR and memory access are initialized.
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//! Caches for SPR and memory access are initialized.
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//! This makes use of the Embecosm cycle accurate SystemC JTAG interface.
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//! This makes use of the Embecosm cycle accurate SystemC JTAG interface.
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//! @see Embecosm Application Note 5 "Using JTAG with SystemC: Implementation
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//! @see Embecosm Application Note 5 "Using JTAG with SystemC: Implementation
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//! of a Cycle Accurate Interface"
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//! of a Cycle Accurate Interface"
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//! (http://www.embecosm.com/download/ean5.html)
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//! (http://www.embecosm.com/download/ean5.html)
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//! @param[in] name Name of this module, passed to the parent
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//! @param[in] name Name of this module, passed to the parent
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//! constructor.
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//! constructor.
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//! @param[in] _tapActionQueue Pointer to fifo of actions to be performed by
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//! @param[in] _tapActionQueue Pointer to fifo of actions to be performed by
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//! the JTAG interface
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//! the JTAG interface
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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DebugUnitSC::DebugUnitSC (sc_module_name name,
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DebugUnitSC::DebugUnitSC(sc_module_name name, sc_fifo < TapAction * >*_tapActionQueue):
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sc_fifo<TapAction *> *_tapActionQueue) :
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sc_module (name),
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sc_module (name),
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tapActionQueue (_tapActionQueue),
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tapActionQueue (_tapActionQueue),
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stallState (UNKNOWN),
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stallState(UNKNOWN), currentScanChain(OR1K_SC_UNDEF)
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currentScanChain (OR1K_SC_UNDEF)
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{
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{
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#ifdef NOCACHE
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#ifdef NOCACHE
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npcCacheIsValid = false; // Always cache NPC
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npcCacheIsValid = false; // Always cache NPC
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#else
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#else
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sprCache = new SprCache ();
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sprCache = new SprCache();
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memCache = new MemCache ();
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memCache = new MemCache();
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#endif
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#endif
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} // DebugUnitSC ()
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} // DebugUnitSC ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Destructor
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//! Destructor
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//! Free up data structures
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//! Free up data structures
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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DebugUnitSC::~DebugUnitSC ()
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DebugUnitSC::~DebugUnitSC()
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{
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{
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#ifndef NOCACHE
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#ifndef NOCACHE
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delete memCache;
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delete memCache;
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delete sprCache;
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delete sprCache;
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#endif
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#endif
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} // ~DebugUnitSC
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} // ~DebugUnitSC
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Reset the Debug Unit
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//! Reset the Debug Unit
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//! This is just a reset of the JTAG. It is quite possible to reset the debug
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//! This is just a reset of the JTAG. It is quite possible to reset the debug
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//! unit without resetting the whole target.
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//! unit without resetting the whole target.
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//! @note Must be called from a SystemC thread, because of the use of wait()
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//! @note Must be called from a SystemC thread, because of the use of wait()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void
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DebugUnitSC::resetDebugUnit ()
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DebugUnitSC::resetDebugUnit()
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{
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{
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sc_event *done = new sc_event();
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sc_event *done = new sc_event();
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TapActionReset *resetAction;
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TapActionReset *resetAction;
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// Create and queue the reset action and wait for it to complete
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// Create and queue the reset action and wait for it to complete
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resetAction = new TapActionReset (done);
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resetAction = new TapActionReset(done);
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tapActionQueue->write (resetAction);
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tapActionQueue->write(resetAction);
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wait (*done);
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wait(*done);
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delete resetAction;
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delete resetAction;
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delete done;
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delete done;
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} // resetDebugUnit ()
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} // resetDebugUnit ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Reset the processor
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//! Reset the processor
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//! Read the RISCOP register, OR in the reset bit and write it back.
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//! Read the RISCOP register, OR in the reset bit and write it back.
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//! After reset, the processor is known to be unstalled.
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//! After reset, the processor is known to be unstalled.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void DebugUnitSC::reset()
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DebugUnitSC::reset ()
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{
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{
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writeRiscop (readRiscop () | RISCOP_RESET);
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writeRiscop(readRiscop() | RISCOP_RESET);
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stallState = UNKNOWN;
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stallState = UNKNOWN;
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} // reset ()
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} // reset ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Stall the processor
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//! Stall the processor
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//! Read the RISCOP register, OR in the stall bit and write it back.
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//! Read the RISCOP register, OR in the stall bit and write it back.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void DebugUnitSC::stall()
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DebugUnitSC::stall ()
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{
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{
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writeRiscop (/*readRiscop () |*/ RISCOP_STALL);
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writeRiscop( /*readRiscop () | */ RISCOP_STALL);
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stallState = STALLED;
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stallState = STALLED;
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} // stall ()
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} // stall ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Unstall the processor
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//! Unstall the processor
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//! Read the RISCOP register, AND out the stall bit and write it back. After
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//! Read the RISCOP register, AND out the stall bit and write it back. After
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//! this the NPC cache will be invalid.
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//! this the NPC cache will be invalid.
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//! @note Don't be tempted to read back for confirmation. Single stepping
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//! @note Don't be tempted to read back for confirmation. Single stepping
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//! will already have stalled the processor again!
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//! will already have stalled the processor again!
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void DebugUnitSC::unstall()
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DebugUnitSC::unstall ()
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{
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{
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writeRiscop (/*readRiscop () & ~RISCOP_STALL*/ 0);
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writeRiscop( /*readRiscop () & ~RISCOP_STALL */ 0);
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stallState = UNKNOWN;
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stallState = UNKNOWN;
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#ifdef NOCACHE
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#ifdef NOCACHE
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npcCacheIsValid = false; // Always cache NPC
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npcCacheIsValid = false; // Always cache NPC
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#else
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#else
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// Clear the caches
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// Clear the caches
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sprCache->clear ();
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sprCache->clear();
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memCache->clear ();
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memCache->clear();
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#endif
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#endif
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} // unstall ()
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} // unstall ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Report if the processor is stalled.
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//! Report if the processor is stalled.
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//! A stalled processor cannot spontaneously "unstall", so if the stallState
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//! A stalled processor cannot spontaneously "unstall", so if the stallState
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//! flag is STALLED, that value is returned. Otherwise the target is
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//! flag is STALLED, that value is returned. Otherwise the target is
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//! interrogated to determine the status.
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//! interrogated to determine the status.
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//! @return TRUE if the processor is known to be stalled
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//! @return TRUE if the processor is known to be stalled
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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bool
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bool DebugUnitSC::isStalled()
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DebugUnitSC::isStalled ()
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{
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if (STALLED == stallState)
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{
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{
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if (STALLED == stallState) {
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return true;
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return true;
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}
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}
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uint32_t riscop = readRiscop ();
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uint32_t riscop = readRiscop();
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/* For some reason the reset bit is skipped over somewhere, so we should
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/* For some reason the reset bit is skipped over somewhere, so we should
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just get riscop = 1 if it's stalled */
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just get riscop = 1 if it's stalled */
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//stallState = (RISCOP_STALL == (riscop & RISCOP_STALL)) ? STALLED : UNKNOWN;
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//stallState = (RISCOP_STALL == (riscop & RISCOP_STALL)) ? STALLED : UNKNOWN;
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stallState = riscop ? STALLED : UNKNOWN;
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stallState = riscop ? STALLED : UNKNOWN;
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return STALLED == stallState;
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return STALLED == stallState;
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} // isStalled ()
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} // isStalled ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Read the value of an OpenRISC 1000 Special Purpose Register
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//! Read the value of an OpenRISC 1000 Special Purpose Register
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//! First see if we have the value in the cache, and if so return
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//! First see if we have the value in the cache, and if so return
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//! it. Otherwise, select the RISC_DEBUG scan chain and read from JTAG,
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//! it. Otherwise, select the RISC_DEBUG scan chain and read from JTAG,
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//! storing the result in the cache.
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//! storing the result in the cache.
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//! @param[in] sprNum The SPR to read
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//! @param[in] sprNum The SPR to read
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//! @return The value of the SPR
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//! @return The value of the SPR
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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uint32_t
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uint32_t DebugUnitSC::readSpr(uint16_t sprNum)
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DebugUnitSC::readSpr (uint16_t sprNum)
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{
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{
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uint32_t cachedValue;
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uint32_t cachedValue;
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#ifdef NOCACHE
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#ifdef NOCACHE
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// Always check NPC cache
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// Always check NPC cache
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if ((STALLED == stallState) && (sprNum == SPR_NPC) && npcCacheIsValid)
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if ((STALLED == stallState) && (sprNum == SPR_NPC) && npcCacheIsValid) {
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{
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return npcCachedValue;
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return npcCachedValue;
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}
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}
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#else
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#else
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// Use any cached value if we are stalled.
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// Use any cached value if we are stalled.
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if ((STALLED == stallState) && sprCache->read (sprNum, cachedValue))
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if ((STALLED == stallState) && sprCache->read(sprNum, cachedValue)) {
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{
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return cachedValue; // Already there, no more to do
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return cachedValue; // Already there, no more to do
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}
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}
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#endif
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#endif
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// Read the value
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// Read the value
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selectDebugModule (OR1K_SC_CPU0);
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selectDebugModule(OR1K_SC_CPU0);
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cachedValue = readJtagReg (sprNum);
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cachedValue = readJtagReg(sprNum);
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#ifdef NOCACHE
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#ifdef NOCACHE
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// Always update the NPC cache
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// Always update the NPC cache
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if ((STALLED == stallState) && (sprNum == SPR_NPC))
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if ((STALLED == stallState) && (sprNum == SPR_NPC)) {
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{
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npcCachedValue = cachedValue;
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npcCachedValue = cachedValue;
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npcCacheIsValid = true;
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npcCacheIsValid = true;
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}
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}
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#else
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#else
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// Update the cache if we are stalled
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// Update the cache if we are stalled
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if (STALLED == stallState)
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if (STALLED == stallState) {
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{
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sprCache->write (sprNum, cachedValue, sprNum == SPR_NPC);
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sprCache->write (sprNum, cachedValue, sprNum == SPR_NPC);
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}
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}
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#endif
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#endif
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return cachedValue;
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return cachedValue;
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} // readSpr ()
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} // readSpr ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Write the value of an OpenRISC 1000 Special Purpose Register
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//! Write the value of an OpenRISC 1000 Special Purpose Register
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//! First look to see if we are stalled and the value is cached. If the value
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//! First look to see if we are stalled and the value is cached. If the value
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//! has not changed, then we need to no more. Otherwise cache the value prior
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//! has not changed, then we need to no more. Otherwise cache the value prior
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//! to writing it.
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//! to writing it.
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//! Select the RISC_DEBUG scan chain and write to JTAG
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//! Select the RISC_DEBUG scan chain and write to JTAG
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//! @param[in] sprNum The SPR to write
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//! @param[in] sprNum The SPR to write
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//! @param[in] value The value to write
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//! @param[in] value The value to write
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void DebugUnitSC::writeSpr(uint16_t sprNum, uint32_t value)
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DebugUnitSC::writeSpr (uint16_t sprNum,
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uint32_t value)
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{
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{
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#ifdef NOCACHE
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#ifdef NOCACHE
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// Always cache the NPC
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// Always cache the NPC
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if ((STALLED == stallState) && (SPR_NPC == sprNum))
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if ((STALLED == stallState) && (SPR_NPC == sprNum)) {
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{
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// Have we already cached this NPC value?
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// Have we already cached this NPC value?
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if (npcCacheIsValid && (value == npcCachedValue))
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if (npcCacheIsValid && (value == npcCachedValue)) {
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{
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return;
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return;
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}
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} else {
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else
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{
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npcCachedValue = value;
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npcCachedValue = value;
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npcCacheIsValid = true;
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npcCacheIsValid = true;
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}
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}
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}
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}
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#else
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#else
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if (STALLED == stallState)
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if (STALLED == stallState) {
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{
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// Have we already cached this value?
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// Have we already cached this value?
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uint32_t cachedValue;
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uint32_t cachedValue;
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if (sprCache->read (sprNum, cachedValue) &&
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if (sprCache->read (sprNum, cachedValue) &&
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(value == cachedValue))
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(value == cachedValue)) {
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{
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return; // Already there, no more to do
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return; // Already there, no more to do
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}
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} else {
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else
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{
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sprCache->write (sprNum, value, sprNum == SPR_NPC);
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sprCache->write (sprNum, value, sprNum == SPR_NPC);
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}
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}
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}
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}
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#endif
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#endif
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// Write the SPR
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// Write the SPR
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selectDebugModule (OR1K_SC_CPU0);
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selectDebugModule(OR1K_SC_CPU0);
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writeJtagReg (sprNum, value);
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writeJtagReg(sprNum, value);
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} // writeSpr ()
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} // writeSpr ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! AND the contents of an SPR with a value
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//! AND the contents of an SPR with a value
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//! A convenience combination of read and write
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//! A convenience combination of read and write
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//! @param[in] sprNum The SPR to write
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//! @param[in] sprNum The SPR to write
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//! @param[in] value The value to AND into the register
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//! @param[in] value The value to AND into the register
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void DebugUnitSC::andSpr(uint16_t sprNum, uint32_t value)
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DebugUnitSC::andSpr (uint16_t sprNum,
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uint32_t value)
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{
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{
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writeSpr (sprNum, readSpr (sprNum) & value);
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writeSpr(sprNum, readSpr(sprNum) & value);
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} // andSpr ()
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} // andSpr ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! OR the contents of an SPR with a value
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//! OR the contents of an SPR with a value
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//! A convenience combination of read and write
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//! A convenience combination of read and write
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//! @param[in] sprNum The SPR to write
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//! @param[in] sprNum The SPR to write
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//! @param[in] value The value to OR into the register
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//! @param[in] value The value to OR into the register
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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void
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void DebugUnitSC::orSpr(uint16_t sprNum, uint32_t value)
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DebugUnitSC::orSpr (uint16_t sprNum,
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uint32_t value)
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{
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{
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writeSpr (sprNum, readSpr (sprNum) | value);
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writeSpr(sprNum, readSpr(sprNum) | value);
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} // orSpr ()
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} // orSpr ()
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//! Read a 32-bit word from the OpenRISC 1000 memory
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//! Read a 32-bit word from the OpenRISC 1000 memory
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//! Select the WISHBONE scan chain, then write the register. The data is in
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//! Select the WISHBONE scan chain, then write the register. The data is in
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//! model endianness and passed on without modification.
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//! model endianness and passed on without modification.
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//! @todo Provide code to check if the read was from a valid address.
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//! @todo Provide code to check if the read was from a valid address.
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//! @param[in] addr The address to read from
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//! @param[in] addr The address to read from
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//! @return The 32-bit value read
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//! @return The 32-bit value read
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//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
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uint32_t
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uint32_t DebugUnitSC::readMem32(uint32_t addr)
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DebugUnitSC::readMem32 (uint32_t addr)
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|
{
|
{
|
uint32_t cachedValue;
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uint32_t cachedValue;
|
|
|
#ifndef NOCACHE
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#ifndef NOCACHE
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// Use any cached value if we are stalled.
|
// Use any cached value if we are stalled.
|
if ((STALLED == stallState) && memCache->read (addr, cachedValue))
|
if ((STALLED == stallState) && memCache->read(addr, cachedValue)) {
|
{
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return cachedValue; // Already there, no more to do
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return cachedValue; // Already there, no more to do
|
}
|
}
|
#endif
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#endif
|
|
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// Read the value
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// Read the value
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selectDebugModule (OR1K_SC_WISHBONE);
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selectDebugModule(OR1K_SC_WISHBONE);
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cachedValue = readJtagReg (addr);
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cachedValue = readJtagReg(addr);
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|
|
#ifndef NOCACHE
|
#ifndef NOCACHE
|
// Update the cache if we are stalled
|
// Update the cache if we are stalled
|
if (STALLED == stallState)
|
if (STALLED == stallState) {
|
{
|
|
memCache->write (addr, cachedValue);
|
memCache->write (addr, cachedValue);
|
}
|
}
|
#endif
|
#endif
|
|
|
return cachedValue;
|
return cachedValue;
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|
|
} // readMem32 ()
|
} // readMem32 ()
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|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Write a 32-bit word to the OpenRISC 1000 memory
|
//! Write a 32-bit word to the OpenRISC 1000 memory
|
|
|
//! Select the WISHBONE scan chain, then write the register. The data is in
|
//! Select the WISHBONE scan chain, then write the register. The data is in
|
//! model endianness and passed on without modification.
|
//! model endianness and passed on without modification.
|
|
|
//! @todo Provide code to check if the write was to a valid address.
|
//! @todo Provide code to check if the write was to a valid address.
|
|
|
//! @param[in] addr The address to write to
|
//! @param[in] addr The address to write to
|
//! @param[in] value The 32-bit value to write
|
//! @param[in] value The 32-bit value to write
|
|
|
//! @return True if the write was successful. For now all writes are
|
//! @return True if the write was successful. For now all writes are
|
// successful.
|
// successful.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
bool
|
bool DebugUnitSC::writeMem32(uint32_t addr, uint32_t value)
|
DebugUnitSC::writeMem32 (uint32_t addr,
|
|
uint32_t value)
|
|
{
|
{
|
#ifndef NOCACHE
|
#ifndef NOCACHE
|
if (STALLED == stallState)
|
if (STALLED == stallState) {
|
{
|
|
// Have we already cached this value?
|
// Have we already cached this value?
|
uint32_t cachedValue;
|
uint32_t cachedValue;
|
if (memCache->read (addr, cachedValue) &&
|
if (memCache->read(addr, cachedValue) && (value == cachedValue)) {
|
(value == cachedValue))
|
|
{
|
|
return true; // Already there, no more to do
|
return true; // Already there, no more to do
|
}
|
} else {
|
else
|
|
{
|
|
memCache->write (addr, value); // Write for the future
|
memCache->write (addr, value); // Write for the future
|
}
|
}
|
}
|
}
|
#endif
|
#endif
|
|
|
// Write the memory
|
// Write the memory
|
selectDebugModule (OR1K_SC_WISHBONE);
|
selectDebugModule(OR1K_SC_WISHBONE);
|
writeJtagReg (addr, value);
|
writeJtagReg(addr, value);
|
|
|
return true;
|
return true;
|
|
|
} // writeMem32 ()
|
} // writeMem32 ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Read a byte from the OpenRISC 1000 main memory
|
//! Read a byte from the OpenRISC 1000 main memory
|
|
|
//! All we can get are 32-bits words, so we have to unpick the value.
|
//! All we can get are 32-bits words, so we have to unpick the value.
|
|
|
//! The underlying 32-bit routines take target endian arguments and return
|
//! The underlying 32-bit routines take target endian arguments and return
|
//! target endian results. We need to convert to host endianness to access the
|
//! target endian results. We need to convert to host endianness to access the
|
//! relevant byte.
|
//! relevant byte.
|
|
|
//! @todo Provide code to check if the read was from a valid address.
|
//! @todo Provide code to check if the read was from a valid address.
|
|
|
//! @note Read bytes from memory mapped devices at your peril!
|
//! @note Read bytes from memory mapped devices at your peril!
|
|
|
//! @param[in] addr The address to read from
|
//! @param[in] addr The address to read from
|
//! @return The byte read
|
//! @return The byte read
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
uint8_t
|
uint8_t DebugUnitSC::readMem8(uint32_t addr)
|
DebugUnitSC::readMem8 (uint32_t addr)
|
|
{
|
{
|
uint32_t word = Utils::ttohl (readMem32 (addr & 0xfffffffc));
|
uint32_t word = Utils::ttohl(readMem32(addr & 0xfffffffc));
|
uint8_t *bytes = (uint8_t *)(&word);
|
uint8_t *bytes = (uint8_t *) (&word);
|
int offset = addr & 0x3;
|
int offset = addr & 0x3;
|
|
|
return bytes[offset];
|
return bytes[offset];
|
|
|
} // readMem8 ()
|
} // readMem8 ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Write a byte to the OpenRISC 1000 main memory
|
//! Write a byte to the OpenRISC 1000 main memory
|
|
|
//! All we can get are 32-bits words, so we have to read the current value and
|
//! All we can get are 32-bits words, so we have to read the current value and
|
//! construct the new value to write back.
|
//! construct the new value to write back.
|
|
|
//! The underlying 32-bit routines take target endian arguments and return
|
//! The underlying 32-bit routines take target endian arguments and return
|
//! target endian results. We need to convert to host endianness to alter the
|
//! target endian results. We need to convert to host endianness to alter the
|
//! relevant byte.
|
//! relevant byte.
|
|
|
//! @note Write bytes to memory mapped devices at your peril!
|
//! @note Write bytes to memory mapped devices at your peril!
|
|
|
//! @todo Provide code to check if the write was to a valid address.
|
//! @todo Provide code to check if the write was to a valid address.
|
|
|
//! @param[in] addr The address to write to
|
//! @param[in] addr The address to write to
|
//! @param[in] value The byte to write
|
//! @param[in] value The byte to write
|
|
|
//! @return True if the write was successful. For now all writes are
|
//! @return True if the write was successful. For now all writes are
|
// successful.
|
// successful.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
bool
|
bool DebugUnitSC::writeMem8(uint32_t addr, uint8_t value)
|
DebugUnitSC::writeMem8 (uint32_t addr,
|
|
uint8_t value)
|
|
{
|
{
|
uint32_t currWord = Utils::ttohl (readMem32 (addr & 0xfffffffc));
|
uint32_t currWord = Utils::ttohl(readMem32(addr & 0xfffffffc));
|
uint8_t *currBytes = (uint8_t *)(&currWord);
|
uint8_t *currBytes = (uint8_t *) (&currWord);
|
int offset = addr & 0x3;
|
int offset = addr & 0x3;
|
|
|
currBytes[offset] = value;
|
currBytes[offset] = value;
|
|
|
return writeMem32 (addr & 0xfffffffc, Utils::htotl (currWord));
|
return writeMem32(addr & 0xfffffffc, Utils::htotl(currWord));
|
|
|
} // writeMem8 ()
|
} // writeMem8 ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Get the debug interface CPU0 control register value
|
//! Get the debug interface CPU0 control register value
|
|
|
//! @return The value in the RISCOP register
|
//! @return The value in the RISCOP register
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
uint32_t
|
uint32_t DebugUnitSC::readRiscop()
|
DebugUnitSC::readRiscop ()
|
|
{
|
{
|
selectDebugModule (OR1K_SC_CPU0);
|
selectDebugModule(OR1K_SC_CPU0);
|
|
|
int drLen; // Size of the data register
|
int drLen; // Size of the data register
|
|
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
|
|
drLen = 1+4+32+52+4+32;
|
drLen = 1 + 4 + 32 + 52 + 4 + 32;
|
|
|
// Initialize the register fields
|
// Initialize the register fields
|
uint64_t *dRegIn = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegIn = new uint64_t[(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t[(drLen + 63) / 64];
|
|
|
// Write the READ command
|
// Write the READ command
|
clearBits (dRegIn, drLen);
|
clearBits(dRegIn, drLen);
|
|
|
packBits (dRegIn, 0, 1, 0);
|
packBits(dRegIn, 0, 1, 0);
|
packBits (dRegIn, 0+1, 4, BITREV(0x3,4)); // We're reading CPU0 control reg
|
packBits(dRegIn, 0 + 1, 4, BITREV(0x3, 4)); // We're reading CPU0 control reg
|
uint32_t crc32_send = crc32 (dRegIn, 0+1+4, 0);
|
uint32_t crc32_send = crc32(dRegIn, 0 + 1 + 4, 0);
|
packBits (dRegIn, 0+1+4, 32, BITREV(crc32_send,32));
|
packBits(dRegIn, 0 + 1 + 4, 32, BITREV(crc32_send, 32));
|
|
|
// Allocate a SystemC completion event
|
// Allocate a SystemC completion event
|
sc_event *done = new sc_event();
|
sc_event *done = new sc_event();
|
|
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan =
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, drLen);
|
new TapActionDRScan(done, dRegIn, drLen);
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = unpackBits (dRegOut,1+4+32+52,4);
|
status_ret = unpackBits(dRegOut, 1 + 4 + 32 + 52, 4);
|
calc_recv_crc = crc32(dRegOut,52+4,1+4+32);
|
calc_recv_crc = crc32(dRegOut,52+4,1+4+32);
|
recv_crc = BITREV(unpackBits (dRegOut,1+4+32+52+4,32),32);
|
recv_crc =
|
|
BITREV(unpackBits(dRegOut, 1 + 4 + 32 + 52 + 4, 32), 32);
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
// All done
|
// All done
|
uint32_t res = BITREV(unpackBits (dRegOut, (1+4+32),2),2);
|
uint32_t res = BITREV(unpackBits(dRegOut, (1 + 4 + 32), 2), 2);
|
|
|
delete [] dRegIn;
|
delete[]dRegIn;
|
delete [] dRegOut;
|
delete[]dRegOut;
|
delete done;
|
delete done;
|
return res;
|
return res;
|
} // readRiscop ()
|
} // readRiscop ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Set the RISCOP control register
|
//! Set the RISCOP control register
|
|
|
//! Convenience function. Select the REGISTER scan chain, write the new value.
|
//! Convenience function. Select the REGISTER scan chain, write the new value.
|
|
|
//! @param[in] value The value to write into the RISCOP register
|
//! @param[in] value The value to write into the RISCOP register
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
void
|
void DebugUnitSC::writeRiscop(uint32_t value)
|
DebugUnitSC::writeRiscop (uint32_t value)
|
|
{
|
{
|
selectDebugModule (OR1K_SC_CPU0);
|
selectDebugModule(OR1K_SC_CPU0);
|
|
|
int drLen; // Size of the data register
|
int drLen; // Size of the data register
|
|
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
|
|
drLen = 1+4+32+52+4+32;
|
drLen = 1 + 4 + 32 + 52 + 4 + 32;
|
|
|
// Initialize the register fields
|
// Initialize the register fields
|
uint64_t *dRegIn = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegIn = new uint64_t[(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t[(drLen + 63) / 64];
|
|
|
// Write the READ command
|
// Write the READ command
|
clearBits (dRegIn, drLen);
|
clearBits(dRegIn, drLen);
|
|
|
packBits (dRegIn, 0, 1, 0);
|
packBits(dRegIn, 0, 1, 0);
|
packBits (dRegIn, 0+1, 4, BITREV(0x4,4)); // We're writing CPU0 control reg
|
packBits(dRegIn, 0 + 1, 4, BITREV(0x4, 4)); // We're writing CPU0 control reg
|
packBits (dRegIn, 5, 1, value&RISCOP_RESET); // First bit is reset
|
packBits(dRegIn, 5, 1, value & RISCOP_RESET); // First bit is reset
|
packBits (dRegIn, 6, 1, (value&RISCOP_STALL)>>1); // Next bit is stall
|
packBits(dRegIn, 6, 1, (value & RISCOP_STALL) >> 1); // Next bit is stall
|
/* Next 50 bits should be zero */
|
/* Next 50 bits should be zero */
|
uint32_t crc32_send = crc32 (dRegIn, 1+4+52, 0);
|
uint32_t crc32_send = crc32(dRegIn, 1 + 4 + 52, 0);
|
packBits (dRegIn, 1+4+52, 32, BITREV(crc32_send,32));
|
packBits(dRegIn, 1 + 4 + 52, 32, BITREV(crc32_send, 32));
|
|
|
// Allocate a SystemC completion event
|
// Allocate a SystemC completion event
|
sc_event *done = new sc_event();
|
sc_event *done = new sc_event();
|
|
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan =
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, drLen);
|
new TapActionDRScan(done, dRegIn, drLen);
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = unpackBits (dRegOut,1+4+32+52,4);
|
status_ret = unpackBits(dRegOut, 1 + 4 + 32 + 52, 4);
|
calc_recv_crc = crc32(dRegOut,4,1+4+52+32);
|
calc_recv_crc = crc32(dRegOut,4,1+4+52+32);
|
recv_crc = BITREV(unpackBits (dRegOut,1+4+52+32+4,32),32);
|
recv_crc =
|
|
BITREV(unpackBits(dRegOut, 1 + 4 + 52 + 32 + 4, 32), 32);
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
delete [] dRegIn;
|
delete[]dRegIn;
|
delete [] dRegOut;
|
delete[]dRegOut;
|
delete done;
|
delete done;
|
|
|
} // writeRiscop ()
|
} // writeRiscop ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Select a module attached to the debug module
|
//! Select a module attached to the debug module
|
|
|
//! @note Must be called from a SystemC thread, because of the use of wait()
|
//! @note Must be called from a SystemC thread, because of the use of wait()
|
|
|
//! @param[in] chain The desired module
|
//! @param[in] chain The desired module
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
void
|
void DebugUnitSC::selectDebugModule(int module)
|
DebugUnitSC::selectDebugModule (int module)
|
|
{
|
{
|
|
|
if (module == currentScanChain)
|
if (module == currentScanChain) {
|
{
|
|
return;
|
return;
|
}
|
} else {
|
else
|
|
{
|
|
currentScanChain = module;
|
currentScanChain = module;
|
}
|
}
|
|
|
sc_event *done = new sc_event();
|
sc_event *done = new sc_event();
|
TapActionIRScan *iRScan;
|
TapActionIRScan *iRScan;
|
TapActionDRScan *dRScan;
|
TapActionDRScan *dRScan;
|
|
|
// Create and queue the IR-Scan action for DEBUG (no CRC)
|
// Create and queue the IR-Scan action for DEBUG (no CRC)
|
iRScan = new TapActionIRScan (done, DEBUG_IR, JTAG_IR_LEN);
|
iRScan = new TapActionIRScan(done, DEBUG_IR, JTAG_IR_LEN);
|
tapActionQueue->write (iRScan);
|
tapActionQueue->write(iRScan);
|
wait (*done);
|
wait(*done);
|
|
|
delete iRScan;
|
delete iRScan;
|
|
|
// Initialize the register fields
|
// Initialize the register fields
|
uint64_t *dRegIn = new uint64_t [(DUSEL_DR_LEN + 63) / 64];
|
uint64_t *dRegIn = new uint64_t[(DUSEL_DR_LEN + 63) / 64];
|
uint64_t *dRegOut = new uint64_t [(DUSEL_DR_LEN + 63) / 64];
|
uint64_t *dRegOut = new uint64_t[(DUSEL_DR_LEN + 63) / 64];
|
|
|
clearBits (dRegIn, DUSEL_DR_LEN);
|
clearBits(dRegIn, DUSEL_DR_LEN);
|
packBits (dRegIn, DUSEL_SEL_OFF, DUSEL_SEL_LEN, 0x1);
|
packBits (dRegIn, DUSEL_SEL_OFF, DUSEL_SEL_LEN, 0x1);
|
packBits (dRegIn, DUSEL_OPCODE_OFF, DUSEL_OPCODE_LEN, bit_reverse_data(module,4));
|
packBits(dRegIn, DUSEL_OPCODE_OFF, DUSEL_OPCODE_LEN,
|
|
bit_reverse_data(module, 4));
|
uint32_t crc32_send = crc32 (dRegIn, DUSEL_CRC_OFF, 0);
|
uint32_t crc32_send = crc32 (dRegIn, DUSEL_CRC_OFF, 0);
|
packBits (dRegIn, DUSEL_CRC_OFF, DUSEL_CRC_LEN, bit_reverse_data(crc32_send,32) );
|
packBits(dRegIn, DUSEL_CRC_OFF, DUSEL_CRC_LEN,
|
|
bit_reverse_data(crc32_send, 32));
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan =
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, DUSEL_DR_LEN);
|
new TapActionDRScan(done, dRegIn, DUSEL_DR_LEN);
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = unpackBits (dRegOut, DUSEL_RESP_STATUS_OFF, DUSEL_RESP_STATUS_LEN);
|
status_ret =
|
calc_recv_crc = crc32(dRegOut, DUSEL_RESP_STATUS_LEN, DUSEL_RESP_STATUS_OFF);
|
unpackBits(dRegOut, DUSEL_RESP_STATUS_OFF,
|
recv_crc = bit_reverse_data(unpackBits (dRegOut, DUSEL_RESP_CRC_OFF, DUSEL_RESP_CRC_LEN),32);
|
DUSEL_RESP_STATUS_LEN);
|
|
calc_recv_crc =
|
|
crc32(dRegOut, DUSEL_RESP_STATUS_LEN,
|
|
DUSEL_RESP_STATUS_OFF);
|
|
recv_crc =
|
|
bit_reverse_data(unpackBits
|
|
(dRegOut, DUSEL_RESP_CRC_OFF,
|
|
DUSEL_RESP_CRC_LEN), 32);
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
delete [] dRegIn;
|
delete[]dRegIn;
|
delete [] dRegOut;
|
delete[]dRegOut;
|
delete done;
|
delete done;
|
|
|
} // selectDebugModule()
|
} // selectDebugModule()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Read a 32-bit value via the debug interface
|
//! Read a 32-bit value via the debug interface
|
|
|
//! @note Must be called from a SystemC thread, because of the use of wait()
|
//! @note Must be called from a SystemC thread, because of the use of wait()
|
|
|
//! @param[in] addr The address of the register
|
//! @param[in] addr The address of the register
|
|
|
//! @return The register value read
|
//! @return The register value read
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
uint32_t
|
uint32_t DebugUnitSC::readJtagReg(uint32_t addr)
|
DebugUnitSC::readJtagReg (uint32_t addr)
|
|
{
|
{
|
int drLen; // Size of the data register
|
int drLen; // Size of the data register
|
|
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
|
|
drLen = 125; // Size of write command command (bigger than data read)
|
drLen = 125; // Size of write command command (bigger than data read)
|
|
|
// Initialize the register fields
|
// Initialize the register fields
|
uint64_t *dRegIn = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegIn = new uint64_t[(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t[(drLen + 63) / 64];
|
|
|
// Write the READ command
|
// Write the READ command
|
clearBits (dRegIn, drLen);
|
clearBits(dRegIn, drLen);
|
|
|
packBits (dRegIn, 0, 1, 0);
|
packBits(dRegIn, 0, 1, 0);
|
packBits (dRegIn, 0+1, 4, BITREV(0x2,4)); // We're writing a command
|
packBits(dRegIn, 0 + 1, 4, BITREV(0x2, 4)); // We're writing a command
|
packBits (dRegIn, 1+4, 4, BITREV(0x6,4)); // Access type, 0x6 = 32-bit READ
|
packBits(dRegIn, 1 + 4, 4, BITREV(0x6, 4)); // Access type, 0x6 = 32-bit READ
|
packBits (dRegIn, 1+4+4, 32, BITREV(addr,32)); // Address
|
packBits(dRegIn, 1 + 4 + 4, 32, BITREV(addr, 32)); // Address
|
packBits (dRegIn, 1+4+4+32, 16, BITREV(0x3,16)); // Length (always 32-bit,n=(32/8)-1=3)
|
packBits(dRegIn, 1 + 4 + 4 + 32, 16, BITREV(0x3, 16)); // Length (always 32-bit,n=(32/8)-1=3)
|
uint32_t crc32_send = crc32 (dRegIn, 1+4+4+32+16, 0);
|
uint32_t crc32_send = crc32(dRegIn, 1 + 4 + 4 + 32 + 16, 0);
|
packBits (dRegIn, 1+4+4+32+16, 32, BITREV(crc32_send,32));
|
packBits(dRegIn, 1 + 4 + 4 + 32 + 16, 32, BITREV(crc32_send, 32));
|
|
|
// Allocate a SystemC completion event
|
// Allocate a SystemC completion event
|
sc_event *done = new sc_event();
|
sc_event *done = new sc_event();
|
|
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan =
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, 125);
|
new TapActionDRScan(done, dRegIn, 125);
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = unpackBits (dRegOut,1+4+4+32+16+32,4);
|
status_ret = unpackBits(dRegOut, 1 + 4 + 4 + 32 + 16 + 32, 4);
|
calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);
|
calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);
|
recv_crc = BITREV(unpackBits (dRegOut,1+4+4+32+16+32+4,32),32);
|
recv_crc =
|
|
BITREV(unpackBits
|
|
(dRegOut, 1 + 4 + 4 + 32 + 16 + 32 + 4, 32), 32);
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
clearBits (dRegIn, drLen);
|
clearBits(dRegIn, drLen);
|
packBits (dRegIn, 0, 1, 0);
|
packBits(dRegIn, 0, 1, 0);
|
packBits (dRegIn, 0+1, 4, 0x0); // We're GO'ing command
|
packBits(dRegIn, 0 + 1, 4, 0x0); // We're GO'ing command
|
crc32_send = crc32 (dRegIn,1+4,0);
|
crc32_send = crc32(dRegIn, 1 + 4, 0);
|
packBits (dRegIn, 1+4, 32, BITREV(crc32_send,32)); // CRC
|
packBits(dRegIn, 1 + 4, 32, BITREV(crc32_send, 32)); // CRC
|
|
|
uint32_t result;
|
uint32_t result;
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan = new TapActionDRScan(done, dRegIn,
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, (1+4+32+36+((3+1)*8)));
|
(1 + 4 + 32 + 36 +
|
|
((3 + 1) * 8)));
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = BITREV(unpackBits (dRegOut,1+4+32+((3+1)*8),4),4);
|
status_ret =
|
if (status_ret)
|
BITREV(unpackBits(dRegOut, 1 + 4 + 32 + ((3 + 1) * 8), 4),
|
{
|
4);
|
printf("readJtagReg(): Addr: 0x%.8x Status err: 0x%x\n",addr,status_ret);
|
if (status_ret) {
|
|
printf("readJtagReg(): Addr: 0x%.8x Status err: 0x%x\n",
|
|
addr, status_ret);
|
result = 0;
|
result = 0;
|
break;
|
break;
|
}
|
}
|
calc_recv_crc = crc32(dRegOut,((3+1)*8)+4,1+4+32);
|
calc_recv_crc = crc32(dRegOut,((3+1)*8)+4,1+4+32);
|
recv_crc = BITREV(unpackBits (dRegOut,1+4+32+((3+1)*8)+4,32),32);
|
recv_crc =
|
result = BITREV(unpackBits (dRegOut, (1+4+32), ((3+1)*8)),32);
|
BITREV(unpackBits
|
|
(dRegOut, 1 + 4 + 32 + ((3 + 1) * 8) + 4, 32), 32);
|
|
result =
|
|
BITREV(unpackBits(dRegOut, (1 + 4 + 32), ((3 + 1) * 8)),
|
|
32);
|
|
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
// All done
|
// All done
|
|
|
delete [] dRegIn;
|
delete[]dRegIn;
|
delete [] dRegOut;
|
delete[]dRegOut;
|
delete done;
|
delete done;
|
return result;
|
return result;
|
|
|
} // readJtagReg ()
|
} // readJtagReg ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Write a 32-bit value via the debug interface
|
//! Write a 32-bit value via the debug interface
|
|
|
//! @note Must be called from a SystemC thread, because of the use of wait()
|
//! @note Must be called from a SystemC thread, because of the use of wait()
|
|
|
//! @param[in] addr The address of the register
|
//! @param[in] addr The address of the register
|
//! @param[in] data The register data to write
|
//! @param[in] data The register data to write
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
void
|
void DebugUnitSC::writeJtagReg(uint32_t addr, uint32_t data)
|
DebugUnitSC::writeJtagReg (uint32_t addr,
|
|
uint32_t data)
|
|
{
|
{
|
int drLen; // Size of the data register
|
int drLen; // Size of the data register
|
|
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
uint32_t calc_recv_crc = 0, recv_crc, status_ret;
|
|
|
drLen = 125; // Size of write command command (bigger than data read)
|
drLen = 125; // Size of write command command (bigger than data read)
|
|
|
// Initialize the register fields
|
// Initialize the register fields
|
uint64_t *dRegIn = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegIn = new uint64_t[(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
|
uint64_t *dRegOut = new uint64_t[(drLen + 63) / 64];
|
|
|
// Write the READ command
|
// Write the READ command
|
clearBits (dRegIn, drLen);
|
clearBits(dRegIn, drLen);
|
|
|
packBits (dRegIn, 0, 1, 0);
|
packBits(dRegIn, 0, 1, 0);
|
packBits (dRegIn, 0+1, 4, BITREV(0x2,4)); // We're writing a command
|
packBits(dRegIn, 0 + 1, 4, BITREV(0x2, 4)); // We're writing a command
|
packBits (dRegIn, 1+4, 4, BITREV(0x2,4)); // Access type, 0x2 = 32-bit WRITE
|
packBits(dRegIn, 1 + 4, 4, BITREV(0x2, 4)); // Access type, 0x2 = 32-bit WRITE
|
packBits (dRegIn, 1+4+4, 32, BITREV(addr,32)); // Address
|
packBits(dRegIn, 1 + 4 + 4, 32, BITREV(addr, 32)); // Address
|
packBits (dRegIn, 1+4+4+32, 16, BITREV(0x3,16)); // Length (always 32-bit,n=(32/8)-1=3)
|
packBits(dRegIn, 1 + 4 + 4 + 32, 16, BITREV(0x3, 16)); // Length (always 32-bit,n=(32/8)-1=3)
|
uint32_t crc32_send = crc32 (dRegIn, 1+4+4+32+16, 0);
|
uint32_t crc32_send = crc32(dRegIn, 1 + 4 + 4 + 32 + 16, 0);
|
packBits (dRegIn, 1+4+4+32+16, 32, BITREV(crc32_send,32));
|
packBits(dRegIn, 1 + 4 + 4 + 32 + 16, 32, BITREV(crc32_send, 32));
|
|
|
// Allocate a SystemC completion event
|
// Allocate a SystemC completion event
|
sc_event *done = new sc_event();
|
sc_event *done = new sc_event();
|
|
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan =
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, 125);
|
new TapActionDRScan(done, dRegIn, 125);
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = unpackBits (dRegOut,1+4+4+32+16+32,4);
|
status_ret = unpackBits(dRegOut, 1 + 4 + 4 + 32 + 16 + 32, 4);
|
calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);
|
calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);
|
recv_crc = BITREV(unpackBits (dRegOut,1+4+4+32+16+32+4,32),32);
|
recv_crc =
|
|
BITREV(unpackBits
|
|
(dRegOut, 1 + 4 + 4 + 32 + 16 + 32 + 4, 32), 32);
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
clearBits (dRegIn, drLen);
|
clearBits(dRegIn, drLen);
|
packBits (dRegIn, 0, 1, 0);
|
packBits(dRegIn, 0, 1, 0);
|
packBits (dRegIn, 0+1, 4, 0x0); // We're GO'ing command
|
packBits(dRegIn, 0 + 1, 4, 0x0); // We're GO'ing command
|
packBits (dRegIn, 0+1+4, 32, BITREV(data,32)); // Add in data
|
packBits(dRegIn, 0 + 1 + 4, 32, BITREV(data, 32)); // Add in data
|
crc32_send = crc32 (dRegIn,1+4+32,0);
|
crc32_send = crc32(dRegIn, 1 + 4 + 32, 0);
|
packBits (dRegIn, 1+4+32, 32, BITREV(crc32_send,32)); // CRC
|
packBits(dRegIn, 1 + 4 + 32, 32, BITREV(crc32_send, 32)); // CRC
|
|
|
// Loop until status is OK and CRCs match.
|
// Loop until status is OK and CRCs match.
|
do
|
do {
|
{
|
TapActionDRScan *dRScan = new TapActionDRScan(done, dRegIn,
|
TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, (1+4+((3+1)*8)+32+36));
|
(1 + 4 +
|
|
((3 + 1) * 8) +
|
|
32 + 36));
|
tapActionQueue->write (dRScan);
|
tapActionQueue->write (dRScan);
|
wait (*done);
|
wait(*done);
|
dRScan->getDRegOut (dRegOut);
|
dRScan->getDRegOut(dRegOut);
|
delete dRScan;
|
delete dRScan;
|
status_ret = unpackBits (dRegOut,1+4+32+32,4);
|
status_ret = unpackBits(dRegOut, 1 + 4 + 32 + 32, 4);
|
calc_recv_crc = crc32(dRegOut,4,1+4+32+32);
|
calc_recv_crc = crc32(dRegOut,4,1+4+32+32);
|
recv_crc = BITREV(unpackBits (dRegOut,1+4+32+32+4,32),32);
|
recv_crc =
|
|
BITREV(unpackBits(dRegOut, 1 + 4 + 32 + 32 + 4, 32), 32);
|
}
|
}
|
while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
|
while ((0 != status_ret) || (calc_recv_crc != recv_crc));
|
|
|
delete [] dRegIn;
|
delete[]dRegIn;
|
delete [] dRegOut;
|
delete[]dRegOut;
|
delete done;
|
delete done;
|
|
|
} // writeJtagReg ()
|
} // writeJtagReg ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Clear the bits in a data register
|
//! Clear the bits in a data register
|
|
|
//! We always clear whole 64-bit words, not just the minimum number of
|
//! We always clear whole 64-bit words, not just the minimum number of
|
//! bytes. It saves all sorts of confusion when debugging code.
|
//! bytes. It saves all sorts of confusion when debugging code.
|
|
|
//! @note It is the caller's responsibility to make sure the date register
|
//! @note It is the caller's responsibility to make sure the date register
|
//! array is large enough.
|
//! array is large enough.
|
|
|
//! @param[in,out] regArray The data register to clear
|
//! @param[in,out] regArray The data register to clear
|
//! @param[in] regBits Size of the data register (in bits)
|
//! @param[in] regBits Size of the data register (in bits)
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
void
|
void DebugUnitSC::clearBits(uint64_t regArray[], int regBits)
|
DebugUnitSC::clearBits (uint64_t regArray[],
|
|
int regBits)
|
|
{
|
{
|
memset ((char *)regArray, 0, ((regBits + 63) / 64) * 8);
|
memset((char *)regArray, 0, ((regBits + 63) / 64) * 8);
|
|
|
} // clearBits ()
|
} // clearBits ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Set a bit field in a data register
|
//! Set a bit field in a data register
|
|
|
//! The field is cleared, the supplied value masked and then ored into the
|
//! The field is cleared, the supplied value masked and then ored into the
|
//! vector.
|
//! vector.
|
|
|
//! @note It is the caller's responsibility to make sure the date register
|
//! @note It is the caller's responsibility to make sure the date register
|
//! array is large enough.
|
//! array is large enough.
|
|
|
//! @param[in,out] regArray The data register
|
//! @param[in,out] regArray The data register
|
//! @param[in] fieldOffset Start of the field (in bits)
|
//! @param[in] fieldOffset Start of the field (in bits)
|
//! @param[in] fieldBits Size of the field (in bits)
|
//! @param[in] fieldBits Size of the field (in bits)
|
//! @param[in] fieldVal Value to set in the field
|
//! @param[in] fieldVal Value to set in the field
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
void
|
void DebugUnitSC::packBits(uint64_t regArray[],
|
DebugUnitSC::packBits (uint64_t regArray[],
|
int fieldOffset, int fieldBits, uint64_t fieldVal)
|
int fieldOffset,
|
|
int fieldBits,
|
|
uint64_t fieldVal)
|
|
{
|
{
|
fieldVal &= (1ULL << fieldBits) - 1ULL; // Mask the supplied value
|
fieldVal &= (1ULL << fieldBits) - 1ULL; // Mask the supplied value
|
|
|
int startWord = fieldOffset / 64;
|
int startWord = fieldOffset / 64;
|
int endWord = (fieldOffset + fieldBits - 1) / 64;
|
int endWord = (fieldOffset + fieldBits - 1) / 64;
|
|
|
fieldOffset = fieldOffset % 64; // Now refers to target word
|
fieldOffset = fieldOffset % 64; // Now refers to target word
|
|
|
// Deal with the startWord. Get enough bits for the mask and put them in the
|
// Deal with the startWord. Get enough bits for the mask and put them in the
|
// right place
|
// right place
|
uint64_t startMask = ((1ULL << fieldBits) - 1ULL) << fieldOffset;
|
uint64_t startMask = ((1ULL << fieldBits) - 1ULL) << fieldOffset;
|
|
|
regArray[startWord] &= ~startMask;
|
regArray[startWord] &= ~startMask;
|
regArray[startWord] |= fieldVal << fieldOffset;
|
regArray[startWord] |= fieldVal << fieldOffset;
|
|
|
// If we were all in one word, we can give up now.
|
// If we were all in one word, we can give up now.
|
if (startWord == endWord)
|
if (startWord == endWord) {
|
{
|
|
return;
|
return;
|
}
|
}
|
|
|
// Deal with the endWord. Get enough bits for the mask. No need to shift
|
// Deal with the endWord. Get enough bits for the mask. No need to shift
|
// these up - they're always at the bottom of the word
|
// these up - they're always at the bottom of the word
|
int bitsToDo = (fieldOffset + fieldBits) % 64;
|
int bitsToDo = (fieldOffset + fieldBits) % 64;
|
uint64_t endMask = (1ULL << bitsToDo) - 1ULL;
|
uint64_t endMask = (1ULL << bitsToDo) - 1ULL;
|
|
|
regArray[endWord] &= ~endMask;
|
regArray[endWord] &= ~endMask;
|
regArray[endWord] |= fieldVal >> (fieldBits - bitsToDo);
|
regArray[endWord] |= fieldVal >> (fieldBits - bitsToDo);
|
|
|
} // packBits ()
|
} // packBits ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Extract a bit field from a data register
|
//! Extract a bit field from a data register
|
|
|
//! The field is cleared, the supplied value masked and then ored into the
|
//! The field is cleared, the supplied value masked and then ored into the
|
//! vector.
|
//! vector.
|
|
|
//! @note It is the caller's responsibility to make sure the date register
|
//! @note It is the caller's responsibility to make sure the date register
|
//! array is large enough.
|
//! array is large enough.
|
|
|
//! @param[in,out] regArray The data register
|
//! @param[in,out] regArray The data register
|
//! @param[in] fieldOffset Start of the field (in bits)
|
//! @param[in] fieldOffset Start of the field (in bits)
|
//! @param[in] fieldBits Size of the field (in bits)
|
//! @param[in] fieldBits Size of the field (in bits)
|
|
|
//! @return The value in the field
|
//! @return The value in the field
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
uint64_t
|
uint64_t
|
DebugUnitSC::unpackBits (uint64_t regArray[],
|
DebugUnitSC::unpackBits(uint64_t regArray[], int fieldOffset, int fieldBits)
|
int fieldOffset,
|
|
int fieldBits)
|
|
{
|
{
|
int startWord = fieldOffset / 64;
|
int startWord = fieldOffset / 64;
|
int endWord = (fieldOffset + fieldBits - 1) / 64;
|
int endWord = (fieldOffset + fieldBits - 1) / 64;
|
|
|
fieldOffset = fieldOffset % 64; // Now refers to target word
|
fieldOffset = fieldOffset % 64; // Now refers to target word
|
|
|
// Deal with the startWord. Get enough bits for the mask and put them in the
|
// Deal with the startWord. Get enough bits for the mask and put them in the
|
// right place
|
// right place
|
uint64_t startMask = ((1ULL << fieldBits) - 1ULL) << fieldOffset;
|
uint64_t startMask = ((1ULL << fieldBits) - 1ULL) << fieldOffset;
|
uint64_t res = (regArray[startWord] & startMask) >> fieldOffset;
|
uint64_t res = (regArray[startWord] & startMask) >> fieldOffset;
|
|
|
// If we were all in one word, we can give up now.
|
// If we were all in one word, we can give up now.
|
if (startWord == endWord)
|
if (startWord == endWord) {
|
{
|
|
res &= (1ULL << fieldBits) - 1ULL; // Mask off any unwanted bits
|
res &= (1ULL << fieldBits) - 1ULL; // Mask off any unwanted bits
|
return res;
|
return res;
|
}
|
}
|
|
|
// Deal with the endWord. Get enough bits for the mask. No need to shift
|
// Deal with the endWord. Get enough bits for the mask. No need to shift
|
// these up - they're always at the bottom of the word
|
// these up - they're always at the bottom of the word
|
int bitsToDo = (fieldOffset + fieldBits) % 64;
|
int bitsToDo = (fieldOffset + fieldBits) % 64;
|
uint64_t endMask = (1ULL << bitsToDo) - 1ULL;
|
uint64_t endMask = (1ULL << bitsToDo) - 1ULL;
|
|
|
res = res | ((regArray[endWord] & endMask) << (fieldBits - bitsToDo));
|
res = res | ((regArray[endWord] & endMask) << (fieldBits - bitsToDo));
|
res &= (1ULL << fieldBits) - 1ULL; // Mask off any unwanted bits
|
res &= (1ULL << fieldBits) - 1ULL; // Mask off any unwanted bits
|
return res;
|
return res;
|
|
|
} // unpackBits ()
|
} // unpackBits ()
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//! Compute CRC-8-ATM
|
//! Compute CRC-8-ATM
|
|
|
//! The data is in an array of uint64_t, for which we use the first size bits
|
//! The data is in an array of uint64_t, for which we use the first size bits
|
//! to compute the CRC.
|
//! to compute the CRC.
|
|
|
//! @Note I am using the same algorithm as the ORPSoC debug unit, but I
|
//! @Note I am using the same algorithm as the ORPSoC debug unit, but I
|
//! believe its function is broken! I don't believe the data bit should
|
//! believe its function is broken! I don't believe the data bit should
|
//! feature in the computation of bits 2 & 1 of the new CRC.
|
//! feature in the computation of bits 2 & 1 of the new CRC.
|
|
|
//! @Note I've realized that this is an algorithm for LSB first, so maybe it
|
//! @Note I've realized that this is an algorithm for LSB first, so maybe it
|
//! is correct!
|
//! is correct!
|
|
|
//! @param dataArray The array of data whose CRC is desired
|
//! @param dataArray The array of data whose CRC is desired
|
//! @param size The number of bits in the data
|
//! @param size The number of bits in the data
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
uint8_t
|
uint8_t DebugUnitSC::crc8(uint64_t dataArray[], int size)
|
DebugUnitSC::crc8 (uint64_t dataArray[],
|
|
int size)
|
|
{
|
{
|
uint8_t crc = 0;
|
uint8_t crc = 0;
|
|
|
for (int i = 0; i < size; i++)
|
for (int i = 0; i < size; i++) {
|
{
|
|
uint8_t d = (dataArray[i / 64] >> (i % 64)) & 1;
|
uint8_t d = (dataArray[i / 64] >> (i % 64)) & 1;
|
uint8_t oldCrc7 = (crc >> 7) & 1;
|
uint8_t oldCrc7 = (crc >> 7) & 1;
|
uint8_t oldCrc1 = (crc >> 1) & 1;
|
uint8_t oldCrc1 = (crc >> 1) & 1;
|
uint8_t oldCrc0 = (crc >> 0) & 1;
|
uint8_t oldCrc0 = (crc >> 0) & 1;
|
uint8_t newCrc2 = d ^ oldCrc1 ^ oldCrc7; // Why d?
|
uint8_t newCrc2 = d ^ oldCrc1 ^ oldCrc7; // Why d?
|
uint8_t newCrc1 = d ^ oldCrc0 ^ oldCrc7; // Why d?
|
uint8_t newCrc1 = d ^ oldCrc0 ^ oldCrc7; // Why d?
|
uint8_t newCrc0 = d ^ oldCrc7;
|
uint8_t newCrc0 = d ^ oldCrc7;
|
|
|
crc = ((crc << 1) & 0xf8) | (newCrc2 << 2) | (newCrc1 << 1) | newCrc0;
|
crc =
|
|
((crc << 1) & 0xf8) | (newCrc2 << 2) | (newCrc1 << 1) |
|
|
newCrc0;
|
}
|
}
|
|
|
return crc;
|
return crc;
|
|
|
} // crc8 ()
|
} // crc8 ()
|
|
|
/* Crc of current read or written data. */
|
/* Crc of current read or written data. */
|
uint32_t crc_r, crc_w = 0;
|
uint32_t crc_r, crc_w = 0;
|
|
|
/* Generates new crc, sending in new bit input_bit */
|
/* Generates new crc, sending in new bit input_bit */
|
uint32_t
|
uint32_t DebugUnitSC::crc32(uint64_t dataArray[], int size, int offset)
|
DebugUnitSC::crc32(uint64_t dataArray[],
|
|
int size,
|
|
int offset)
|
|
{
|
{
|
uint32_t crc = 0xffffffff;
|
uint32_t crc = 0xffffffff;
|
for (int i = offset; i < size+offset; i++)
|
for (int i = offset; i < size + offset; i++) {
|
{
|
uint32_t d =
|
uint32_t d = ((dataArray[i / 64] >> (i % 64)) & 1) ? 0xfffffff : 0x0000000;
|
((dataArray[i / 64] >> (i % 64)) & 1) ? 0xfffffff :
|
|
0x0000000;
|
uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
|
uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
|
crc <<= 1;
|
crc <<= 1;
|
crc = crc ^ ((d ^ crc_32) & DBG_CRC32_POLY);
|
crc = crc ^ ((d ^ crc_32) & DBG_CRC32_POLY);
|
}
|
}
|
|
|
return crc;
|
return crc;
|
}
|
}
|
|
|
uint32_t
|
uint32_t DebugUnitSC::bit_reverse_swar_2(uint32_t x)
|
DebugUnitSC::bit_reverse_swar_2(uint32_t x)
|
|
{
|
{
|
return (((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
|
return (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
|
}
|
}
|
uint32_t
|
|
DebugUnitSC::bit_reverse_swar_4(uint32_t x)
|
uint32_t DebugUnitSC::bit_reverse_swar_4(uint32_t x)
|
{
|
{
|
x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
|
x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
|
x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
|
x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
|
return x;
|
return x;
|
}
|
}
|
uint32_t
|
|
DebugUnitSC::bit_reverse_swar_8(uint32_t x)
|
uint32_t DebugUnitSC::bit_reverse_swar_8(uint32_t x)
|
{
|
{
|
x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
|
x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
|
x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
|
x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
|
x=(((x&0xf0f0f0f0)>>4)|((x&0x0f0f0f0f)<<4));
|
x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
|
return x;
|
return x;
|
}
|
}
|
uint32_t
|
|
DebugUnitSC::bit_reverse_swar_16(uint32_t x)
|
uint32_t DebugUnitSC::bit_reverse_swar_16(uint32_t x)
|
{
|
{
|
x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
|
x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
|
x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
|
x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
|
x=(((x&0xf0f0f0f0)>>4)|((x&0x0f0f0f0f)<<4));
|
x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
|
x=(((x&0xff00ff00)>>8)|((x&0x00ff00ff)<<8));
|
x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
|
return x;
|
return x;
|
}
|
}
|
uint32_t
|
|
DebugUnitSC::bit_reverse_swar_32(uint32_t x)
|
uint32_t DebugUnitSC::bit_reverse_swar_32(uint32_t x)
|
{
|
{
|
x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
|
x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
|
x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
|
x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
|
x=(((x&0xf0f0f0f0)>>4)|((x&0x0f0f0f0f)<<4));
|
x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
|
x=(((x&0xff00ff00)>>8)|((x&0x00ff00ff)<<8));
|
x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
|
x=(((x&0xffff0000)>>16)|((x&0x0000ffff)<<16)); // We could be on 64-bit arch!
|
x = (((x & 0xffff0000) >> 16) | ((x & 0x0000ffff) << 16)); // We could be on 64-bit arch!
|
return x;
|
return x;
|
}
|
}
|
|
|
uint32_t
|
uint32_t DebugUnitSC::bit_reverse_data(uint32_t data, int length)
|
DebugUnitSC::bit_reverse_data(uint32_t data, int length){
|
{
|
if (length == 2) return bit_reverse_swar_2(data);
|
if (length == 2)
|
if (length == 4) return bit_reverse_swar_4(data);
|
return bit_reverse_swar_2(data);
|
if (length == 8) return bit_reverse_swar_8(data);
|
if (length == 4)
|
if (length == 16) return bit_reverse_swar_16(data);
|
return bit_reverse_swar_4(data);
|
if (length == 32) return bit_reverse_swar_32(data);
|
if (length == 8)
|
|
return bit_reverse_swar_8(data);
|
|
if (length == 16)
|
|
return bit_reverse_swar_16(data);
|
|
if (length == 32)
|
|
return bit_reverse_swar_32(data);
|
// Long and laborious way - hopefully never gets called anymore!
|
// Long and laborious way - hopefully never gets called anymore!
|
uint32_t reverse=0;
|
uint32_t reverse=0;
|
for (int i=0;i<length;i++) reverse |= (((data>>i)&1)<<(length-1-i));
|
for (int i = 0; i < length; i++)
|
|
reverse |= (((data >> i) & 1) << (length - 1 - i));
|
return reverse;
|
return reverse;
|
}
|
}
|
|
|
