/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// ORPSoC SystemC Testbench ////
|
//// ORPSoC SystemC Testbench ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// ORPSoC Testbench file ////
|
//// ORPSoC Testbench file ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
|
//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
|
//// - Julius Baxter jb@orsoc.se ////
|
//// - Julius Baxter jb@orsoc.se ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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|
|
#include "OrpsocMain.h"
|
#include "OrpsocMain.h"
|
|
|
#include "JtagSC_includes.h"
|
// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
|
|
// them and include/exclude RSP stuff. For now is defined
|
|
//#define JTAG_DEBUG
|
|
|
#include "Vorpsoc_top.h"
|
#include "Vorpsoc_top.h"
|
#include "OrpsocAccess.h"
|
#include "OrpsocAccess.h"
|
#include "MemoryLoad.h"
|
#include "MemoryLoad.h"
|
|
|
#include <verilated_vcd_c.h>
|
#include <verilated_vcd_c.h>
|
|
|
#include "ResetSC.h"
|
#include "ResetSC.h"
|
#include "Or1200MonitorSC.h"
|
#include "Or1200MonitorSC.h"
|
|
|
|
#ifdef JTAG_DEBUG
|
#include "GdbServerSC.h"
|
#include "GdbServerSC.h"
|
|
# include "JtagSC_includes.h"
|
|
#endif
|
|
|
#include "UartSC.h"
|
#include "UartSC.h"
|
|
|
int SIM_RUNNING;
|
int SIM_RUNNING;
|
int sc_main (int argc,
|
int sc_main (int argc,
|
char *argv[] )
|
char *argv[] )
|
{
|
{
|
sc_set_time_resolution( 1, TIMESCALE_UNIT);
|
sc_set_time_resolution( 1, TIMESCALE_UNIT);
|
// CPU clock (also used as JTAG TCK) and reset (both active high and low)
|
// CPU clock (also used as JTAG TCK) and reset (both active high and low)
|
sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
|
sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
|
sc_time jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
|
|
|
|
sc_clock clk ("clk", clkPeriod);
|
sc_clock clk ("clk", clkPeriod);
|
sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
|
|
|
|
sc_signal<bool> rst;
|
sc_signal<bool> rst;
|
sc_signal<bool> rstn;
|
sc_signal<bool> rstn;
|
|
|
|
#ifdef JTAG_DEBUG
|
|
sc_time jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
|
|
sc_clock jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
|
|
|
sc_signal<bool> jtag_tdi; // JTAG interface
|
sc_signal<bool> jtag_tdi; // JTAG interface
|
sc_signal<bool> jtag_tdo;
|
sc_signal<bool> jtag_tdo;
|
sc_signal<bool> jtag_tms;
|
sc_signal<bool> jtag_tms;
|
sc_signal<bool> jtag_trst;
|
sc_signal<bool> jtag_trst;
|
|
#endif
|
|
|
sc_signal<bool> uart_rx; // External UART
|
sc_signal<bool> uart_rx; // External UART
|
sc_signal<bool> uart_tx;
|
sc_signal<bool> uart_tx;
|
|
|
SIM_RUNNING = 0;
|
SIM_RUNNING = 0;
|
|
|
// Setup the name of the VCD dump file
|
// Setup the name of the VCD dump file
|
bool VCD_enabled = false;
|
bool VCD_enabled = false;
|
string dumpNameDefault("vlt-dump.vcd");
|
string dumpNameDefault("vlt-dump.vcd");
|
string testNameString;
|
string testNameString;
|
string vcdDumpFile;
|
string vcdDumpFile;
|
// VCD dump controling vars
|
// VCD dump controling vars
|
bool dump_start_delay_set = false, dump_stop_set = false;
|
bool dump_start_delay_set = false, dump_stop_set = false;
|
bool dumping_now = false;
|
bool dumping_now = false;
|
int dump_depth = 99; // Default dump depth
|
int dump_depth = 99; // Default dump depth
|
sc_time dump_start,dump_stop, finish_time;
|
sc_time dump_start,dump_stop, finish_time;
|
bool finish_time_set = false; // By default we will let the simulation finish naturally
|
bool finish_time_set = false; // By default we will let the simulation
|
|
// finish naturally
|
VerilatedVcdC *verilatorVCDFile;
|
VerilatedVcdC *verilatorVCDFile;
|
|
|
/*int*/double time_val;
|
/*int*/double time_val;
|
bool vcd_file_name_given = false;
|
bool vcd_file_name_given = false;
|
|
|
|
#ifdef JTAG_DEBUG
|
bool rsp_server_enabled = false;
|
bool rsp_server_enabled = false;
|
int rsp_server_port = DEFAULT_RSP_PORT;
|
int rsp_server_port = DEFAULT_RSP_PORT;
|
|
#endif
|
|
|
// Executable app load variables
|
// Executable app load variables
|
int do_program_file_load = 0; // Default: we don't require a file, we use the VMEM
|
int do_program_file_load = 0; // Default: we don't require a file, we use the
|
|
// VMEM
|
char* program_file; // Old char* style for program name
|
char* program_file; // Old char* style for program name
|
|
|
// Verilator accessor
|
// Verilator accessor
|
OrpsocAccess *accessor;
|
OrpsocAccess *accessor;
|
|
|
// Modules
|
// Modules
|
Vorpsoc_top *orpsoc; // Verilated ORPSoC
|
Vorpsoc_top *orpsoc; // Verilated ORPSoC
|
|
|
MemoryLoad *memoryload; // Memory loader
|
MemoryLoad *memoryload; // Memory loader
|
|
|
ResetSC *reset; // Generate a RESET signal
|
ResetSC *reset; // Generate a RESET signal
|
|
|
Or1200MonitorSC *monitor; // Handle l.nop x instructions
|
Or1200MonitorSC *monitor; // Handle l.nop x instructions
|
|
|
|
#ifdef JTAG_DEBUG
|
JtagSC *jtag; // Generate JTAG signals
|
JtagSC *jtag; // Generate JTAG signals
|
GdbServerSC *gdbServer; // Map RSP requests to debug unit
|
GdbServerSC *gdbServer; // Map RSP requests to debug unit
|
|
#endif
|
|
|
UartSC *uart; // Handle UART signals
|
UartSC *uart; // Handle UART signals
|
|
|
// Instantiate the Verilator model, VCD trace handler and accessor
|
// Instantiate the Verilator model, VCD trace handler and accessor
|
orpsoc = new Vorpsoc_top ("orpsoc");
|
orpsoc = new Vorpsoc_top ("orpsoc");
|
|
|
accessor = new OrpsocAccess (orpsoc);
|
accessor = new OrpsocAccess (orpsoc);
|
|
|
memoryload = new MemoryLoad (accessor);
|
memoryload = new MemoryLoad (accessor);
|
|
|
monitor = new Or1200MonitorSC ("monitor", accessor, memoryload,
|
monitor = new Or1200MonitorSC ("monitor", accessor, memoryload,
|
argc, argv);
|
argc, argv);
|
|
|
// Instantiate the SystemC modules
|
// Instantiate the SystemC modules
|
reset = new ResetSC ("reset", BENCH_RESET_TIME);
|
reset = new ResetSC ("reset", BENCH_RESET_TIME);
|
|
|
|
#ifdef JTAG_DEBUG
|
jtag = new JtagSC ("jtag");
|
jtag = new JtagSC ("jtag");
|
|
#endif
|
|
|
uart = new UartSC("uart"); // TODO: Probalby some sort of param
|
uart = new UartSC("uart"); // TODO: Probalby some sort of param
|
|
|
// Parse command line options
|
// Parse command line options
|
// Default is for VCD generation OFF, only turned on if specified on command line
|
// Default is for VCD generation OFF, only turned on if specified on command
|
|
// line
|
|
|
// Search through the command line parameters for options
|
// Search through the command line parameters for options
|
if (argc > 1)
|
if (argc > 1)
|
{
|
{
|
for(int i=1; i<argc; i++)
|
for(int i=1; i<argc; i++)
|
{
|
{
|
if ( (strcmp(argv[i], "-e")==0) ||
|
if ( (strcmp(argv[i], "-e")==0) ||
|
(strcmp(argv[i], "--endtime")==0) )
|
(strcmp(argv[i], "--endtime")==0) )
|
{
|
{
|
time_val = strtod(argv[i+1], NULL);
|
time_val = strtod(argv[i+1], NULL);
|
sc_time opt_end_time(time_val,TIMESCALE_UNIT);
|
sc_time opt_end_time(time_val,TIMESCALE_UNIT);
|
finish_time = opt_end_time;
|
finish_time = opt_end_time;
|
finish_time_set = true;
|
finish_time_set = true;
|
}
|
}
|
else if ( (strcmp(argv[i], "-f")==0) ||
|
else if ( (strcmp(argv[i], "-f")==0) ||
|
(strcmp(argv[i], "--program")==0) )
|
(strcmp(argv[i], "--program")==0) )
|
{
|
{
|
do_program_file_load = 1; // Enable program loading - will be done after sim init
|
do_program_file_load = 1; // Enable program loading - will be
|
|
// done after sim init.
|
program_file = argv[i+1]; // Old char* style for program name
|
program_file = argv[i+1]; // Old char* style for program name
|
}
|
}
|
else if ((strcmp(argv[i], "-d")==0) ||
|
else if ((strcmp(argv[i], "-d")==0) ||
|
(strcmp(argv[i], "--vcdfile")==0) ||
|
(strcmp(argv[i], "--vcdfile")==0) ||
|
(strcmp(argv[i], "-v")==0) ||
|
(strcmp(argv[i], "-v")==0) ||
|
(strcmp(argv[i], "--vcdon")==0)
|
(strcmp(argv[i], "--vcdon")==0)
|
)
|
)
|
{
|
{
|
VCD_enabled = true;
|
VCD_enabled = true;
|
dumping_now = true;
|
dumping_now = true;
|
vcdDumpFile = dumpNameDefault;
|
vcdDumpFile = dumpNameDefault;
|
if (i+1 < argc)
|
if (i+1 < argc)
|
if(argv[i+1][0] != '-')
|
if(argv[i+1][0] != '-')
|
{
|
{
|
testNameString = argv[i+1];
|
testNameString = argv[i+1];
|
vcdDumpFile = testNameString;
|
vcdDumpFile = testNameString;
|
i++;
|
i++;
|
}
|
}
|
}
|
}
|
else if ( (strcmp(argv[i], "-s")==0) ||
|
else if ( (strcmp(argv[i], "-s")==0) ||
|
(strcmp(argv[i], "--vcdstart")==0) )
|
(strcmp(argv[i], "--vcdstart")==0) )
|
{
|
{
|
VCD_enabled = true;
|
VCD_enabled = true;
|
time_val = strtod(argv[i+1], NULL);
|
time_val = strtod(argv[i+1], NULL);
|
sc_time dump_start_time(time_val,TIMESCALE_UNIT);
|
sc_time dump_start_time(time_val,TIMESCALE_UNIT);
|
dump_start = dump_start_time;
|
dump_start = dump_start_time;
|
dump_start_delay_set = true;
|
dump_start_delay_set = true;
|
dumping_now = false;
|
dumping_now = false;
|
}
|
}
|
else if ( (strcmp(argv[i], "-t")==0) ||
|
else if ( (strcmp(argv[i], "-t")==0) ||
|
(strcmp(argv[i], "--vcdstop")==0) )
|
(strcmp(argv[i], "--vcdstop")==0) )
|
{
|
{
|
VCD_enabled = true;
|
VCD_enabled = true;
|
time_val = strtod(argv[i+1],NULL);
|
time_val = strtod(argv[i+1],NULL);
|
sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
|
sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
|
dump_stop = dump_stop_time;
|
dump_stop = dump_stop_time;
|
dump_stop_set = true;
|
dump_stop_set = true;
|
}
|
}
|
|
#ifdef JTAG_DEBUG
|
else if ( (strcmp(argv[i], "-r")==0) ||
|
else if ( (strcmp(argv[i], "-r")==0) ||
|
(strcmp(argv[i], "--rsp")==0) )
|
(strcmp(argv[i], "--rsp")==0) )
|
{
|
{
|
rsp_server_enabled = true;
|
rsp_server_enabled = true;
|
if (i+1 < argc) if(argv[i+1][0] != '-')
|
if (i+1 < argc) if(argv[i+1][0] != '-')
|
{
|
{
|
rsp_server_port = atoi(argv[i+1]);
|
rsp_server_port = atoi(argv[i+1]);
|
i++;
|
i++;
|
}
|
}
|
}
|
}
|
|
#endif
|
/*
|
/*
|
Depth setting of VCD doesn't appear to work, I think it's only
|
Depth setting of VCD doesn't appear to work, I think it's only
|
configurable during at compile time .
|
configurable during at compile time .
|
*/
|
*/
|
/* else if ( (strcmp(argv[i], "-p")==0) ||
|
/* else if ( (strcmp(argv[i], "-p")==0) ||
|
(strcmp(argv[i], "--vcddepth")==0) )
|
(strcmp(argv[i], "--vcddepth")==0) )
|
{
|
{
|
dump_depth = atoi(argv[i+1]);
|
dump_depth = atoi(argv[i+1]);
|
}*/
|
}*/
|
else if ( (strcmp(argv[i], "-h")==0) ||
|
else if ( (strcmp(argv[i], "-h")==0) ||
|
(strcmp(argv[i], "--help")==0) )
|
(strcmp(argv[i], "--help")==0) )
|
{
|
{
|
printf("Usage: %s [options]\n",argv[0]);
|
printf("Usage: %s [options]\n",argv[0]);
|
printf("\n ORPSoCv2 cycle accurate model\n");
|
printf("\n ORPSoCv2 cycle accurate model\n");
|
printf(" For details visit http://opencores.org/openrisc,orpsocv2\n");
|
printf(" For details visit http://opencores.org/openrisc,orpsocv2\n");
|
printf("\n");
|
printf("\n");
|
printf("Options:\n");
|
printf("Options:\n");
|
printf(" -h, --help\t\tPrint this help message\n");
|
printf(" -h, --help\t\tPrint this help message\n");
|
printf("\nSimulation control:\n");
|
printf("\nSimulation control:\n");
|
printf(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");
|
printf(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");
|
printf(" -e, --endtime <val> \tStop the sim at <val> ns\n");
|
printf(" -e, --endtime <val> \tStop the sim at <val> ns\n");
|
printf("\nVCD generation:\n");
|
printf("\nVCD generation:\n");
|
printf(" -v, --vcdon\t\tEnable VCD generation\n");
|
printf(" -v, --vcdon\t\tEnable VCD generation\n");
|
printf(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
|
printf(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
|
|
|
printf(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
|
printf(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
|
printf(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
|
printf(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
|
|
#ifdef JTAG_DEBUG
|
printf("\nRemote debugging:\n");
|
printf("\nRemote debugging:\n");
|
printf(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
|
printf(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
|
|
#endif
|
monitor->printUsage();
|
monitor->printUsage();
|
printf("\n");
|
printf("\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
// Determine if we're going to setup a VCD dump:
|
// Determine if we're going to setup a VCD dump:
|
// Pretty much setting any related option will enable VCD dumping.
|
// Pretty much setting any related option will enable VCD dumping.
|
if (VCD_enabled)
|
if (VCD_enabled)
|
{
|
{
|
|
|
cout << "* Enabling VCD trace";
|
cout << "* Enabling VCD trace";
|
|
|
if (dump_start_delay_set)
|
if (dump_start_delay_set)
|
cout << ", on at time " << dump_start.to_string();
|
cout << ", on at time " << dump_start.to_string();
|
if (dump_stop_set)
|
if (dump_stop_set)
|
cout << ", off at time " << dump_stop.to_string();
|
cout << ", off at time " << dump_stop.to_string();
|
cout << endl;
|
cout << endl;
|
}
|
}
|
|
#ifdef JTAG_DEBUG
|
if (rsp_server_enabled)
|
if (rsp_server_enabled)
|
gdbServer = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
|
gdbServer = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
|
rsp_server_port, jtag->tapActionQueue);
|
rsp_server_port, jtag->tapActionQueue);
|
else
|
else
|
gdbServer = NULL;
|
gdbServer = NULL;
|
|
#endif
|
|
|
// Connect up ORPSoC
|
// Connect up ORPSoC
|
orpsoc->clk_pad_i (clk);
|
orpsoc->clk_pad_i (clk);
|
orpsoc->rst_n_pad_i (rstn);
|
orpsoc->rst_n_pad_i (rstn);
|
|
|
|
#ifdef JTAG_DEBUG
|
orpsoc->tck_pad_i (jtag_tck); // JTAG interface
|
orpsoc->tck_pad_i (jtag_tck); // JTAG interface
|
orpsoc->tdi_pad_i (jtag_tdi);
|
orpsoc->tdi_pad_i (jtag_tdi);
|
orpsoc->tms_pad_i (jtag_tms);
|
orpsoc->tms_pad_i (jtag_tms);
|
orpsoc->tdo_pad_o (jtag_tdo);
|
orpsoc->tdo_pad_o (jtag_tdo);
|
|
#endif
|
|
|
orpsoc->uart0_srx_pad_i (uart_rx); // External UART
|
orpsoc->uart0_srx_pad_i (uart_rx); // External UART
|
orpsoc->uart0_stx_pad_o (uart_tx);
|
orpsoc->uart0_stx_pad_o (uart_tx);
|
|
|
// Connect up the SystemC modules
|
// Connect up the SystemC modules
|
reset->clk (clk); // Reset
|
reset->clk (clk); // Reset
|
reset->rst (rst);
|
reset->rst (rst);
|
reset->rstn (rstn);
|
reset->rstn (rstn);
|
|
|
monitor->clk (clk); // Monitor
|
monitor->clk (clk); // Monitor
|
|
|
|
#ifdef JTAG_DEBUG
|
jtag->sysReset (rst); // JTAG
|
jtag->sysReset (rst); // JTAG
|
jtag->tck (jtag_tck);
|
jtag->tck (jtag_tck);
|
jtag->tdi (jtag_tdi);
|
jtag->tdi (jtag_tdi);
|
jtag->tdo (jtag_tdo);
|
jtag->tdo (jtag_tdo);
|
jtag->tms (jtag_tms);
|
jtag->tms (jtag_tms);
|
jtag->trst (jtag_trst);
|
jtag->trst (jtag_trst);
|
|
#endif
|
|
|
uart->clk (clk); // Uart
|
uart->clk (clk); // Uart
|
uart->uartrx (uart_rx); // orpsoc's receive line
|
uart->uartrx (uart_rx); // orpsoc's receive line
|
uart->uarttx (uart_tx); // orpsoc's transmit line
|
uart->uarttx (uart_tx); // orpsoc's transmit line
|
|
|
// Tie off signals
|
// Tie off signals
|
|
#ifdef JTAG_DEBUG
|
jtag_tdi = 1; // Tie off the JTAG inputs
|
jtag_tdi = 1; // Tie off the JTAG inputs
|
jtag_tms = 1;
|
jtag_tms = 1;
|
|
#endif
|
|
|
if (VCD_enabled)
|
if (VCD_enabled)
|
{
|
{
|
Verilated::traceEverOn (true);
|
Verilated::traceEverOn (true);
|
|
|
printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
|
printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
|
|
|
// Establish a new trace with its correct time resolution, and trace to
|
// Establish a new trace with its correct time resolution, and trace to
|
// great depth.
|
// great depth.
|
verilatorVCDFile = new VerilatedVcdC ();
|
verilatorVCDFile = new VerilatedVcdC ();
|
//verilatorVCDFile->verilated()->set_time_resolution (sc_get_time_resolution());
|
|
//setSpTimeResolution (sc_get_time_resolution ());
|
|
//traceTarget->trace (verilatorVCDFile, 99);
|
|
orpsoc->trace (verilatorVCDFile, dump_depth);
|
orpsoc->trace (verilatorVCDFile, dump_depth);
|
|
|
if (dumping_now)
|
if (dumping_now)
|
{
|
{
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
}
|
}
|
}
|
}
|
|
|
//printf("* Beginning test\n");
|
//printf("* Beginning test\n");
|
|
|
// Init the UART function
|
// Init the UART function
|
uart->initUart(50000000, 115200);
|
uart->initUart(50000000, 115200);
|
|
|
if (do_program_file_load) // Did the user specify a file to load?
|
if (do_program_file_load) // Did the user specify a file to load?
|
{
|
{
|
cout << "* Loading program from " << program_file << endl;
|
cout << "* Loading program from " << program_file << endl;
|
if (memoryload->loadcode(program_file,0,0) < 0)
|
if (memoryload->loadcode(program_file,0,0) < 0)
|
{
|
{
|
cout << "* Error: executable file " << program_file << " not loaded" << endl;
|
cout << "* Error: executable file " << program_file <<
|
|
" not loaded" << endl;
|
}
|
}
|
}
|
}
|
else // Load SRAM from VMEM file
|
else // Load SRAM from VMEM file
|
{
|
{
|
accessor->do_ram_readmemh();
|
accessor->do_ram_readmemh();
|
}
|
}
|
|
|
SIM_RUNNING = 1;
|
SIM_RUNNING = 1;
|
|
|
// First check how we should run the sim.
|
// First check how we should run the sim.
|
if (VCD_enabled || finish_time_set)
|
if (VCD_enabled || finish_time_set)
|
{ // We'll run sim with step
|
{ // We'll run sim with step
|
|
|
if (!VCD_enabled && finish_time_set)
|
if (!VCD_enabled && finish_time_set)
|
{
|
{
|
// We just run the sim until the set finish time
|
// We just run the sim until the set finish time
|
sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
|
sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
|
SIM_RUNNING=0;
|
SIM_RUNNING=0;
|
sc_stop();
|
sc_stop();
|
// Print performance summary
|
// Print performance summary
|
monitor->perfSummary();
|
monitor->perfSummary();
|
// Do memdump if enabled
|
// Do memdump if enabled
|
monitor->memdump();
|
monitor->memdump();
|
}
|
}
|
else
|
else
|
{
|
{
|
if (dump_start_delay_set)
|
if (dump_start_delay_set)
|
{
|
{
|
// Run the sim until we want to dump
|
// Run the sim until we want to dump
|
sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
|
sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
|
// Open the trace file
|
// Open the trace file
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
verilatorVCDFile->open (vcdDumpFile.c_str());
|
dumping_now = 1;
|
dumping_now = 1;
|
}
|
}
|
|
|
if (dumping_now)
|
if (dumping_now)
|
{
|
{
|
// Step the sim and generate the trace
|
// Step the sim and generate the trace
|
// Execute until we stop
|
// Execute until we stop
|
while(!Verilated::gotFinish())
|
while(!Verilated::gotFinish())
|
{
|
{
|
if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
|
if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
|
sc_start (1,TIMESCALE_UNIT); // Step the sim
|
sc_start (1,TIMESCALE_UNIT); // Step the sim
|
else
|
else
|
{
|
{
|
verilatorVCDFile->close();
|
verilatorVCDFile->close();
|
break;
|
break;
|
}
|
}
|
|
|
verilatorVCDFile->dump (sc_time_stamp().to_double());
|
verilatorVCDFile->dump (sc_time_stamp().to_double());
|
|
|
if (dump_stop_set)
|
if (dump_stop_set)
|
{
|
{
|
if (sc_time_stamp() >= dump_stop)
|
if (sc_time_stamp() >= dump_stop)
|
{
|
{
|
// Close dump file
|
// Close dump file
|
verilatorVCDFile->close();
|
verilatorVCDFile->close();
|
// Now continue on again until the end
|
// Now continue on again until the end
|
if (!finish_time_set)
|
if (!finish_time_set)
|
sc_start();
|
sc_start();
|
else
|
else
|
{
|
{
|
// Determine how long we should run for
|
// Determine how long we should run for
|
sc_time sim_time_remaining =
|
sc_time sim_time_remaining =
|
finish_time - sc_time_stamp();
|
finish_time - sc_time_stamp();
|
sc_start((double)(sim_time_remaining.to_double()),
|
sc_start((double)(sim_time_remaining.to_double()),
|
TIMESCALE_UNIT);
|
TIMESCALE_UNIT);
|
// Officially stop the sim
|
// Officially stop the sim
|
sc_stop();
|
sc_stop();
|
// Print performance summary
|
// Print performance summary
|
monitor->perfSummary();
|
monitor->perfSummary();
|
// Do memdump if enabled
|
// Do memdump if enabled
|
monitor->memdump();
|
monitor->memdump();
|
}
|
}
|
break;
|
break;
|
}
|
}
|
}
|
}
|
if (finish_time_set)
|
if (finish_time_set)
|
{
|
{
|
if (sc_time_stamp() >= finish_time)
|
if (sc_time_stamp() >= finish_time)
|
{
|
{
|
// Officially stop the sim
|
// Officially stop the sim
|
sc_stop();
|
sc_stop();
|
// Close dump file
|
// Close dump file
|
verilatorVCDFile->close();
|
verilatorVCDFile->close();
|
// Do memdump if enabled
|
// Do memdump if enabled
|
monitor->memdump();
|
monitor->memdump();
|
// Print performance summary
|
// Print performance summary
|
monitor->perfSummary();
|
monitor->perfSummary();
|
break;
|
break;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
// Simple run case
|
// Simple run case
|
// Ideally a "l.nop 1" will terminate the simulation gracefully
|
// Ideally a "l.nop 1" will terminate the simulation gracefully.
|
// Need to step at clock period / 4, otherwise model appears to skip the monitor and logging functions sometimes (?!?)
|
// Need to step at clock period / 4, otherwise model appears to skip the
|
|
// monitor and logging functions sometimes (?!?)
|
while (SIM_RUNNING)
|
while (SIM_RUNNING)
|
sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
|
sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
|
//sc_start();
|
//sc_start();
|
}
|
}
|
|
|
|
|
// Free memory
|
// Free memory
|
|
#ifdef JTAG_DEBUG
|
if (rsp_server_enabled)
|
if (rsp_server_enabled)
|
delete gdbServer;
|
delete gdbServer;
|
|
|
delete jtag;
|
delete jtag;
|
|
#endif
|
|
|
delete monitor;
|
delete monitor;
|
|
|
delete reset;
|
delete reset;
|
|
|
delete accessor;
|
delete accessor;
|
|
|
//delete trace;
|
//delete trace;
|
|
|
delete orpsoc;
|
delete orpsoc;
|
|
|
return 0;
|
return 0;
|
|
|
} /* sc_main() */
|
} /* sc_main() */
|
|
|
