// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// SystemC reset signal generator
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// SystemC reset signal generator
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// This file is part of the cycle accurate model of the OpenRISC 1000 based
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// This file is part of the cycle accurate model of the OpenRISC 1000 based
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// system-on-chip, ORPSoC, built using Verilator.
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// system-on-chip, ORPSoC, built using Verilator.
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// This program is free software: you can redistribute it and/or modify it
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// This program is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or (at your
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// the Free Software Foundation, either version 3 of the License, or (at your
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// option) any later version.
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// option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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// License for more details.
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// You should have received a copy of the GNU Lesser General Public License
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// $Id: ResetSC.cpp 286 2009-02-03 11:19:30Z jeremy $
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// $Id: ResetSC.cpp 286 2009-02-03 11:19:30Z jeremy $
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#include "ResetSC.h"
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#include "ResetSC.h"
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SC_HAS_PROCESS( ResetSC );
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SC_HAS_PROCESS(ResetSC);
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//! Constructor for the reset generator
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//! Constructor for the reset generator
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//! @param name Name of this module, passed to the parent
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//! @param name Name of this module, passed to the parent
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//! constructor.
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//! constructor.
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//! @param resetCounter Number of cycles of reset to provide.
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//! @param resetCounter Number of cycles of reset to provide.
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ResetSC::ResetSC (sc_core::sc_module_name name,
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ResetSC::ResetSC(sc_core::sc_module_name name, int _resetCounter):
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int _resetCounter) :
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sc_module(name), resetCounter(_resetCounter)
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sc_module (name),
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resetCounter (_resetCounter)
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{
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{
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SC_METHOD (driveReset);
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SC_METHOD(driveReset);
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sensitive << clk.neg();
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sensitive << clk.neg();
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} // ResetSC ()
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} // ResetSC ()
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//! Method to drive the reset port (active low). We will be called as an
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//! Method to drive the reset port (active low). We will be called as an
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//! initialization, which can be used to drive the reset low.
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//! initialization, which can be used to drive the reset low.
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void
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void ResetSC::driveReset()
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ResetSC::driveReset()
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{
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if (resetCounter > 0)
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{
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{
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if (resetCounter > 0) {
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rst = 1;
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rst = 1;
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rstn = 0;
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rstn = 0;
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resetCounter--;
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resetCounter--;
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}
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} else {
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else
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{
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rst = 0;
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rst = 0;
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rstn = 1;
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rstn = 1;
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}
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}
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} // driveReset()
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} // driveReset()
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No newline at end of file
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No newline at end of file
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