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////                                                              ////

////                                                              ////

////  File name: eth_phy.v                                        ////

////  File name: eth_phy.v                                        ////

////                                                              ////

////                                                              ////

////  This file is part of the Ethernet IP core project           ////

////  This file is part of the Ethernet IP core project           ////

////  http://www.opencores.org/projects/ethmac/                   ////

////  http://www.opencores.org/projects/ethmac/                   ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Tadej Markovic, tadej@opencores.org                   ////

////      - Tadej Markovic, tadej@opencores.org                   ////

////                                                              ////

////                                                              ////

////  All additional information is available in the README.txt   ////

////  All additional information is available in the README.txt   ////

////  file.                                                       ////

////  file.                                                       ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2002  Authors                                  ////

//// Copyright (C) 2002  Authors                                  ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.7  2002/10/18 13:58:22  tadejm

// Revision 1.7  2002/10/18 13:58:22  tadejm

// Some code changed due to bug fixes.

// Some code changed due to bug fixes.

//

//

// Revision 1.6  2002/10/09 13:16:51  tadejm

// Revision 1.6  2002/10/09 13:16:51  tadejm

// Just back-up; not completed testbench and some testcases are not

// Just back-up; not completed testbench and some testcases are not

// wotking properly yet.

// wotking properly yet.

//

//

// Revision 1.5  2002/09/18 17:55:08  tadej

// Revision 1.5  2002/09/18 17:55:08  tadej

// Bug repaired in eth_phy device

// Bug repaired in eth_phy device

//

//

// Revision 1.3  2002/09/13 14:50:15  mohor

// Revision 1.3  2002/09/13 14:50:15  mohor

// Bug in MIIM fixed.

// Bug in MIIM fixed.

//

//

// Revision 1.2  2002/09/13 12:29:14  mohor

// Revision 1.2  2002/09/13 12:29:14  mohor

// Headers changed.

// Headers changed.

//

//

// Revision 1.1  2002/09/13 11:57:20  mohor

// Revision 1.1  2002/09/13 11:57:20  mohor

// New testbench. Thanks to Tadej M - "The Spammer".

// New testbench. Thanks to Tadej M - "The Spammer".

//

//

//

//

//

//

`include "timescale.v"

`include "timescale.v"

`include "eth_phy_defines.v"

`include "eth_phy_defines.v"

// ORPSoCv2 testbench include

// ORPSoCv2 testbench include

// Will enable verbose if eth test

// Will enable verbose if eth test

`ifdef TEST_DEFINE_FILE

`ifdef TEST_DEFINE_FILE

 `include "test_define.v"

 `include "test_define.v"

`endif

`endif

`define MULTICAST_XFR          0

`define MULTICAST_XFR          0

`define UNICAST_XFR            1

`define UNICAST_XFR            1

`define BROADCAST_XFR          2

`define BROADCAST_XFR          2

`define UNICAST_WRONG_XFR      3

`define UNICAST_WRONG_XFR      3

`define ETH_PHY_VERBOSE 1

`define ETH_PHY_VERBOSE 1

module eth_phy // This PHY model simulate simplified Intel LXT971A PHY

module eth_phy // This PHY model simulate simplified Intel LXT971A PHY

  (

  (

   // COMMON

   // COMMON

   m_rst_n_i,

   m_rst_n_i,

   // MAC TX

   // MAC TX

   mtx_clk_o,

   mtx_clk_o,

   mtxd_i,

   mtxd_i,

   mtxen_i,

   mtxen_i,

   mtxerr_i,

   mtxerr_i,

   // MAC RX

   // MAC RX

   mrx_clk_o,

   mrx_clk_o,

   mrxd_o,

   mrxd_o,

   mrxdv_o,

   mrxdv_o,

   mrxerr_o,

   mrxerr_o,

   // SMII signals

   // SMII signals

   smii_clk_i,

   smii_clk_i,

   smii_sync_i,

   smii_sync_i,

   smii_rx_o,

   smii_rx_o,

   mcoll_o,

   mcoll_o,

   mcrs_o,

   mcrs_o,

   // MIIM

   // MIIM

   mdc_i,

   mdc_i,

   md_io,

   md_io,

   speed_o,

   speed_o,

   link_o,

   link_o,

   duplex_o

   duplex_o

   );

   );

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

         //

         //

   // Input/output signals

   // Input/output signals

   //

   //

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   // MAC miscellaneous signals

   // MAC miscellaneous signals

   input           m_rst_n_i;

   input           m_rst_n_i;

   // MAC TX signals

   // MAC TX signals

   output          mtx_clk_o;

   output          mtx_clk_o;

   input [3:0]      mtxd_i;

   input [3:0]      mtxd_i;

   input           mtxen_i;

   input           mtxen_i;

   input           mtxerr_i;

   input           mtxerr_i;

   // MAC RX signals

   // MAC RX signals

   output          mrx_clk_o;

   output          mrx_clk_o;

   output [3:0]    mrxd_o;

   output [3:0]    mrxd_o;

   output          mrxdv_o;

   output          mrxdv_o;

   output          mrxerr_o;

   output          mrxerr_o;

   // SMII RX signals

   // SMII RX signals

   input           smii_clk_i;

   input           smii_clk_i;

   input           smii_sync_i;

   input           smii_sync_i;

   output          smii_rx_o;

   output          smii_rx_o;

   // MAC common signals

   // MAC common signals

   output          mcoll_o;

   output          mcoll_o;

   output          mcrs_o;

   output          mcrs_o;

   // MAC management signals

   // MAC management signals

   input           mdc_i;

   input           mdc_i;

   inout           md_io;

   inout           md_io;

   // Sideband signals for SMII -- jb

   // Sideband signals for SMII -- jb

   output          link_o;

   output          link_o;

   output          speed_o;

   output          speed_o;

   output          duplex_o;

   output          duplex_o;

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   //

   //

   // PHY management (MIIM) REGISTER definitions

   // PHY management (MIIM) REGISTER definitions

   //

   //

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   //

   //

   //   Supported registers:

   //   Supported registers:

   //

   //

   // Addr | Register Name

   // Addr | Register Name

   //--------------------------------------------------------------------

   //--------------------------------------------------------------------

   //   0  | Control reg.     |

   //   0  | Control reg.     |

   //   1  | Status reg. #1   |--> normal operation

   //   1  | Status reg. #1   |--> normal operation

   //   2  | PHY ID reg. 1    |

   //   2  | PHY ID reg. 1    |

   //   3  | PHY ID reg. 2    |

   //   3  | PHY ID reg. 2    |

   //----------------------

   //----------------------

   // Addr | Data MEMORY      |-->  for testing

   // Addr | Data MEMORY      |-->  for testing

   //

   //

   //--------------------------------------------------------------------

   //--------------------------------------------------------------------

   //

   //

   // Control register

   // Control register

   reg             control_bit15; // self clearing bit

   reg             control_bit15; // self clearing bit

   reg [14:10]     control_bit14_10 = 5'b01000; // Init to 100MBPs (speed set)

   reg [14:10]     control_bit14_10 = 5'b01000; // Init to 100MBPs (speed set)

   reg             control_bit9; // self clearing bit

   reg             control_bit9; // self clearing bit

   reg [8:0]        control_bit8_0;

   reg [8:0]        control_bit8_0;

   // Status register

   // Status register

   wire [15:9]     status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;

   wire [15:9]     status_bit15_9 = `SUPPORTED_SPEED_AND_PORT;

   wire            status_bit8    = `EXTENDED_STATUS;

   wire            status_bit8    = `EXTENDED_STATUS;

   wire            status_bit7    = 1'b0; // reserved

   wire            status_bit7    = 1'b0; // reserved

   reg [6:0]        status_bit6_0;

   reg [6:0]        status_bit6_0;

   // PHY ID register 1

   // PHY ID register 1

   wire [15:0]      phy_id1        = `PHY_ID1;

   wire [15:0]      phy_id1        = `PHY_ID1;

   // PHY ID register 2

   // PHY ID register 2

   wire [15:0]      phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};

   wire [15:0]      phy_id2        = {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM};

   //--------------------------------------------------------------------

   //--------------------------------------------------------------------

   //

   //

   // Data MEMORY

   // Data MEMORY

   reg [15:0]       data_mem [0:31]; // 32 locations of 16-bit data width

   reg [15:0]       data_mem [0:31]; // 32 locations of 16-bit data width

   //

   //

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   //

   //

   // PHY clocks - RX & TX

   // PHY clocks - RX & TX

   //

   //

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   reg             mtx_clk_o;

   reg             mtx_clk_o;

   reg             mrx_clk_o;

   reg             mrx_clk_o;

   // random generator for a RX period when link is down

   // random generator for a RX period when link is down

   real            rx_link_down_halfperiod;

   real            rx_link_down_halfperiod;

   always@(status_bit6_0[2])

   always@(status_bit6_0[2])

     begin

     begin

        if (!status_bit6_0[2]) // Link is down

        if (!status_bit6_0[2]) // Link is down

          begin

          begin

             #1 rx_link_down_halfperiod = ({$random} % 243) + 13;

             #1 rx_link_down_halfperiod = ({$random} % 243) + 13;

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

             #1 $display( "(%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!",

             #1 $display( "(%0t)(%m)MAC RX clock is %f MHz while ethernet link is down!",

                          $time, (1000/(rx_link_down_halfperiod*2)) );

                          $time, (1000/(rx_link_down_halfperiod*2)) );

`endif

`endif

          end

          end

     end

     end

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

   always@(status_bit6_0[2])

   always@(status_bit6_0[2])

     begin

     begin

        if (!status_bit6_0[2]) // Link is down

        if (!status_bit6_0[2]) // Link is down

          #1 $display( "(%0t)(%m)Ethernet link is down!", $time);

          #1 $display( "(%0t)(%m)Ethernet link is down!", $time);

        else

        else

          #1 $display( "(%0t)(%m)Ethernet link is up!", $time);

          #1 $display( "(%0t)(%m)Ethernet link is up!", $time);

     end

     end

`endif

`endif

   // speed selection signal eth_speed: 1'b1 - 100 Mbps, 1'b0 - 10 Mbps

   // speed selection signal eth_speed: 1'b1 - 100 Mbps, 1'b0 - 10 Mbps

   wire      eth_speed;

   wire      eth_speed;

   assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );

   assign eth_speed = ( (control_bit14_10[13]) && !((`LED_CFG1) && (`LED_CFG2)) );

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

   always@(eth_speed)

   always@(eth_speed)

     begin

     begin

        if (eth_speed)

        if (eth_speed)

          #1 $display( "(%0t)(%m)PHY configured to 100 Mbps!", $time);

          #1 $display( "(%0t)(%m)PHY configured to 100 Mbps!", $time);

        else

        else

          #1 $display( "(%0t)(%m)PHY configured tp 10 Mbps!", $time);

          #1 $display( "(%0t)(%m)PHY configured tp 10 Mbps!", $time);

     end

     end

`endif

`endif

   // different clock calculation between RX and TX, so that there is alsways a litle difference

   // different clock calculation between RX and TX, so that there is alsways a litle difference

   /*initial

   /*initial

    begin

    begin

    set_mrx_equal_mtx = 1; // default

    set_mrx_equal_mtx = 1; // default

end*/

end*/

   always

   always

     begin

     begin

        mtx_clk_o = 0;

        mtx_clk_o = 0;

        #7;

        #7;

        forever

        forever

          begin

          begin

             if (eth_speed) // 100 Mbps - 25 MHz, 40 ns

             if (eth_speed) // 100 Mbps - 25 MHz, 40 ns

               begin

               begin

                  #20 mtx_clk_o = ~mtx_clk_o;

                  #20 mtx_clk_o = ~mtx_clk_o;

               end

               end

             else // 10 Mbps - 2.5 MHz, 400 ns

             else // 10 Mbps - 2.5 MHz, 400 ns

               begin

               begin

                  #200 mtx_clk_o = ~mtx_clk_o;

                  #200 mtx_clk_o = ~mtx_clk_o;

               end

               end

          end

          end

     end

     end

   always

   always

     begin

     begin

        // EQUAL mrx_clk to mtx_clk

        // EQUAL mrx_clk to mtx_clk

        mrx_clk_o = 0;

        mrx_clk_o = 0;

        #7;

        #7;

        forever

        forever

          begin

          begin

             if (eth_speed) // 100 Mbps - 25 MHz, 40 ns

             if (eth_speed) // 100 Mbps - 25 MHz, 40 ns

               begin

               begin

                  #20 mrx_clk_o = ~mrx_clk_o;

                  #20 mrx_clk_o = ~mrx_clk_o;

               end

               end

             else // 10 Mbps - 2.5 MHz, 400 ns

             else // 10 Mbps - 2.5 MHz, 400 ns

               begin

               begin

                  #200 mrx_clk_o = ~mrx_clk_o;

                  #200 mrx_clk_o = ~mrx_clk_o;

               end

               end

          end

          end

        // DIFFERENT mrx_clk than mtx_clk

        // DIFFERENT mrx_clk than mtx_clk

        /*  mrx_clk_diff_than_mtx = 1;

        /*  mrx_clk_diff_than_mtx = 1;

         #3;

         #3;

         forever

         forever

         begin

         begin

         if (status_bit6_0[2]) // Link is UP

         if (status_bit6_0[2]) // Link is UP

         begin

         begin

         if (eth_speed) // 100 Mbps - 25 MHz, 40 ns

         if (eth_speed) // 100 Mbps - 25 MHz, 40 ns

         begin

         begin

         //#(((1/0.025001)/2))

         //#(((1/0.025001)/2))

         #19.99 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz

         #19.99 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz

      end

      end

         else // 10 Mbps - 2.5 MHz, 400 ns

         else // 10 Mbps - 2.5 MHz, 400 ns

         begin

         begin

         //#(((1/0.0024999)/2))

         //#(((1/0.0024999)/2))

         #200.01 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz

         #200.01 mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // period is calculated from frequency in GHz

      end

      end

    end

    end

         else // Link is down

         else // Link is down

         begin

         begin

         #(rx_link_down_halfperiod) mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // random frequency between 2 MHz and 40 MHz

         #(rx_link_down_halfperiod) mrx_clk_diff_than_mtx = ~mrx_clk_diff_than_mtx; // random frequency between 2 MHz and 40 MHz

    end

    end

  end*/

  end*/

        //  // set output mrx_clk

        //  // set output mrx_clk

        //  if (set_mrx_equal_mtx)

        //  if (set_mrx_equal_mtx)

        //    mrx_clk_o = mrx_clk_equal_to_mtx;

        //    mrx_clk_o = mrx_clk_equal_to_mtx;

        //  else

        //  else

        //    mrx_clk_o = mrx_clk_diff_than_mtx;

        //    mrx_clk_o = mrx_clk_diff_than_mtx;

     end

     end

   // set output mrx_clk

   // set output mrx_clk

   //assign mrx_clk_o = set_mrx_equal_mtx ? mrx_clk_equal_to_mtx : mrx_clk_diff_than_mtx ;

   //assign mrx_clk_o = set_mrx_equal_mtx ? mrx_clk_equal_to_mtx : mrx_clk_diff_than_mtx ;

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   //

   //

   // PHY management (MIIM) interface

   // PHY management (MIIM) interface

   //

   //

   //////////////////////////////////////////////////////////////////////

   //////////////////////////////////////////////////////////////////////

   reg             respond_to_all_phy_addr; // PHY will respond to all phy addresses

   reg             respond_to_all_phy_addr; // PHY will respond to all phy addresses

   reg             no_preamble; // PHY responds to frames without preamble

   reg             no_preamble; // PHY responds to frames without preamble

   integer         md_transfer_cnt; // counter countes the value of whole data transfer

   integer         md_transfer_cnt; // counter countes the value of whole data transfer

   reg             md_transfer_cnt_reset; // for reseting the counter

   reg             md_transfer_cnt_reset; // for reseting the counter

   reg             md_io_reg; // registered input

   reg             md_io_reg; // registered input

   reg             md_io_output; // registered output

   reg             md_io_output; // registered output

   reg             md_io_rd_wr;  // op-code latched (read or write)

   reg             md_io_rd_wr;  // op-code latched (read or write)

   reg             md_io_enable; // output enable

   reg             md_io_enable; // output enable

   reg [4:0]        phy_address; // address of PHY device

   reg [4:0]        phy_address; // address of PHY device

   reg [4:0]        reg_address; // address of a register

   reg [4:0]        reg_address; // address of a register

   reg             md_get_phy_address; // for shifting PHY address in

   reg             md_get_phy_address; // for shifting PHY address in

   reg             md_get_reg_address; // for shifting register address in

   reg             md_get_reg_address; // for shifting register address in

   reg [15:0]       reg_data_in; // data to be written in a register

   reg [15:0]       reg_data_in; // data to be written in a register

   reg             md_get_reg_data_in; // for shifting data in

   reg             md_get_reg_data_in; // for shifting data in

   reg             md_put_reg_data_in; // for storing data into a selected register

   reg             md_put_reg_data_in; // for storing data into a selected register

   reg [15:0]       reg_data_out; // data to be read from a register

   reg [15:0]       reg_data_out; // data to be read from a register

   reg             md_put_reg_data_out; // for registering data from a selected register

   reg             md_put_reg_data_out; // for registering data from a selected register

   wire [15:0]      register_bus_in; // data bus to a selected register

   wire [15:0]      register_bus_in; // data bus to a selected register

   reg [15:0]       register_bus_out; // data bus from a selected register

   reg [15:0]       register_bus_out; // data bus from a selected register

   initial

   initial

     begin

     begin

        md_io_enable = 1'b0;

        md_io_enable = 1'b0;

        respond_to_all_phy_addr = 1'b0;

        respond_to_all_phy_addr = 1'b0;

        no_preamble = 1'b0;

        no_preamble = 1'b0;

     end

     end

   // tristate output

   // tristate output

   assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ;

   assign #1 md_io = (m_rst_n_i && md_io_enable) ? md_io_output : 1'bz ;

   // registering input

   // registering input

   always@(posedge mdc_i or negedge m_rst_n_i)

   always@(posedge mdc_i or negedge m_rst_n_i)

     begin

     begin

        if (!m_rst_n_i)

        if (!m_rst_n_i)

          md_io_reg <= #1 0;

          md_io_reg <= #1 0;

        else

        else

          md_io_reg <= #1 md_io;

          md_io_reg <= #1 md_io;

     end

     end

   // getting (shifting) PHY address, Register address and Data in

   // getting (shifting) PHY address, Register address and Data in

   // putting Data out and shifting

   // putting Data out and shifting

   always@(posedge mdc_i or negedge m_rst_n_i)

   always@(posedge mdc_i or negedge m_rst_n_i)

     begin

     begin

        if (!m_rst_n_i)

        if (!m_rst_n_i)

          begin

          begin

             phy_address <= 0;

             phy_address <= 0;

             reg_address <= 0;

             reg_address <= 0;

             reg_data_in <= 0;

             reg_data_in <= 0;

             reg_data_out <= 0;

             reg_data_out <= 0;

             md_io_output <= 0;

             md_io_output <= 0;

          end

          end

        else

        else

          begin

          begin

             if (md_get_phy_address)

             if (md_get_phy_address)

               begin

               begin

                  phy_address[4:1] <= phy_address[3:0]; // correct address is `ETH_PHY_ADDR

                  phy_address[4:1] <= phy_address[3:0]; // correct address is `ETH_PHY_ADDR

                  phy_address[0]   <= md_io;

                  phy_address[0]   <= md_io;

               end

               end

             if (md_get_reg_address)

             if (md_get_reg_address)

               begin

               begin

                  reg_address[4:1] <= reg_address[3:0];

                  reg_address[4:1] <= reg_address[3:0];

                  reg_address[0]   <= md_io;

                  reg_address[0]   <= md_io;

               end

               end

             if (md_get_reg_data_in)

             if (md_get_reg_data_in)

               begin

               begin

                  reg_data_in[15:1] <= reg_data_in[14:0];

                  reg_data_in[15:1] <= reg_data_in[14:0];

                  reg_data_in[0]    <= md_io;

                  reg_data_in[0]    <= md_io;

               end

               end

             if (md_put_reg_data_out)

             if (md_put_reg_data_out)

               begin

               begin

                  reg_data_out <= register_bus_out;

                  reg_data_out <= register_bus_out;

               end

               end

             if (md_io_enable)

             if (md_io_enable)

               begin

               begin

                  md_io_output       <= reg_data_out[15];

                  md_io_output       <= reg_data_out[15];

                  reg_data_out[15:1] <= reg_data_out[14:0];

                  reg_data_out[15:1] <= reg_data_out[14:0];

                  reg_data_out[0]    <= 1'b0;

                  reg_data_out[0]    <= 1'b0;

               end

               end

          end

          end

     end

     end

   assign #1 register_bus_in = reg_data_in; // md_put_reg_data_in - allows writing to a selected register

   assign #1 register_bus_in = reg_data_in; // md_put_reg_data_in - allows writing to a selected register

   // counter for transfer to and from MIIM

   // counter for transfer to and from MIIM

   always@(posedge mdc_i or negedge m_rst_n_i)

   always@(posedge mdc_i or negedge m_rst_n_i)

     begin

     begin

        if (!m_rst_n_i)

        if (!m_rst_n_i)

          begin

          begin

             if (no_preamble)

             if (no_preamble)

               md_transfer_cnt <= 33;

               md_transfer_cnt <= 33;

             else

             else

               md_transfer_cnt <= 1;

               md_transfer_cnt <= 1;

          end

          end

        else

        else

          begin

          begin

             if (md_transfer_cnt_reset)

             if (md_transfer_cnt_reset)

               begin

               begin

                  if (no_preamble)

                  if (no_preamble)

                    md_transfer_cnt <= 33;

                    md_transfer_cnt <= 33;

                  else

                  else

                    md_transfer_cnt <= 1;

                    md_transfer_cnt <= 1;

               end

               end

             else if (md_transfer_cnt < 64)

             else if (md_transfer_cnt < 64)

               begin

               begin

                  md_transfer_cnt <= md_transfer_cnt + 1'b1;

                  md_transfer_cnt <= md_transfer_cnt + 1'b1;

               end

               end

             else

             else

               begin

               begin

                  if (no_preamble)

                  if (no_preamble)

                    md_transfer_cnt <= 33;

                    md_transfer_cnt <= 33;

                  else

                  else

                    md_transfer_cnt <= 1;

                    md_transfer_cnt <= 1;

               end

               end

          end

          end

     end

     end

   // MIIM transfer control

   // MIIM transfer control

   always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or

   always@(m_rst_n_i or md_transfer_cnt or md_io_reg or md_io_rd_wr or

           phy_address or respond_to_all_phy_addr or no_preamble)

           phy_address or respond_to_all_phy_addr or no_preamble)

     begin

     begin

        #1;

        #1;

        while ((m_rst_n_i) && (md_transfer_cnt <= 64))

        while ((m_rst_n_i) && (md_transfer_cnt <= 64))

          begin

          begin

             // reset the signal - put registered data in the register (when write)

             // reset the signal - put registered data in the register (when write)

             // check preamble

             // check preamble

             if (md_transfer_cnt < 33)

             if (md_transfer_cnt < 33)

               begin

               begin

                  #4 md_put_reg_data_in = 1'b0;

                  #4 md_put_reg_data_in = 1'b0;

                  if (md_io_reg !== 1'b1)

                  if (md_io_reg !== 1'b1)

                    begin

                    begin

                       #1 md_transfer_cnt_reset = 1'b1;

                       #1 md_transfer_cnt_reset = 1'b1;

                    end

                    end

                  else

                  else

                    begin

                    begin

                       #1 md_transfer_cnt_reset = 1'b0;

                       #1 md_transfer_cnt_reset = 1'b0;

                    end

                    end

               end

               end

             // check start bits

             // check start bits

             else if (md_transfer_cnt == 33)

             else if (md_transfer_cnt == 33)

               begin

               begin

                  if (no_preamble)

                  if (no_preamble)

                    begin

                    begin

                       #4 md_put_reg_data_in = 1'b0;

                       #4 md_put_reg_data_in = 1'b0;

                       if (md_io_reg === 1'b0)

                       if (md_io_reg === 1'b0)

                         begin

                         begin

                            #1 md_transfer_cnt_reset = 1'b0;

                            #1 md_transfer_cnt_reset = 1'b0;

                         end

                         end

                       else

                       else

                         begin

                         begin

                            #1 md_transfer_cnt_reset = 1'b1;

                            #1 md_transfer_cnt_reset = 1'b1;

                            //if ((md_io_reg !== 1'bz) && (md_io_reg !== 1'b1))

                            //if ((md_io_reg !== 1'bz) && (md_io_reg !== 1'b1))

                            if (md_io_reg !== 1'bz)

                            if (md_io_reg !== 1'bz)

                              begin

                              begin

                                 // ERROR - start !

                                 // ERROR - start !

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                                 $display( "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time);

                                 $display( "*E (%0t)(%m)MIIM - wrong first start bit (without preamble)", $time);

`endif

`endif

                                 #10 $stop;

                                 #10 $stop;

                              end

                              end

                         end

                         end

                    end

                    end

                  else // with preamble

                  else // with preamble

                    begin

                    begin

                       #4 ;

                       #4 ;

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                       $display( "(%0t)(%m)MIIM - 32-bit preamble received", $time);

                       $display( "(%0t)(%m)MIIM - 32-bit preamble received", $time);

`endif

`endif

                       // check start bit only if md_transfer_cnt_reset is inactive, because if

                       // check start bit only if md_transfer_cnt_reset is inactive, because if

                       // preamble suppression was changed start bit should not be checked

                       // preamble suppression was changed start bit should not be checked

                       if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))

                       if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))

                         begin

                         begin

                            // ERROR - start !

                            // ERROR - start !

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                            $display( "*E (%0t)(%m)MIIM - wrong first start bit", $time);

                            $display( "*E (%0t)(%m)MIIM - wrong first start bit", $time);

`endif

`endif

                            #10 $stop;

                            #10 $stop;

                         end

                         end

                    end

                    end

               end

               end

             else if (md_transfer_cnt == 34)

             else if (md_transfer_cnt == 34)

               begin

               begin

                  #4;

                  #4;

                  if (md_io_reg !== 1'b1)

                  if (md_io_reg !== 1'b1)

                    begin

                    begin

                       // ERROR - start !

                       // ERROR - start !

                       #1;

                       #1;

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                       if (no_preamble)

                       if (no_preamble)

                         $display( "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time);

                         $display( "*E (%0t)(%m)MIIM - wrong second start bit (without preamble)", $time);

                       else

                       else

                         $display( "*E (%0t)(%m)MIIM - wrong second start bit", $time);

                         $display( "*E (%0t)(%m)MIIM - wrong second start bit", $time);

`endif

`endif

                       #10 $stop;

                       #10 $stop;

                    end

                    end

                  else

                  else

                    begin

                    begin

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                       if (no_preamble)

                       if (no_preamble)

                         #1 $display( "(%0t)(%m)MIIM - 2 start bits received (without preamble)", $time);

                         #1 $display( "(%0t)(%m)MIIM - 2 start bits received (without preamble)", $time);

                       else

                       else

                         #1 $display( "(%0t)(%m)MIIM - 2 start bits received", $time);

                         #1 $display( "(%0t)(%m)MIIM - 2 start bits received", $time);

`endif

`endif

                    end

                    end

               end

               end

             // register the op-code (rd / wr)

             // register the op-code (rd / wr)

             else if (md_transfer_cnt == 35)

             else if (md_transfer_cnt == 35)

               begin

               begin

                  #4;

                  #4;

                  if (md_io_reg === 1'b1)

                  if (md_io_reg === 1'b1)

                    begin

                    begin

                       #1 md_io_rd_wr = 1'b1;

                       #1 md_io_rd_wr = 1'b1;

                    end

                    end

                  else

                  else

                    begin

                    begin

                       #1 md_io_rd_wr = 1'b0;

                       #1 md_io_rd_wr = 1'b0;

                    end

                    end

               end

               end

             else if (md_transfer_cnt == 36)

             else if (md_transfer_cnt == 36)

               begin

               begin

                  #4;

                  #4;

                  if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1))

                  if ((md_io_reg === 1'b0) && (md_io_rd_wr == 1'b1))

                    begin

                    begin

                       #1 md_io_rd_wr = 1'b1; // reading from PHY registers

                       #1 md_io_rd_wr = 1'b1; // reading from PHY registers

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                       $display( "(%0t)(%m)MIIM - op-code for READING from registers", $time);

                       $display( "(%0t)(%m)MIIM - op-code for READING from registers", $time);

`endif

`endif

                    end

                    end

                  else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0))

                  else if ((md_io_reg === 1'b1) && (md_io_rd_wr == 1'b0))

                    begin

                    begin

                       #1 md_io_rd_wr = 1'b0; // writing to PHY registers

                       #1 md_io_rd_wr = 1'b0; // writing to PHY registers

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                       $display( "(%0t)(%m)MIIM - op-code for WRITING to registers", $time);

                       $display( "(%0t)(%m)MIIM - op-code for WRITING to registers", $time);

`endif

`endif

                    end

                    end

                  else

                  else

                    begin

                    begin

                       // ERROR - wrong opcode !

                       // ERROR - wrong opcode !

`ifdef ETH_PHY_VERBOSE

`ifdef ETH_PHY_VERBOSE

                       #1 $display( "*E (%0t)(%m)MIIM - wrong OP-CODE", $time);

                       #1 $display( "*E (%0t)(%m)MIIM - wrong OP-CODE", $time);

`endif

`endif

                       #10 $stop;

                       #10 $stop;

                    end

                    end

                  // set the signal - get PHY address

                  // set the signal - get PHY address

                  begin

                  begin

                     #1 md_get_phy_address = 1'b1;

                     #1 md_get_phy_address = 1'b1;

                  end

                  end

               end

               end

             // reset the signal - get PHY address

             // reset the signal - get PHY address

             else if (md_transfer_cnt == 41)

             else if (md_transfer_cnt == 41)

               begin

               begin

                  #4 md_get_phy_address = 1'b0;

                  #4 md_get_phy_address = 1'b0;