//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// or1200_monitor ////
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//// or1200_monitor ////
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//// ////
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//// ////
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//// OR1200 processor monitor module ////
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//// OR1200 processor monitor module ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "test-defines.v"
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`include "test-defines.v"
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|
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//
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`define OR1200_TOP orpsoc_testbench.dut.or1200_top
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`define OR1200_TOP orpsoc_testbench.dut.or1200_top0
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|
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//
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//
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// Define to enable lookup file generation
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// Define to enable lookup file generation
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//
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//
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//`define OR1200_MONITOR_LOOKUP
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//`define OR1200_MONITOR_LOOKUP
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|
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//
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//
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// Define to enable SPR access log file generation
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// Define to enable SPR access log file generation
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//
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//
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//`define OR1200_MONITOR_SPRS
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//`define OR1200_MONITOR_SPRS
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|
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//
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//
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// Enable logging of state during execution
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// Enable logging of state during execution
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//
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//
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//`define OR1200_MONITOR_EXEC_STATE
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//`define OR1200_MONITOR_EXEC_STATE
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|
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//
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//
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// Enable disassembly of instructions in execution state log
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// Enable disassembly of instructions in execution state log
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//
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//
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//`define OR1200_MONITOR_PRINT_DISASSEMBLY
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//`define OR1200_MONITOR_PRINT_DISASSEMBLY
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|
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// Can either individually enable things above, or usually have the scripts
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// Can either individually enable things above, or usually have the scripts
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// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
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// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
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// enable them all.
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// enable them all.
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|
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`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
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`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
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`define OR1200_MONITOR_EXEC_STATE
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`define OR1200_MONITOR_EXEC_STATE
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`define OR1200_MONITOR_SPRS
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`define OR1200_MONITOR_SPRS
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`define OR1200_MONITOR_LOOKUP
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`define OR1200_MONITOR_LOOKUP
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`endif
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`endif
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|
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//
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`define CPU or1200
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`define CPU or1200
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`define CPU_cpu or1200_cpu
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`define CPU_cpu or1200_cpu
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`define CPU_rf or1200_rf
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`define CPU_rf or1200_rf
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`define CPU_except or1200_except
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`define CPU_except or1200_except
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`define CPU_ctrl or1200_ctrl
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`define CPU_ctrl or1200_ctrl
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`define CPU_sprs or1200_sprs
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`define CPU_sprs or1200_sprs
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module or1200_monitor;
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module or1200_monitor;
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integer fexe;
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integer fexe;
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reg [23:0] ref;
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reg [23:0] ref;
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`ifdef OR1200_MONITOR_SPRS
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`ifdef OR1200_MONITOR_SPRS
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integer fspr;
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integer fspr;
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`endif
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`endif
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integer fgeneral;
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integer fgeneral;
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`ifdef OR1200_MONITOR_LOOKUP
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`ifdef OR1200_MONITOR_LOOKUP
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integer flookup;
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integer flookup;
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`endif
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`endif
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integer r3;
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integer r3;
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integer insns;
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integer insns;
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|
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//
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//
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// Initialization
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// Initialization
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//
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//
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initial begin
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initial begin
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ref = 0;
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ref = 0;
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`ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_MONITOR_EXEC_STATE
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fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
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fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
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`endif
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`endif
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$timeformat (-9, 2, " ns", 12);
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$timeformat (-9, 2, " ns", 12);
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`ifdef OR1200_MONITOR_SPRS
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`ifdef OR1200_MONITOR_SPRS
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fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
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fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
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`endif
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`endif
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fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
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fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
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`ifdef OR1200_MONITOR_LOOKUP
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`ifdef OR1200_MONITOR_LOOKUP
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flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
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flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
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`endif
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`endif
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insns = 0;
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insns = 0;
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|
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end
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end
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//
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//
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// Get GPR
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// Get GPR
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//
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//
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task get_gpr;
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task get_gpr;
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input [4:0] gpr_no;
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input [4:0] gpr_no;
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output [31:0] gpr;
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output [31:0] gpr;
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integer j;
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integer j;
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begin
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begin
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|
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`ifdef OR1200_RFRAM_GENERIC
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`ifdef OR1200_RFRAM_GENERIC
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for(j = 0; j < 32; j = j + 1) begin
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for(j = 0; j < 32; j = j + 1) begin
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gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
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gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
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end
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end
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`else
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`else
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//gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
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//gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
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gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
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gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
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|
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`endif
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`endif
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|
|
|
|
end
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end
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endtask
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endtask
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|
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//
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//
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// Write state of the OR1200 registers into a file
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// Write state of the OR1200 registers into a file
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//
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//
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// Limitation: only a small subset of register file RAMs
|
// Limitation: only a small subset of register file RAMs
|
// are supported
|
// are supported
|
//
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//
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task display_arch_state;
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task display_arch_state;
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reg [5:0] i;
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reg [5:0] i;
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reg [31:0] r;
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reg [31:0] r;
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integer j;
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integer j;
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begin
|
begin
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`ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_MONITOR_EXEC_STATE
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ref = ref + 1;
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ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
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`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns,
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`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`ifdef OR1200_MONITOR_PRINT_DISASSEMBLY
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`ifdef OR1200_MONITOR_PRINT_DISASSEMBLY
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$fwrite(fexe,"\t");
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$fwrite(fexe,"\t");
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// Decode the instruction, print it out
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// Decode the instruction, print it out
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or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`endif
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`endif
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for(i = 0; i < 32; i = i + 1) begin
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for(i = 0; i < 32; i = i + 1) begin
|
if (i % 4 == 0)
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if (i % 4 == 0)
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$fdisplay(fexe);
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$fdisplay(fexe);
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get_gpr(i, r);
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get_gpr(i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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end
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end
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$fdisplay(fexe);
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$fdisplay(fexe);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
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$fwrite(fexe, "SR : %h ", r);
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$fwrite(fexe, "SR : %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
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$fwrite(fexe, "EPCR0: %h ", r);
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$fwrite(fexe, "EPCR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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$fwrite(fexe, "EEAR0: %h ", r);
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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$fdisplay(fexe, "ESR0 : %h", r);
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`endif // `ifdef OR1200_MONITOR_EXEC_STATE
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`ifdef OR1200_DISPLAY_EXECUTED
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`ifdef OR1200_DISPLAY_EXECUTED
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ref = ref + 1;
|
ref = ref + 1;
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`ifdef OR1200_MONITOR_LOOKUP
|
`ifdef OR1200_MONITOR_LOOKUP
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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$fdisplay(flookup, "Instruction %d: %t", insns, $time);
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`endif
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`endif
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
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`endif
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`endif
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insns = insns + 1;
|
insns = insns + 1;
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end
|
end
|
endtask // display_arch_state
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endtask // display_arch_state
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|
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/* Keep a trace buffer of the last lot of instructions and addresses
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/* Keep a trace buffer of the last lot of instructions and addresses
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* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
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* an instruction that is invalid, such as all zeros.
|
* an instruction that is invalid, such as all zeros.
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* made to break for anything with an X in it too. And of course ideally this
|
* made to break for anything with an X in it too. And of course ideally this
|
* shouldn't be needed - but is handy if someone changes something and stops
|
* shouldn't be needed - but is handy if someone changes something and stops
|
* the test continuing forever.
|
* the test continuing forever.
|
*/
|
*/
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integer num_nul_inst;
|
integer num_nul_inst;
|
initial num_nul_inst = 0;
|
initial num_nul_inst = 0;
|
|
|
task monitor_for_crash;
|
task monitor_for_crash;
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
//Trace buffer of 32 instructions
|
//Trace buffer of 32 instructions
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reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
|
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
|
//Trace buffer of the addresses of those instructions
|
//Trace buffer of the addresses of those instructions
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
|
num_nul_inst = num_nul_inst + 1;
|
num_nul_inst = num_nul_inst + 1;
|
else
|
else
|
num_nul_inst = 0; // Reset it
|
num_nul_inst = 0; // Reset it
|
|
|
if (num_nul_inst == 1000) // Sat a loop a bit too long...
|
if (num_nul_inst == 1000) // Sat a loop a bit too long...
|
begin
|
begin
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h",
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h",
|
`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
|
`OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
|
`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
|
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
end
|
end
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
insn_trace[i] = insn_trace[i-1];
|
insn_trace[i] = insn_trace[i-1];
|
addr_trace[i] = addr_trace[i-1];
|
addr_trace[i] = addr_trace[i-1];
|
end
|
end
|
insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
|
insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
|
addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
|
addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
|
end
|
end
|
|
|
end
|
end
|
endtask // monitor_for_crash
|
endtask // monitor_for_crash
|
|
|
|
|
//
|
//
|
// Write state of the OR1200 registers into a file; version for exception
|
// Write state of the OR1200 registers into a file; version for exception
|
//
|
//
|
task display_arch_state_except;
|
task display_arch_state_except;
|
reg [5:0] i;
|
reg [5:0] i;
|
reg [31:0] r;
|
reg [31:0] r;
|
integer j;
|
integer j;
|
begin
|
begin
|
`ifdef OR1200_MONITOR_EXEC_STATE
|
`ifdef OR1200_MONITOR_EXEC_STATE
|
ref = ref + 1;
|
ref = ref + 1;
|
`ifdef OR1200_MONITOR_LOOKUP
|
`ifdef OR1200_MONITOR_LOOKUP
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
`endif
|
`endif
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
|
for(i = 0; i < 32; i = i + 1) begin
|
for(i = 0; i < 32; i = i + 1) begin
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
$fdisplay(fexe);
|
$fdisplay(fexe);
|
get_gpr(i, r);
|
get_gpr(i, r);
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
end
|
end
|
$fdisplay(fexe);
|
$fdisplay(fexe);
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
|
$fwrite(fexe, "SR : %h ", r);
|
$fwrite(fexe, "SR : %h ", r);
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
|
$fwrite(fexe, "EPCR0: %h ", r);
|
$fwrite(fexe, "EPCR0: %h ", r);
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
|
$fwrite(fexe, "EEAR0: %h ", r);
|
$fwrite(fexe, "EEAR0: %h ", r);
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
|
r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
|
$fdisplay(fexe, "ESR0 : %h", r);
|
$fdisplay(fexe, "ESR0 : %h", r);
|
insns = insns + 1;
|
insns = insns + 1;
|
`endif // `ifdef OR1200_MONITOR_EXEC_STATE
|
`endif // `ifdef OR1200_MONITOR_EXEC_STATE
|
`ifdef OR1200_DISPLAY_EXECUTED
|
`ifdef OR1200_DISPLAY_EXECUTED
|
ref = ref + 1;
|
ref = ref + 1;
|
`ifdef OR1200_MONITOR_LOOKUP
|
`ifdef OR1200_MONITOR_LOOKUP
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
`endif
|
`endif
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns,
|
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
|
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
|
`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
|
`OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
|
insns = insns + 1;
|
insns = insns + 1;
|
`endif
|
`endif
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
integer iwb_progress;
|
integer iwb_progress;
|
reg [31:0] iwb_progress_addr;
|
reg [31:0] iwb_progress_addr;
|
//
|
//
|
// WISHBONE bus checker
|
// WISHBONE bus checker
|
//
|
//
|
always @(posedge `OR1200_TOP.iwb_clk_i)
|
always @(posedge `OR1200_TOP.iwb_clk_i)
|
if (`OR1200_TOP.iwb_rst_i) begin
|
if (`OR1200_TOP.iwb_rst_i) begin
|
iwb_progress = 0;
|
iwb_progress = 0;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
end
|
end
|
else begin
|
else begin
|
if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
|
if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
|
iwb_progress = 1;
|
iwb_progress = 1;
|
end
|
end
|
if (`OR1200_TOP.iwb_stb_o) begin
|
if (`OR1200_TOP.iwb_stb_o) begin
|
if (iwb_progress >= 1) begin
|
if (iwb_progress >= 1) begin
|
if (iwb_progress == 1)
|
if (iwb_progress == 1)
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress = 2;
|
iwb_progress = 2;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
end
|
end
|
if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
|
if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
|
end
|
end
|
if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
|
if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
|
if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
|
if (iwb_progress == 2) begin
|
if (iwb_progress == 2) begin
|
iwb_progress = 0;
|
iwb_progress = 0;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
|
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
end
|
end
|
|
|
integer dwb_progress;
|
integer dwb_progress;
|
reg [31:0] dwb_progress_addr;
|
reg [31:0] dwb_progress_addr;
|
//
|
//
|
// WISHBONE bus checker
|
// WISHBONE bus checker
|
//
|
//
|
always @(posedge `OR1200_TOP.dwb_clk_i)
|
always @(posedge `OR1200_TOP.dwb_clk_i)
|
if (`OR1200_TOP.dwb_rst_i)
|
if (`OR1200_TOP.dwb_rst_i)
|
dwb_progress = 0;
|
dwb_progress = 0;
|
else begin
|
else begin
|
if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
|
if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
|
dwb_progress = 1;
|
dwb_progress = 1;
|
if (`OR1200_TOP.dwb_stb_o)
|
if (`OR1200_TOP.dwb_stb_o)
|
if (dwb_progress >= 1) begin
|
if (dwb_progress >= 1) begin
|
if (dwb_progress == 1)
|
if (dwb_progress == 1)
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
dwb_progress = 2;
|
dwb_progress = 2;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
|
if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
|
end
|
end
|
if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
|
if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
|
if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
|
if (dwb_progress == 2) begin
|
if (dwb_progress == 2) begin
|
dwb_progress = 0;
|
dwb_progress = 0;
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
|
if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Hooks for:
|
// Hooks for:
|
// - displaying registers
|
// - displaying registers
|
// - end of simulation
|
// - end of simulation
|
// - access to SPRs
|
// - access to SPRs
|
//
|
//
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
|
if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
|
// #2;
|
// #2;
|
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
|
if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
|
| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
|
| !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
|
& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
|
& !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
|
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
|
`OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
|
begin
|
begin
|
display_arch_state;
|
display_arch_state;
|
monitor_for_crash;
|
monitor_for_crash;
|
end
|
end
|
else
|
else
|
if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
|
display_arch_state_except;
|
display_arch_state_except;
|
// small hack to stop simulation (l.nop 1):
|
// small hack to stop simulation (l.nop 1):
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
|
$finish;
|
$finish;
|
end
|
end
|
// debug if test (l.nop 10)
|
// debug if test (l.nop 10)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
|
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
|
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
|
end
|
end
|
// simulation reports (l.nop 2)
|
// simulation reports (l.nop 2)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
|
end
|
end
|
// simulation printfs (l.nop 3)
|
// simulation printfs (l.nop 3)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
|
end
|
end
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
|
if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
|
// simulation putc (l.nop 4)
|
// simulation putc (l.nop 4)
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$write("%c", r3);
|
$write("%c", r3);
|
$fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
|
end
|
end
|
`ifdef OR1200_MONITOR_SPRS
|
`ifdef OR1200_MONITOR_SPRS
|
if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
|
if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
|
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
|
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
|
if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
|
if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
|
!`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
|
!`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
|
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
|
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
|
`OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
|
`endif
|
`endif
|
end
|
end
|
|
|
|
|
`ifdef VERSATILE_SDRAM
|
`ifdef VERSATILE_SDRAM
|
`define SDRAM_TOP design_testbench.sdram0
|
`define SDRAM_TOP orpsoc_testbench.sdram0
|
// Bit selects to define the bank
|
// Bit selects to define the bank
|
// 32 MB part with 4 banks
|
// 32 MB part with 4 banks
|
`define SDRAM_BANK_SEL_BITS 24:23
|
`define SDRAM_BANK_SEL_BITS 24:23
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
`define SDRAM_WORD_SEL_TOP_BIT 22
|
// Gets instruction word from correct bank
|
// Gets instruction word from correct bank
|
task get_insn_from_sdram;
|
task get_insn_from_sdram;
|
input [31:0] addr;
|
input [31:0] addr;
|
output [31:0] insn;
|
output [31:0] insn;
|
reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
|
reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
|
|
|
begin
|
begin
|
word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
|
word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
|
if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
|
if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
|
begin
|
begin
|
|
|
//$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
|
//$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
|
insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
|
insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
|
insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
|
insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
|
end
|
end
|
end
|
end
|
|
|
endtask // get_insn_from_sdram
|
endtask // get_insn_from_sdram
|
`endif // `ifdef VERSATILE_SDRAM
|
`endif // `ifdef VERSATILE_SDRAM
|
|
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
`define DDR2_TOP design_testbench.gen_cs[0]
|
`define DDR2_TOP orpsoc_testbench.gen_cs[0]
|
// Gets instruction word from correct bank
|
// Gets instruction word from correct bank
|
task get_insn_from_xilinx_ddr2;
|
task get_insn_from_xilinx_ddr2;
|
input [31:0] addr;
|
input [31:0] addr;
|
output [31:0] insn;
|
output [31:0] insn;
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
|
reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,ddr2_array_line3;
|
integer word_in_line_num;
|
integer word_in_line_num;
|
begin
|
begin
|
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 16 words total
|
// Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 16 words total
|
`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
|
`DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
|
`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
|
`DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
|
`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
|
`DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
|
`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
|
`DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
|
case (addr[5:2])
|
case (addr[5:2])
|
4'h0:
|
4'h0:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[15:0];
|
insn[15:0] = ddr2_array_line0[15:0];
|
insn[31:16] = ddr2_array_line1[15:0];
|
insn[31:16] = ddr2_array_line1[15:0];
|
end
|
end
|
4'h1:
|
4'h1:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[15:0];
|
insn[15:0] = ddr2_array_line2[15:0];
|
insn[31:16] = ddr2_array_line3[15:0];
|
insn[31:16] = ddr2_array_line3[15:0];
|
end
|
end
|
4'h2:
|
4'h2:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[31:16];
|
insn[15:0] = ddr2_array_line0[31:16];
|
insn[31:16] = ddr2_array_line1[31:16];
|
insn[31:16] = ddr2_array_line1[31:16];
|
end
|
end
|
4'h3:
|
4'h3:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[31:16];
|
insn[15:0] = ddr2_array_line2[31:16];
|
insn[31:16] = ddr2_array_line3[31:16];
|
insn[31:16] = ddr2_array_line3[31:16];
|
end
|
end
|
4'h4:
|
4'h4:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[47:32];
|
insn[15:0] = ddr2_array_line0[47:32];
|
insn[31:16] = ddr2_array_line1[47:32];
|
insn[31:16] = ddr2_array_line1[47:32];
|
end
|
end
|
4'h5:
|
4'h5:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[47:32];
|
insn[15:0] = ddr2_array_line2[47:32];
|
insn[31:16] = ddr2_array_line3[47:32];
|
insn[31:16] = ddr2_array_line3[47:32];
|
end
|
end
|
4'h6:
|
4'h6:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[63:48];
|
insn[15:0] = ddr2_array_line0[63:48];
|
insn[31:16] = ddr2_array_line1[63:48];
|
insn[31:16] = ddr2_array_line1[63:48];
|
end
|
end
|
4'h7:
|
4'h7:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[63:48];
|
insn[15:0] = ddr2_array_line2[63:48];
|
insn[31:16] = ddr2_array_line3[63:48];
|
insn[31:16] = ddr2_array_line3[63:48];
|
end
|
end
|
4'h8:
|
4'h8:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[79:64];
|
insn[15:0] = ddr2_array_line0[79:64];
|
insn[31:16] = ddr2_array_line1[79:64];
|
insn[31:16] = ddr2_array_line1[79:64];
|
end
|
end
|
4'h9:
|
4'h9:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[79:64];
|
insn[15:0] = ddr2_array_line2[79:64];
|
insn[31:16] = ddr2_array_line3[79:64];
|
insn[31:16] = ddr2_array_line3[79:64];
|
end
|
end
|
4'ha:
|
4'ha:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[95:80];
|
insn[15:0] = ddr2_array_line0[95:80];
|
insn[31:16] = ddr2_array_line1[95:80];
|
insn[31:16] = ddr2_array_line1[95:80];
|
end
|
end
|
4'hb:
|
4'hb:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[95:80];
|
insn[15:0] = ddr2_array_line2[95:80];
|
insn[31:16] = ddr2_array_line3[95:80];
|
insn[31:16] = ddr2_array_line3[95:80];
|
end
|
end
|
4'hc:
|
4'hc:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[111:96];
|
insn[15:0] = ddr2_array_line0[111:96];
|
insn[31:16] = ddr2_array_line1[111:96];
|
insn[31:16] = ddr2_array_line1[111:96];
|
end
|
end
|
4'hd:
|
4'hd:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[111:96];
|
insn[15:0] = ddr2_array_line2[111:96];
|
insn[31:16] = ddr2_array_line3[111:96];
|
insn[31:16] = ddr2_array_line3[111:96];
|
end
|
end
|
4'he:
|
4'he:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line0[127:112];
|
insn[15:0] = ddr2_array_line0[127:112];
|
insn[31:16] = ddr2_array_line1[127:112];
|
insn[31:16] = ddr2_array_line1[127:112];
|
end
|
end
|
4'hf:
|
4'hf:
|
begin
|
begin
|
insn[15:0] = ddr2_array_line2[127:112];
|
insn[15:0] = ddr2_array_line2[127:112];
|
insn[31:16] = ddr2_array_line3[127:112];
|
insn[31:16] = ddr2_array_line3[127:112];
|
end
|
end
|
endcase // case (addr[5:2])
|
endcase // case (addr[5:2])
|
end
|
end
|
endtask // get_insn_from_xilinx_ddr2
|
endtask // get_insn_from_xilinx_ddr2
|
`endif
|
`endif
|
|
|
|
|
task get_insn_from_memory;
|
task get_insn_from_memory;
|
input [31:0] id_pc;
|
input [31:0] id_pc;
|
output [31:0] insn;
|
output [31:0] insn;
|
begin
|
begin
|
// do a decode of which server we should look in
|
// do a decode of which server we should look in
|
case (id_pc[31:28])
|
case (id_pc[31:28])
|
`ifdef VERSATILE_SDRAM
|
`ifdef VERSATILE_SDRAM
|
4'h0:
|
4'h0:
|
get_insn_from_sdram(id_pc, insn);
|
get_insn_from_sdram(id_pc, insn);
|
`endif
|
`endif
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
4'h0:
|
4'h0:
|
get_insn_from_xilinx_ddr2(id_pc, insn);
|
get_insn_from_xilinx_ddr2(id_pc, insn);
|
`endif
|
`endif
|
4'hf:
|
4'hf:
|
// Flash isn't stored in a memory, it's an FSM so just skip/ignore
|
// Flash isn't stored in a memory, it's an FSM so just skip/ignore
|
insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
|
insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
|
default:
|
default:
|
begin
|
begin
|
$fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
|
$fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
|
insn = 32'hxxxxxxxx; // Unknown server
|
insn = 32'hxxxxxxxx; // Unknown server
|
end
|
end
|
endcase // case (id_pc[31:28])
|
endcase // case (id_pc[31:28])
|
end
|
end
|
endtask // get_insn_from_memory
|
endtask // get_insn_from_memory
|
|
|
|
|
reg [31:0] mem_word;
|
reg [31:0] mem_word;
|
reg [31:0] last_addr = 0;
|
reg [31:0] last_addr = 0;
|
reg [31:0] last_mem_word;
|
reg [31:0] last_mem_word;
|
|
|
//`define TRIGGER_FOR_CHECK (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
|
//`define TRIGGER_FOR_CHECK (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
|
// Disabled:
|
// Disabled:
|
`define TRIGGER_FOR_CHECK 0
|
`define TRIGGER_FOR_CHECK 0
|
`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
|
`define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
|
`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
|
`define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
|
|
|
// Check instruction in decode stage is what is in the RAM
|
// Check instruction in decode stage is what is in the RAM
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
always @(posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
begin
|
begin
|
if (`TRIGGER_FOR_CHECK)
|
if (`TRIGGER_FOR_CHECK)
|
begin
|
begin
|
// Check if it's a new PC - will also get triggered if the
|
// Check if it's a new PC - will also get triggered if the
|
// instruction has changed since we last checked it
|
// instruction has changed since we last checked it
|
if ((`PC_TO_CHECK !== last_addr) ||
|
if ((`PC_TO_CHECK !== last_addr) ||
|
(last_mem_word != `INSN_TO_CHECK))
|
(last_mem_word != `INSN_TO_CHECK))
|
begin
|
begin
|
// Decode stage not void, check instruction
|
// Decode stage not void, check instruction
|
// get PC
|
// get PC
|
get_insn_from_memory(`PC_TO_CHECK, mem_word);
|
get_insn_from_memory(`PC_TO_CHECK, mem_word);
|
|
|
// Debugging output to prove it's doing something!
|
// Debugging output to prove it's doing something!
|
//$display("%t: Checking instruction for address 0x%h - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, mem_word, `INSN_TO_CHECK);
|
//$display("%t: Checking instruction for address 0x%h - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, mem_word, `INSN_TO_CHECK);
|
|
|
if (mem_word !== `INSN_TO_CHECK)
|
if (mem_word !== `INSN_TO_CHECK)
|
begin
|
begin
|
$fdisplay(fgeneral, "%t: Instruction mismatch for address 0x%h - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, mem_word, `INSN_TO_CHECK);
|
$fdisplay(fgeneral, "%t: Instruction mismatch for address 0x%h - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, mem_word, `INSN_TO_CHECK);
|
#20
|
#20
|
$finish;
|
$finish;
|
end
|
end
|
last_addr = `PC_TO_CHECK;
|
last_addr = `PC_TO_CHECK;
|
last_mem_word = mem_word;
|
last_mem_word = mem_word;
|
end // if (`PC_TO_CHECK !== last_addr)
|
end // if (`PC_TO_CHECK !== last_addr)
|
end
|
end
|
end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
end // always @ (posedge `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk)
|
|
|
|
|
|
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
// Instruction decode task
|
// Instruction decode task
|
/////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////
|
|
|
|
|
`define OR32_OPCODE_POS 31:26
|
`define OR32_OPCODE_POS 31:26
|
`define OR32_J_BR_IMM_POS 25:0
|
`define OR32_J_BR_IMM_POS 25:0
|
`define OR32_RD_POS 25:21
|
`define OR32_RD_POS 25:21
|
`define OR32_RA_POS 20:16
|
`define OR32_RA_POS 20:16
|
`define OR32_RB_POS 15:11
|
`define OR32_RB_POS 15:11
|
`define OR32_ALU_OP_POS 3:0
|
`define OR32_ALU_OP_POS 3:0
|
|
|
`define OR32_SHROT_OP_POS 7:6
|
`define OR32_SHROT_OP_POS 7:6
|
`define OR32_SHROTI_IMM_POS 5:0
|
`define OR32_SHROTI_IMM_POS 5:0
|
`define OR32_SF_OP 25:21
|
`define OR32_SF_OP 25:21
|
|
|
`define OR32_XSYNC_OP_POS 25:21
|
`define OR32_XSYNC_OP_POS 25:21
|
|
|
|
|
// Switch between outputting to execution file or STD out for instruction
|
// Switch between outputting to execution file or STD out for instruction
|
// decoding task.
|
// decoding task.
|
//`define PRINT_OP_WRITE $write(
|
//`define PRINT_OP_WRITE $write(
|
`define PRINT_OP_WRITE $fwrite(fexe,
|
`define PRINT_OP_WRITE $fwrite(fexe,
|
|
|
task or1200_print_op;
|
task or1200_print_op;
|
input [31:0] insn;
|
input [31:0] insn;
|
|
|
reg [5:0] opcode;
|
reg [5:0] opcode;
|
|
|
reg [25:0] j_imm;
|
reg [25:0] j_imm;
|
reg [25:0] br_imm;
|
reg [25:0] br_imm;
|
|
|
reg [4:0] rD_num, rA_num, rB_num;
|
reg [4:0] rD_num, rA_num, rB_num;
|
reg [31:0] rA_val, rB_val;
|
reg [31:0] rA_val, rB_val;
|
reg [15:0] imm_16bit;
|
reg [15:0] imm_16bit;
|
reg [10:0] imm_split16bit;
|
reg [10:0] imm_split16bit;
|
|
|
reg [3:0] alu_op;
|
reg [3:0] alu_op;
|
reg [1:0] shrot_op;
|
reg [1:0] shrot_op;
|
|
|
reg [5:0] shroti_imm;
|
reg [5:0] shroti_imm;
|
|
|
reg [5:0] sf_op;
|
reg [5:0] sf_op;
|
|
|
reg [5:0] xsync_op;
|
reg [5:0] xsync_op;
|
|
|
begin
|
begin
|
// Instruction opcode
|
// Instruction opcode
|
opcode = insn[`OR32_OPCODE_POS];
|
opcode = insn[`OR32_OPCODE_POS];
|
// Immediates for jump or branch instructions
|
// Immediates for jump or branch instructions
|
j_imm = insn[`OR32_J_BR_IMM_POS];
|
j_imm = insn[`OR32_J_BR_IMM_POS];
|
br_imm = insn[`OR32_J_BR_IMM_POS];
|
br_imm = insn[`OR32_J_BR_IMM_POS];
|
// Register numbers (D, A and B)
|
// Register numbers (D, A and B)
|
rD_num = insn[`OR32_RD_POS];
|
rD_num = insn[`OR32_RD_POS];
|
rA_num = insn[`OR32_RA_POS];
|
rA_num = insn[`OR32_RA_POS];
|
rB_num = insn[`OR32_RB_POS];
|
rB_num = insn[`OR32_RB_POS];
|
// Bottom 16 bits when used as immediates in various instructions
|
// Bottom 16 bits when used as immediates in various instructions
|
imm_16bit = insn[15:0];
|
imm_16bit = insn[15:0];
|
// Bottom 11 bits used as immediates for l.sX instructions
|
// Bottom 11 bits used as immediates for l.sX instructions
|
|
|
// Split 16-bit immediate for l.mtspr/l.sX instructions
|
// Split 16-bit immediate for l.mtspr/l.sX instructions
|
imm_split16bit = {insn[25:21],insn[10:0]};
|
imm_split16bit = {insn[25:21],insn[10:0]};
|
// ALU op for ALU instructions
|
// ALU op for ALU instructions
|
alu_op = insn[`OR32_ALU_OP_POS];
|
alu_op = insn[`OR32_ALU_OP_POS];
|
// Shift-rotate op for SHROT ALU instructions
|
// Shift-rotate op for SHROT ALU instructions
|
shrot_op = insn[`OR32_SHROT_OP_POS];
|
shrot_op = insn[`OR32_SHROT_OP_POS];
|
shroti_imm = insn[`OR32_SHROTI_IMM_POS];
|
shroti_imm = insn[`OR32_SHROTI_IMM_POS];
|
|
|
// Set flag op
|
// Set flag op
|
sf_op = insn[`OR32_SF_OP];
|
sf_op = insn[`OR32_SF_OP];
|
|
|
// Xsync/syscall/trap opcode
|
// Xsync/syscall/trap opcode
|
xsync_op = insn[`OR32_XSYNC_OP_POS];
|
xsync_op = insn[`OR32_XSYNC_OP_POS];
|
|
|
case (opcode)
|
case (opcode)
|
`OR1200_OR32_J:
|
`OR1200_OR32_J:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.j 0x%h", {j_imm,2'b00});
|
`PRINT_OP_WRITE"l.j 0x%h", {j_imm,2'b00});
|
end
|
end
|
|
|
`OR1200_OR32_JAL:
|
`OR1200_OR32_JAL:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.jal 0x%h", {j_imm,2'b00});
|
`PRINT_OP_WRITE"l.jal 0x%h", {j_imm,2'b00});
|
end
|
end
|
|
|
`OR1200_OR32_BNF:
|
`OR1200_OR32_BNF:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.bnf 0x%h", {br_imm,2'b00});
|
`PRINT_OP_WRITE"l.bnf 0x%h", {br_imm,2'b00});
|
end
|
end
|
|
|
`OR1200_OR32_BF:
|
`OR1200_OR32_BF:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.bf 0x%h", {br_imm,2'b00});
|
`PRINT_OP_WRITE"l.bf 0x%h", {br_imm,2'b00});
|
end
|
end
|
|
|
`OR1200_OR32_RFE:
|
`OR1200_OR32_RFE:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.rfe");
|
`PRINT_OP_WRITE"l.rfe");
|
end
|
end
|
|
|
`OR1200_OR32_JR:
|
`OR1200_OR32_JR:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.jr r%0d",rB_num);
|
`PRINT_OP_WRITE"l.jr r%0d",rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_JALR:
|
`OR1200_OR32_JALR:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.jalr r%0d",rB_num);
|
`PRINT_OP_WRITE"l.jalr r%0d",rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_LWZ:
|
`OR1200_OR32_LWZ:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
`PRINT_OP_WRITE"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
end
|
end
|
|
|
`OR1200_OR32_LBZ:
|
`OR1200_OR32_LBZ:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
`PRINT_OP_WRITE"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
end
|
end
|
|
|
`OR1200_OR32_LBS:
|
`OR1200_OR32_LBS:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
`PRINT_OP_WRITE"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
end
|
end
|
|
|
`OR1200_OR32_LHZ:
|
`OR1200_OR32_LHZ:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
`PRINT_OP_WRITE"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
end
|
end
|
|
|
`OR1200_OR32_LHS:
|
`OR1200_OR32_LHS:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
`PRINT_OP_WRITE"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
|
end
|
end
|
|
|
`OR1200_OR32_SW:
|
`OR1200_OR32_SW:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
|
`PRINT_OP_WRITE"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_SB:
|
`OR1200_OR32_SB:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
|
`PRINT_OP_WRITE"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_SH:
|
`OR1200_OR32_SH:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
|
`PRINT_OP_WRITE"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_MFSPR:
|
`OR1200_OR32_MFSPR:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
|
`PRINT_OP_WRITE"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
|
end
|
end
|
|
|
`OR1200_OR32_MTSPR:
|
`OR1200_OR32_MTSPR:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
|
`PRINT_OP_WRITE"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
|
end
|
end
|
|
|
`OR1200_OR32_MOVHI:
|
`OR1200_OR32_MOVHI:
|
begin
|
begin
|
if (!insn[16])
|
if (!insn[16])
|
`PRINT_OP_WRITE"l.movhi r%0d,0x%h",rD_num,imm_16bit);
|
`PRINT_OP_WRITE"l.movhi r%0d,0x%h",rD_num,imm_16bit);
|
else
|
else
|
`PRINT_OP_WRITE"l.macrc r%0d",rD_num);
|
`PRINT_OP_WRITE"l.macrc r%0d",rD_num);
|
end
|
end
|
|
|
`OR1200_OR32_ADDI:
|
`OR1200_OR32_ADDI:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_ADDIC:
|
`OR1200_OR32_ADDIC:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_ANDI:
|
`OR1200_OR32_ANDI:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_ORI:
|
`OR1200_OR32_ORI:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_XORI:
|
`OR1200_OR32_XORI:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_MULI:
|
`OR1200_OR32_MULI:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_ALU:
|
`OR1200_OR32_ALU:
|
begin
|
begin
|
case(alu_op)
|
case(alu_op)
|
`OR1200_ALUOP_ADD:
|
`OR1200_ALUOP_ADD:
|
`PRINT_OP_WRITE"l.add ");
|
`PRINT_OP_WRITE"l.add ");
|
`OR1200_ALUOP_ADDC:
|
`OR1200_ALUOP_ADDC:
|
`PRINT_OP_WRITE"l.addc ");
|
`PRINT_OP_WRITE"l.addc ");
|
`OR1200_ALUOP_SUB:
|
`OR1200_ALUOP_SUB:
|
`PRINT_OP_WRITE"l.sub ");
|
`PRINT_OP_WRITE"l.sub ");
|
`OR1200_ALUOP_AND:
|
`OR1200_ALUOP_AND:
|
`PRINT_OP_WRITE"l.and ");
|
`PRINT_OP_WRITE"l.and ");
|
`OR1200_ALUOP_OR:
|
`OR1200_ALUOP_OR:
|
`PRINT_OP_WRITE"l.or ");
|
`PRINT_OP_WRITE"l.or ");
|
`OR1200_ALUOP_XOR:
|
`OR1200_ALUOP_XOR:
|
`PRINT_OP_WRITE"l.xor ");
|
`PRINT_OP_WRITE"l.xor ");
|
`OR1200_ALUOP_MUL:
|
`OR1200_ALUOP_MUL:
|
`PRINT_OP_WRITE"l.mul ");
|
`PRINT_OP_WRITE"l.mul ");
|
`OR1200_ALUOP_SHROT:
|
`OR1200_ALUOP_SHROT:
|
begin
|
begin
|
case(shrot_op)
|
case(shrot_op)
|
`OR1200_SHROTOP_SLL:
|
`OR1200_SHROTOP_SLL:
|
`PRINT_OP_WRITE"l.sll ");
|
`PRINT_OP_WRITE"l.sll ");
|
`OR1200_SHROTOP_SRL:
|
`OR1200_SHROTOP_SRL:
|
`PRINT_OP_WRITE"l.srl ");
|
`PRINT_OP_WRITE"l.srl ");
|
`OR1200_SHROTOP_SRA:
|
`OR1200_SHROTOP_SRA:
|
`PRINT_OP_WRITE"l.sra ");
|
`PRINT_OP_WRITE"l.sra ");
|
`OR1200_SHROTOP_ROR:
|
`OR1200_SHROTOP_ROR:
|
`PRINT_OP_WRITE"l.ror ");
|
`PRINT_OP_WRITE"l.ror ");
|
endcase // case (shrot_op)
|
endcase // case (shrot_op)
|
end
|
end
|
`OR1200_ALUOP_DIV:
|
`OR1200_ALUOP_DIV:
|
`PRINT_OP_WRITE"l.div ");
|
`PRINT_OP_WRITE"l.div ");
|
`OR1200_ALUOP_DIVU:
|
`OR1200_ALUOP_DIVU:
|
`PRINT_OP_WRITE"l.divu ");
|
`PRINT_OP_WRITE"l.divu ");
|
`OR1200_ALUOP_CMOV:
|
`OR1200_ALUOP_CMOV:
|
`PRINT_OP_WRITE"l.cmov ");
|
`PRINT_OP_WRITE"l.cmov ");
|
endcase // case (alu_op)
|
endcase // case (alu_op)
|
`PRINT_OP_WRITE"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
|
`PRINT_OP_WRITE"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_SH_ROTI:
|
`OR1200_OR32_SH_ROTI:
|
begin
|
begin
|
case(shrot_op)
|
case(shrot_op)
|
`OR1200_SHROTOP_SLL:
|
`OR1200_SHROTOP_SLL:
|
`PRINT_OP_WRITE"l.slli ");
|
`PRINT_OP_WRITE"l.slli ");
|
`OR1200_SHROTOP_SRL:
|
`OR1200_SHROTOP_SRL:
|
`PRINT_OP_WRITE"l.srli ");
|
`PRINT_OP_WRITE"l.srli ");
|
`OR1200_SHROTOP_SRA:
|
`OR1200_SHROTOP_SRA:
|
`PRINT_OP_WRITE"l.srai ");
|
`PRINT_OP_WRITE"l.srai ");
|
`OR1200_SHROTOP_ROR:
|
`OR1200_SHROTOP_ROR:
|
`PRINT_OP_WRITE"l.rori ");
|
`PRINT_OP_WRITE"l.rori ");
|
endcase // case (shrot_op)
|
endcase // case (shrot_op)
|
`PRINT_OP_WRITE"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
|
`PRINT_OP_WRITE"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
|
end
|
end
|
|
|
`OR1200_OR32_SFXXI:
|
`OR1200_OR32_SFXXI:
|
begin
|
begin
|
case(sf_op[2:0])
|
case(sf_op[2:0])
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
`PRINT_OP_WRITE"l.sfeqi ");
|
`PRINT_OP_WRITE"l.sfeqi ");
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
`PRINT_OP_WRITE"l.sfnei ");
|
`PRINT_OP_WRITE"l.sfnei ");
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sfgtsi ");
|
`PRINT_OP_WRITE"l.sfgtsi ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfgtui ");
|
`PRINT_OP_WRITE"l.sfgtui ");
|
end
|
end
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sfgesi ");
|
`PRINT_OP_WRITE"l.sfgesi ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfgeui ");
|
`PRINT_OP_WRITE"l.sfgeui ");
|
end
|
end
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sfltsi ");
|
`PRINT_OP_WRITE"l.sfltsi ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfltui ");
|
`PRINT_OP_WRITE"l.sfltui ");
|
end
|
end
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sflesi ");
|
`PRINT_OP_WRITE"l.sflesi ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfleui ");
|
`PRINT_OP_WRITE"l.sfleui ");
|
end
|
end
|
endcase // case (sf_op[2:0])
|
endcase // case (sf_op[2:0])
|
|
|
`PRINT_OP_WRITE"r%0d,0x%h",rA_num, imm_16bit);
|
`PRINT_OP_WRITE"r%0d,0x%h",rA_num, imm_16bit);
|
|
|
end // case: `OR1200_OR32_SFXXI
|
end // case: `OR1200_OR32_SFXXI
|
|
|
`OR1200_OR32_SFXX:
|
`OR1200_OR32_SFXX:
|
begin
|
begin
|
case(sf_op[2:0])
|
case(sf_op[2:0])
|
`OR1200_COP_SFEQ:
|
`OR1200_COP_SFEQ:
|
`PRINT_OP_WRITE"l.sfeq ");
|
`PRINT_OP_WRITE"l.sfeq ");
|
`OR1200_COP_SFNE:
|
`OR1200_COP_SFNE:
|
`PRINT_OP_WRITE"l.sfne ");
|
`PRINT_OP_WRITE"l.sfne ");
|
`OR1200_COP_SFGT:
|
`OR1200_COP_SFGT:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sfgts ");
|
`PRINT_OP_WRITE"l.sfgts ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfgtu ");
|
`PRINT_OP_WRITE"l.sfgtu ");
|
end
|
end
|
`OR1200_COP_SFGE:
|
`OR1200_COP_SFGE:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sfges ");
|
`PRINT_OP_WRITE"l.sfges ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfgeu ");
|
`PRINT_OP_WRITE"l.sfgeu ");
|
end
|
end
|
`OR1200_COP_SFLT:
|
`OR1200_COP_SFLT:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sflts ");
|
`PRINT_OP_WRITE"l.sflts ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfltu ");
|
`PRINT_OP_WRITE"l.sfltu ");
|
end
|
end
|
`OR1200_COP_SFLE:
|
`OR1200_COP_SFLE:
|
begin
|
begin
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
if (sf_op[`OR1200_SIGNED_COMPARE])
|
`PRINT_OP_WRITE"l.sfles ");
|
`PRINT_OP_WRITE"l.sfles ");
|
else
|
else
|
`PRINT_OP_WRITE"l.sfleu ");
|
`PRINT_OP_WRITE"l.sfleu ");
|
end
|
end
|
|
|
endcase // case (sf_op[2:0])
|
endcase // case (sf_op[2:0])
|
|
|
`PRINT_OP_WRITE"r%0d,r%0d",rA_num, rB_num);
|
`PRINT_OP_WRITE"r%0d,r%0d",rA_num, rB_num);
|
|
|
end
|
end
|
|
|
`OR1200_OR32_MACI:
|
`OR1200_OR32_MACI:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.maci r%0d,0x%h",rA_num,imm_16bit);
|
`PRINT_OP_WRITE"l.maci r%0d,0x%h",rA_num,imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_MACMSB:
|
`OR1200_OR32_MACMSB:
|
begin
|
begin
|
if(insn[3:0] == 4'h1)
|
if(insn[3:0] == 4'h1)
|
`PRINT_OP_WRITE"l.mac ");
|
`PRINT_OP_WRITE"l.mac ");
|
else if(insn[3:0] == 4'h2)
|
else if(insn[3:0] == 4'h2)
|
`PRINT_OP_WRITE"l.msb ");
|
`PRINT_OP_WRITE"l.msb ");
|
|
|
`PRINT_OP_WRITE"r%0d,r%0d",rA_num,rB_num);
|
`PRINT_OP_WRITE"r%0d,r%0d",rA_num,rB_num);
|
end
|
end
|
|
|
`OR1200_OR32_NOP:
|
`OR1200_OR32_NOP:
|
begin
|
begin
|
`PRINT_OP_WRITE"l.nop 0x%0h",imm_16bit);
|
`PRINT_OP_WRITE"l.nop 0x%0h",imm_16bit);
|
end
|
end
|
|
|
`OR1200_OR32_XSYNC:
|
`OR1200_OR32_XSYNC:
|
begin
|
begin
|
case (xsync_op)
|
case (xsync_op)
|
5'd0:
|
5'd0:
|
`PRINT_OP_WRITE"l.sys 0x%h",imm_16bit);
|
`PRINT_OP_WRITE"l.sys 0x%h",imm_16bit);
|
5'd8:
|
5'd8:
|
`PRINT_OP_WRITE"l.trap 0x%h",imm_16bit);
|
`PRINT_OP_WRITE"l.trap 0x%h",imm_16bit);
|
5'd16:
|
5'd16:
|
`PRINT_OP_WRITE"l.msync");
|
`PRINT_OP_WRITE"l.msync");
|
5'd20:
|
5'd20:
|
`PRINT_OP_WRITE"l.psync");
|
`PRINT_OP_WRITE"l.psync");
|
5'd24:
|
5'd24:
|
`PRINT_OP_WRITE"l.csync");
|
`PRINT_OP_WRITE"l.csync");
|
default:
|
default:
|
begin
|
begin
|
$display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
|
$display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
|
`PRINT_OP_WRITE"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
|
`PRINT_OP_WRITE"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
|
end
|
end
|
endcase // case (xsync_op)
|
endcase // case (xsync_op)
|
end
|
end
|
|
|
default:
|
default:
|
begin
|
begin
|
$display("%t: Unknown opcode 0x%h",$time,opcode);
|
$display("%t: Unknown opcode 0x%h",$time,opcode);
|
`PRINT_OP_WRITE"%t: Unknown opcode 0x%h",$time,opcode);
|
`PRINT_OP_WRITE"%t: Unknown opcode 0x%h",$time,opcode);
|
end
|
end
|
|
|
endcase // case (opcode)
|
endcase // case (opcode)
|
|
|
end
|
end
|
endtask // or1200_print_op
|
endtask // or1200_print_op
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
