//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's simulation monitor ////
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//// OR1200's simulation monitor ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Simulation monitor ////
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//// Simulation monitor ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - move it to bench ////
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//// - move it to bench ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: or1200_monitor.v,v $
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// $Log: or1200_monitor.v,v $
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// Revision 1.4 2004/04/05 08:46:06 lampret
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// Revision 1.4 2004/04/05 08:46:06 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.3 2003/04/07 01:32:53 lampret
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// Revision 1.3 2003/04/07 01:32:53 lampret
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// Added get_gpr support for OR1200_RFRAM_GENERIC
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// Added get_gpr support for OR1200_RFRAM_GENERIC
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//
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//
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// Revision 1.2 2002/08/12 05:38:11 lampret
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// Revision 1.2 2002/08/12 05:38:11 lampret
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// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
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// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
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//
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//
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// Revision 1.1 2002/03/28 19:59:55 lampret
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// Revision 1.1 2002/03/28 19:59:55 lampret
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// Added bench directory
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// Added bench directory
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//
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//
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// Revision 1.9 2002/02/01 19:56:54 lampret
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// Revision 1.9 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.8 2002/01/28 01:25:22 lampret
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// Revision 1.8 2002/01/28 01:25:22 lampret
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// Fixed display of new 'void' nop insns.
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// Fixed display of new 'void' nop insns.
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//
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//
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// Revision 1.7 2002/01/19 14:10:39 lampret
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// Revision 1.7 2002/01/19 14:10:39 lampret
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// Fixed OR1200_XILINX_RAM32X1D.
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// Fixed OR1200_XILINX_RAM32X1D.
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//
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//
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// Revision 1.6 2002/01/18 07:57:56 lampret
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// Revision 1.6 2002/01/18 07:57:56 lampret
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// Added support for reading XILINX_RAM32X1D register file.
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// Added support for reading XILINX_RAM32X1D register file.
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//
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//
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// Revision 1.5 2002/01/14 06:19:35 lampret
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// Revision 1.5 2002/01/14 06:19:35 lampret
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// Added debug model for testing du. Updated or1200_monitor.
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// Added debug model for testing du. Updated or1200_monitor.
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//
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//
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// Revision 1.4 2002/01/03 08:40:15 lampret
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// Revision 1.4 2002/01/03 08:40:15 lampret
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// Added second clock as RISC main clock. Updated or120_monitor.
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// Added second clock as RISC main clock. Updated or120_monitor.
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//
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//
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// Revision 1.3 2001/11/23 08:50:35 lampret
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// Revision 1.3 2001/11/23 08:50:35 lampret
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// Typos.
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// Typos.
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//
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//
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// Revision 1.2 2001/11/10 04:22:55 lampret
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// Revision 1.2 2001/11/10 04:22:55 lampret
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// Modified monitor tu support exceptions.
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// Modified monitor tu support exceptions.
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//
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//
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// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
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// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
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// First import.
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// First import.
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//
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//
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Initial revision
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// Initial revision
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//
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//
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Added monitor.v and timescale.v
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// Added monitor.v and timescale.v
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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`include "orpsoc_testbench_defines.v"
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//
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//
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// Top of OR1200 inside test bench
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// Top of OR1200 inside test bench
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//
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//
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`ifndef OR1200_TOP
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`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
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`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
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`include "orpsoc_testbench_defines.v"
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`else
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`include `TESTBENCH_DEFINES
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`endif
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//
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//
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// Enable display_arch_state task
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// Enable display_arch_state task
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//
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//
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//`define OR1200_DISPLAY_ARCH_STATE
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//`define OR1200_DISPLAY_ARCH_STATE
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module or1200_monitor;
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module or1200_monitor;
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integer fexe;
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integer fexe;
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reg [23:0] ref;
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reg [23:0] ref;
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integer fspr;
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integer fspr;
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integer fgeneral;
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integer fgeneral;
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integer flookup;
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integer flookup;
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integer r3;
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integer r3;
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integer insns;
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integer insns;
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//
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//
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// Initialization
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// Initialization
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//
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//
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initial begin
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initial begin
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ref = 0;
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ref = 0;
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fexe = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-executed.log"});
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fexe = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-executed.log"});
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$timeformat (-9, 2, " ns", 12);
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$timeformat (-9, 2, " ns", 12);
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fspr = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-sprs.log"});
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fspr = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-sprs.log"});
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fgeneral = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-general.log"});
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fgeneral = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-general.log"});
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flookup = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-lookup.log"});
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flookup = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-lookup.log"});
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insns = 0;
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insns = 0;
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end
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end
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//
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//
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// Get GPR
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// Get GPR
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//
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//
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task get_gpr;
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task get_gpr;
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input [4:0] gpr_no;
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input [4:0] gpr_no;
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output [31:0] gpr;
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output [31:0] gpr;
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integer j;
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integer j;
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begin
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begin
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`ifdef OR1200_RFRAM_GENERIC
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`ifdef OR1200_RFRAM_GENERIC
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for(j = 0; j < 32; j = j + 1) begin
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for(j = 0; j < 32; j = j + 1) begin
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gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
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gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
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end
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end
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`else
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`else
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`ifdef OR1200_XILINX_RAM32X1D
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`ifdef OR1200_XILINX_RAM32X1D
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gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
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gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
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gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
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gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
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gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
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gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
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gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
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gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
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gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
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gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
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gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
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gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
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gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
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gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
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gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
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gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
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gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
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gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
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gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
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gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
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gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
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gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
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gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
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gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
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gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
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gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
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gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
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gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
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gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
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gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
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gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
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gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
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gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
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gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
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gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
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gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
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gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
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gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
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gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
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gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
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gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
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gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
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gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
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gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
|
gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
|
gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
|
gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
|
gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
|
gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
|
gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
|
gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
|
gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
|
gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
|
gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
|
gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
|
gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
|
gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
|
gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
|
gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
|
gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
|
gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
|
gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
|
gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
|
gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
|
`else
|
`else
|
`ifdef OR1200_XILINX_RAMB4
|
`ifdef OR1200_XILINX_RAMB4
|
for(j = 0; j < 16; j = j + 1) begin
|
for(j = 0; j < 16; j = j + 1) begin
|
gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
|
gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
|
end
|
end
|
for(j = 0; j < 16; j = j + 1) begin
|
for(j = 0; j < 16; j = j + 1) begin
|
gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
|
gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
|
end
|
end
|
`else
|
`else
|
`ifdef OR1200_ARTISAN_SDP
|
`ifdef OR1200_ARTISAN_SDP
|
`else
|
`else
|
|
`ifdef OR1200_XILINX_RAMB16
|
|
`ifdef legacy_model
|
|
for(j = 0; j < 32; j = j + 1) begin
|
|
gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[gpr_no*32+j];
|
|
end
|
|
`else
|
|
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[gpr_no];
|
|
`endif
|
|
`else
|
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
|
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
|
`endif
|
`endif
|
`endif
|
end
|
end
|
endtask
|
endtask
|
|
|
//
|
//
|
// Write state of the OR1200 registers into a file
|
// Write state of the OR1200 registers into a file
|
//
|
//
|
// Limitation: only a small subset of register file RAMs
|
// Limitation: only a small subset of register file RAMs
|
// are supported
|
// are supported
|
//
|
//
|
task display_arch_state;
|
task display_arch_state;
|
reg [5:0] i;
|
reg [5:0] i;
|
reg [31:0] r;
|
reg [31:0] r;
|
integer j;
|
integer j;
|
begin
|
begin
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
ref = ref + 1;
|
ref = ref + 1;
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
|
for(i = 0; i < 32; i = i + 1) begin
|
for(i = 0; i < 32; i = i + 1) begin
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
$fdisplay(fexe);
|
$fdisplay(fexe);
|
get_gpr(i, r);
|
get_gpr(i, r);
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
end
|
end
|
$fdisplay(fexe);
|
$fdisplay(fexe);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
$fwrite(fexe, "SR : %h ", r);
|
$fwrite(fexe, "SR : %h ", r);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
$fwrite(fexe, "EPCR0: %h ", r);
|
$fwrite(fexe, "EPCR0: %h ", r);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
$fwrite(fexe, "EEAR0: %h ", r);
|
$fwrite(fexe, "EEAR0: %h ", r);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
$fdisplay(fexe, "ESR0 : %h", r);
|
$fdisplay(fexe, "ESR0 : %h", r);
|
insns = insns + 1;
|
insns = insns + 1;
|
`endif
|
`endif
|
end
|
end
|
endtask // display_arch_state
|
endtask // display_arch_state
|
|
|
//
|
//
|
// Write state of the OR1200 registers into a file; version for exception
|
// Write state of the OR1200 registers into a file; version for exception
|
//
|
//
|
task display_arch_state_except;
|
task display_arch_state_except;
|
reg [5:0] i;
|
reg [5:0] i;
|
reg [31:0] r;
|
reg [31:0] r;
|
integer j;
|
integer j;
|
begin
|
begin
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
`ifdef OR1200_DISPLAY_ARCH_STATE
|
ref = ref + 1;
|
ref = ref + 1;
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
|
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
|
for(i = 0; i < 32; i = i + 1) begin
|
for(i = 0; i < 32; i = i + 1) begin
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
$fdisplay(fexe);
|
$fdisplay(fexe);
|
get_gpr(i, r);
|
get_gpr(i, r);
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
$fwrite(fexe, "GPR%d: %h ", i, r);
|
end
|
end
|
$fdisplay(fexe);
|
$fdisplay(fexe);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
|
$fwrite(fexe, "SR : %h ", r);
|
$fwrite(fexe, "SR : %h ", r);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
|
$fwrite(fexe, "EPCR0: %h ", r);
|
$fwrite(fexe, "EPCR0: %h ", r);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
|
$fwrite(fexe, "EEAR0: %h ", r);
|
$fwrite(fexe, "EEAR0: %h ", r);
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
|
$fdisplay(fexe, "ESR0 : %h", r);
|
$fdisplay(fexe, "ESR0 : %h", r);
|
insns = insns + 1;
|
insns = insns + 1;
|
`endif
|
`endif
|
end
|
end
|
endtask // display_arch_state_except
|
endtask // display_arch_state_except
|
|
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
/* Keep a trace buffer of the last lot of instructions and addresses
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* "executed",as read from the writeback stage, and cause a $finish if we hit
|
* an instruction that is invalid, such as all zeros.
|
* an instruction that is invalid, such as all zeros.
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* Currently, only breaks on an all zero instruction, but should probably be
|
* made to break for anything with an X in it too. And of course ideally this
|
* made to break for anything with an X in it too. And of course ideally this
|
* shouldn't be needed - but is handy if someone changes something and stops
|
* shouldn't be needed - but is handy if someone changes something and stops
|
* the test continuing forever.
|
* the test continuing forever.
|
*/
|
*/
|
integer num_nul_inst;
|
integer num_nul_inst;
|
initial num_nul_inst = 0;
|
initial num_nul_inst = 0;
|
|
|
task monitor_for_crash;
|
task monitor_for_crash;
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
|
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
|
reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
|
reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
|
integer i;
|
integer i;
|
|
|
begin
|
begin
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
|
num_nul_inst = num_nul_inst + 1;
|
num_nul_inst = num_nul_inst + 1;
|
|
|
if (num_nul_inst == 1000) // Sat a loop a bit too long...
|
if (num_nul_inst == 1000) // Sat a loop a bit too long...
|
begin
|
begin
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
|
$fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
|
|
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
$fdisplay(fgeneral, "PC\t\tINSTR");
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
|
end
|
end
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
|
insn_trace[i] = insn_trace[i-1];
|
insn_trace[i] = insn_trace[i-1];
|
addr_trace[i] = addr_trace[i-1];
|
addr_trace[i] = addr_trace[i-1];
|
end
|
end
|
insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
|
insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
|
addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
|
addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
|
end
|
end
|
|
|
end
|
end
|
endtask // monitor_for_crash
|
endtask // monitor_for_crash
|
|
|
integer iwb_progress;
|
integer iwb_progress;
|
reg [31:0] iwb_progress_addr;
|
reg [31:0] iwb_progress_addr;
|
//
|
//
|
// WISHBONE bus checker
|
// WISHBONE bus checker
|
//
|
//
|
always @(posedge `OR1200_TOP.iwb_clk_i)
|
always @(posedge `OR1200_TOP.iwb_clk_i)
|
if (`OR1200_TOP.iwb_rst_i) begin
|
if (`OR1200_TOP.iwb_rst_i) begin
|
iwb_progress = 0;
|
iwb_progress = 0;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
end
|
end
|
else begin
|
else begin
|
if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
|
if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
|
iwb_progress = 1;
|
iwb_progress = 1;
|
end
|
end
|
if (`OR1200_TOP.iwb_stb_o) begin
|
if (`OR1200_TOP.iwb_stb_o) begin
|
if (iwb_progress >= 1) begin
|
if (iwb_progress >= 1) begin
|
if (iwb_progress == 1)
|
if (iwb_progress == 1)
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress = 2;
|
iwb_progress = 2;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
end
|
end
|
if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
|
if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
|
end
|
end
|
if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
|
if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
|
if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
|
if (iwb_progress == 2) begin
|
if (iwb_progress == 2) begin
|
iwb_progress = 0;
|
iwb_progress = 0;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
|
if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
|
/* #100 $finish;*/
|
/* #100 $finish;*/
|
end
|
end
|
end
|
end
|
|
|
integer dwb_progress;
|
integer dwb_progress;
|
reg [31:0] dwb_progress_addr;
|
reg [31:0] dwb_progress_addr;
|
//
|
//
|
// WISHBONE bus checker
|
// WISHBONE bus checker
|
//
|
//
|
always @(posedge `OR1200_TOP.dwb_clk_i)
|
always @(posedge `OR1200_TOP.dwb_clk_i)
|
if (`OR1200_TOP.dwb_rst_i)
|
if (`OR1200_TOP.dwb_rst_i)
|
dwb_progress = 0;
|
dwb_progress = 0;
|
else begin
|
else begin
|
if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
|
if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
|
dwb_progress = 1;
|
dwb_progress = 1;
|
if (`OR1200_TOP.dwb_stb_o)
|
if (`OR1200_TOP.dwb_stb_o)
|
if (dwb_progress >= 1) begin
|
if (dwb_progress >= 1) begin
|
if (dwb_progress == 1)
|
if (dwb_progress == 1)
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
dwb_progress = 2;
|
dwb_progress = 2;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
|
if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
|
end
|
end
|
if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
|
if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
|
if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
|
if (dwb_progress == 2) begin
|
if (dwb_progress == 2) begin
|
dwb_progress = 0;
|
dwb_progress = 0;
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
|
end
|
end
|
else begin
|
else begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
|
if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
|
#100 $finish;
|
#100 $finish;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Hooks for:
|
// Hooks for:
|
// - displaying registers
|
// - displaying registers
|
// - end of simulation
|
// - end of simulation
|
// - access to SPRs
|
// - access to SPRs
|
//
|
//
|
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
|
always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
|
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
|
if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
|
#2;
|
#2;
|
if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
|
if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
|
&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
|
&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
|
begin
|
begin
|
display_arch_state;
|
display_arch_state;
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monitor_for_crash;
|
monitor_for_crash;
|
end
|
end
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else
|
else
|
if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
|
if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
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display_arch_state_except;
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display_arch_state_except;
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
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if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
|
get_gpr(3, r3);
|
get_gpr(3, r3);
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$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
|
$finish;
|
$finish;
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
|
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
|
$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
|
`ifdef DBG_IF_MODEL
|
`ifdef DBG_IF_MODEL
|
xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
|
xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
|
`endif
|
`endif
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
|
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
|
get_gpr(3, r3);
|
get_gpr(3, r3);
|
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
|
$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
|
end
|
end
|
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
|
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
|
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
|
$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
|
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
|
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
|
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
|
if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
|
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
|
$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
|
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
|
`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|