/*$$HEADER*/
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/*$$HEADER*/
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/******************************************************************************/
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/******************************************************************************/
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/* */
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/* */
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/* H E A D E R I N F O R M A T I O N */
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/* H E A D E R I N F O R M A T I O N */
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/* */
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/* */
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/******************************************************************************/
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/******************************************************************************/
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// Project Name : ORPSoCv2
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// Project Name : ORPSoCv2
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// File Name : rsp-vpi.h
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// File Name : rsp-vpi.h
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// Prepared By : jb, jb@orsoc.se
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// Prepared By : jb, jb@orsoc.se
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// Project Start : 2009-05-01
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// Project Start : 2009-05-01
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/*$$COPYRIGHT NOTICE*/
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/*$$COPYRIGHT NOTICE*/
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/******************************************************************************/
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/******************************************************************************/
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/* */
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/* */
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/* C O P Y R I G H T N O T I C E */
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/* C O P Y R I G H T N O T I C E */
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/* */
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/* */
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/******************************************************************************/
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/******************************************************************************/
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/*
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/*
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This library is free software; you can redistribute it and/or
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation;
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License as published by the Free Software Foundation;
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version 2.1 of the License, a copy of which is available from
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version 2.1 of the License, a copy of which is available from
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http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
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http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
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This library is distributed in the hope that it will be useful,
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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// Defines for protocol ensuring synchronisation with the simulation process
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// Defines for protocol ensuring synchronisation with the simulation process
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// 1. rsp-rtl_sim will first write a command byte
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// 1. rsp-rtl_sim will first write a command byte
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// 2. rsp-rtl_sim will then send the address if it's a read or write
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// 2. rsp-rtl_sim will then send the address if it's a read or write
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// or the data to write if it's a dbg_cpu_wr_ctrl (stall & reset bits)
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// or the data to write if it's a dbg_cpu_wr_ctrl (stall & reset bits)
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// 3. will then send data if we're writing and we sent address in 2
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// 3. will then send data if we're writing and we sent address in 2
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// 4. wait for response from vpi functions
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// 4. wait for response from vpi functions
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// commands:
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// commands:
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// 4'h1 jtag set instruction register (input: instruction value)
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// 4'h1 jtag set instruction register (input: instruction value)
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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
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// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
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// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
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// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
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// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
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// 4'h5 cpu wr reg (inputs: address, data)
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// 4'h5 cpu wr reg (inputs: address, data)
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// 4'h6 cpu rd reg (input: address; output: data)
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// 4'h6 cpu rd reg (input: address; output: data)
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// 4'h7 wb wr (inputs: address, data, size)
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// 4'h7 wb wr (inputs: address, data, size)
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// 4'h8 wb rd 32 (input: address; output: data)
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// 4'h8 wb rd 32 (input: address; output: data)
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// 4'h9 wb wr block 32 (inputs: address, length, data)
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// 4'h9 wb wr block 32 (inputs: address, length, data)
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// 4'ha wb rd block 32 (inputs: address, length; output: data)
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// 4'ha wb rd block 32 (inputs: address, length; output: data)
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// 4'hb reset
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// 4'hb reset
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// 4'hc read jtag id (output: data)
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// 4'hc read jtag id (output: data)
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// 4'hd GDB detach - do something (like close down, restart, etc.)
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// 4'hd GDB detach - do something (like close down, restart, etc.)
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// 4'he wb rd 8 (input: address, data pointer)
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// There should be a correlating set of verilog `define's in the
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// There should be a correlating set of verilog `define's in the
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// verilog debug testbench module's include file, test_defines.v
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// verilog debug testbench module's include file, vpi_debug_defines.v
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#define CMD_JTAG_SET_IR 0x1
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#define CMD_JTAG_SET_IR 0x1
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#define CMD_SET_DEBUG_CHAIN 0x2
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#define CMD_SET_DEBUG_CHAIN 0x2
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#define CMD_CPU_CTRL_WR 0x3
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#define CMD_CPU_CTRL_WR 0x3
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#define CMD_CPU_CTRL_RD 0x4
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#define CMD_CPU_CTRL_RD 0x4
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#define CMD_CPU_WR_REG 0x5
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#define CMD_CPU_WR_REG 0x5
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#define CMD_CPU_RD_REG 0x6
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#define CMD_CPU_RD_REG 0x6
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#define CMD_WB_WR 0x7
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#define CMD_WB_WR 0x7
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#define CMD_WB_RD32 0x8
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#define CMD_WB_RD32 0x8
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#define CMD_WB_BLOCK_WR32 0x9
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#define CMD_WB_BLOCK_WR32 0x9
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#define CMD_WB_BLOCK_RD32 0xa
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#define CMD_WB_BLOCK_RD32 0xa
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#define CMD_RESET 0xb
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#define CMD_RESET 0xb
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#define CMD_READ_JTAG_ID 0xc
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#define CMD_READ_JTAG_ID 0xc
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#define CMD_GDB_DETACH 0xd
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#define CMD_GDB_DETACH 0xd
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#define CMD_WB_RD8 0xe
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No newline at end of file
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No newline at end of file
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