//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ORPSoC Testbench ////
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//// ORPSoC Testbench ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ORPSoC VPI Debugging Testbench defines file ////
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//// ORPSoC VPI Debugging Testbench defines file ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - jb, jb@orsoc.se ////
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//// - jb, jb@orsoc.se ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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// Defines from the following files:
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// Defines from the following files:
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// tap_defines.v
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// tap_defines.v
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// Define IDCODE Value
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// Define IDCODE Value
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`define IDCODE_VALUE 32'h14951185
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`define IDCODE_VALUE 32'h14951185
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// Length of the Instruction register
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// Length of the Instruction register
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`define IR_LENGTH 4
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`define IR_LENGTH 4
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// Supported Instructions
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// Supported Instructions
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`define EXTEST 4'b0000
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`define EXTEST 4'b0000
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`define SAMPLE_PRELOAD 4'b0001
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`define SAMPLE_PRELOAD 4'b0001
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`define IDCODE 4'b0010
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`define IDCODE 4'b0010
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`define DEBUG 4'b1000
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`define DEBUG 4'b1000
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`define MBIST 4'b1001
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`define MBIST 4'b1001
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`define BYPASS 4'b1111
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`define BYPASS 4'b1111
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// Number of cells in boundary scan chain
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// Number of cells in boundary scan chain
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`define BS_CELL_NB 32'd558
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`define BS_CELL_NB 32'd558
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//dbg_defines.v
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//dbg_defines.v
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// Length of the MODULE ID register
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// Length of the MODULE ID register
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`define DBG_TOP_MODULE_ID_LENGTH 4
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`define DBG_TOP_MODULE_ID_LENGTH 4
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// Length of data
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// Length of data
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`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
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`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
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`define DBG_TOP_DATA_CNT 3
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`define DBG_TOP_DATA_CNT 3
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// Length of status
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// Length of status
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`define DBG_TOP_STATUS_LEN 3'd4
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`define DBG_TOP_STATUS_LEN 3'd4
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`define DBG_TOP_STATUS_CNT_WIDTH 3
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`define DBG_TOP_STATUS_CNT_WIDTH 3
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// Length of the CRC
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// Length of the CRC
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`define DBG_TOP_CRC_LEN 32
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`define DBG_TOP_CRC_LEN 32
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`define DBG_TOP_CRC_CNT 6
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`define DBG_TOP_CRC_CNT 6
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// Chains
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// Chains
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`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
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`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
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`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
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`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
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`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
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`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
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// dbg_wb_defines.v
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// dbg_wb_defines.v
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// If WISHBONE sub-module is supported uncomment the folowing line
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// If WISHBONE sub-module is supported uncomment the folowing line
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`define DBG_WISHBONE_SUPPORTED
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`define DBG_WISHBONE_SUPPORTED
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// If CPU_0 sub-module is supported uncomment the folowing line
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// If CPU_0 sub-module is supported uncomment the folowing line
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`define DBG_CPU0_SUPPORTED
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`define DBG_CPU0_SUPPORTED
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// If CPU_1 sub-module is supported uncomment the folowing line
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// If CPU_1 sub-module is supported uncomment the folowing line
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//`define DBG_CPU1_SUPPORTED
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//`define DBG_CPU1_SUPPORTED
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// If more debug info is needed, uncomment the follofing line
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// If more debug info is needed, uncomment the follofing line
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//`define DBG_MORE_INFO
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//`define DBG_MORE_INFO
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// Defining length of the command
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// Defining length of the command
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`define DBG_WB_CMD_LEN 3'd4
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`define DBG_WB_CMD_LEN 3'd4
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`define DBG_WB_CMD_CNT_WIDTH 3
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`define DBG_WB_CMD_CNT_WIDTH 3
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// Defining length of the access_type field
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// Defining length of the access_type field
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`define DBG_WB_ACC_TYPE_LEN 3'd4
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`define DBG_WB_ACC_TYPE_LEN 3'd4
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// Defining length of the address
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// Defining length of the address
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`define DBG_WB_ADR_LEN 6'd32
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`define DBG_WB_ADR_LEN 6'd32
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// Defining length of the length register
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// Defining length of the length register
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`define DBG_WB_LEN_LEN 5'd16
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`define DBG_WB_LEN_LEN 5'd16
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// Defining total length of the DR needed
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// Defining total length of the DR needed
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`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
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`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
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// Defining length of the CRC
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// Defining length of the CRC
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`define DBG_WB_CRC_LEN 6'd32
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`define DBG_WB_CRC_LEN 6'd32
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`define DBG_WB_CRC_CNT_WIDTH 6
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`define DBG_WB_CRC_CNT_WIDTH 6
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// Defining length of status
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// Defining length of status
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`define DBG_WB_STATUS_LEN 3'd4
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`define DBG_WB_STATUS_LEN 3'd4
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`define DBG_WB_STATUS_CNT_WIDTH 3
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`define DBG_WB_STATUS_CNT_WIDTH 3
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// Defining length of the data
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// Defining length of the data
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`define DBG_WB_DATA_CNT_WIDTH (`DBG_WB_LEN_LEN + 3)
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`define DBG_WB_DATA_CNT_WIDTH (`DBG_WB_LEN_LEN + 3)
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`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
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`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
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//Defining commands
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//Defining commands
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`define DBG_WB_GO 4'h0
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`define DBG_WB_GO 4'h0
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`define DBG_WB_RD_COMM 4'h1
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`define DBG_WB_RD_COMM 4'h1
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`define DBG_WB_WR_COMM 4'h2
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`define DBG_WB_WR_COMM 4'h2
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// Defining access types for wishbone
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// Defining access types for wishbone
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`define DBG_WB_WRITE8 4'h0
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`define DBG_WB_WRITE8 4'h0
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`define DBG_WB_WRITE16 4'h1
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`define DBG_WB_WRITE16 4'h1
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`define DBG_WB_WRITE32 4'h2
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`define DBG_WB_WRITE32 4'h2
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`define DBG_WB_READ8 4'h4
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`define DBG_WB_READ8 4'h4
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`define DBG_WB_READ16 4'h5
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`define DBG_WB_READ16 4'h5
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`define DBG_WB_READ32 4'h6
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`define DBG_WB_READ32 4'h6
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// dbg_cpu_defines.v
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// dbg_cpu_defines.v
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// Defining length of the command
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// Defining length of the command
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`define DBG_CPU_CMD_LEN 3'd4
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`define DBG_CPU_CMD_LEN 3'd4
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`define DBG_CPU_CMD_CNT_WIDTH 3
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`define DBG_CPU_CMD_CNT_WIDTH 3
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// Defining length of the access_type field
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// Defining length of the access_type field
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`define DBG_CPU_ACC_TYPE_LEN 3'd4
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`define DBG_CPU_ACC_TYPE_LEN 3'd4
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// Defining length of the address
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// Defining length of the address
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`define DBG_CPU_ADR_LEN 6'd32
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`define DBG_CPU_ADR_LEN 6'd32
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// Defining length of the length register
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// Defining length of the length register
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`define DBG_CPU_LEN_LEN 5'd16
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`define DBG_CPU_LEN_LEN 5'd16
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// Defining total length of the DR needed
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// Defining total length of the DR needed
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//define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
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//define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
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`define DBG_CPU_DR_LEN 52
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`define DBG_CPU_DR_LEN 52
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// Defining length of the CRC
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// Defining length of the CRC
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`define DBG_CPU_CRC_LEN 6'd32
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`define DBG_CPU_CRC_LEN 6'd32
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`define DBG_CPU_CRC_CNT_WIDTH 6
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`define DBG_CPU_CRC_CNT_WIDTH 6
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// Defining length of status
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// Defining length of status
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`define DBG_CPU_STATUS_LEN 3'd4
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`define DBG_CPU_STATUS_LEN 3'd4
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`define DBG_CPU_STATUS_CNT_WIDTH 3
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`define DBG_CPU_STATUS_CNT_WIDTH 3
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// Defining length of the data
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// Defining length of the data
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//define DBG_CPU_DATA_CNT_WIDTH `DBG_CPU_LEN_LEN + 3
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//define DBG_CPU_DATA_CNT_WIDTH `DBG_CPU_LEN_LEN + 3
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`define DBG_CPU_DATA_CNT_WIDTH 19
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`define DBG_CPU_DATA_CNT_WIDTH 19
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//define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN
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//define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN
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`define DBG_CPU_DATA_CNT_LIM_WIDTH 16
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`define DBG_CPU_DATA_CNT_LIM_WIDTH 16
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// Defining length of the control register
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// Defining length of the control register
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`define DBG_CPU_CTRL_LEN 2
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`define DBG_CPU_CTRL_LEN 2
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//Defining commands
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//Defining commands
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`define DBG_CPU_GO 4'h0
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`define DBG_CPU_GO 4'h0
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`define DBG_CPU_RD_COMM 4'h1
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`define DBG_CPU_RD_COMM 4'h1
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`define DBG_CPU_WR_COMM 4'h2
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`define DBG_CPU_WR_COMM 4'h2
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`define DBG_CPU_RD_CTRL 4'h3
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`define DBG_CPU_RD_CTRL 4'h3
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`define DBG_CPU_WR_CTRL 4'h4
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`define DBG_CPU_WR_CTRL 4'h4
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// Defining access types for wishbone
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// Defining access types for wishbone
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`define DBG_CPU_WRITE 4'h2
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`define DBG_CPU_WRITE 4'h2
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`define DBG_CPU_READ 4'h6
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`define DBG_CPU_READ 4'h6
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// commands from jp_vpi
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// commands from jp_vpi
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`define CMD_JTAG_SET_IR 4'h1
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`define CMD_JTAG_SET_IR 4'h1
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`define CMD_SET_DEBUG_CHAIN 4'h2
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`define CMD_SET_DEBUG_CHAIN 4'h2
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`define CMD_CPU_CTRL_WR 4'h3
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`define CMD_CPU_CTRL_WR 4'h3
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`define CMD_CPU_CTRL_RD 4'h4
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`define CMD_CPU_CTRL_RD 4'h4
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`define CMD_CPU_WR_REG 4'h5
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`define CMD_CPU_WR_REG 4'h5
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`define CMD_CPU_RD_REG 4'h6
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`define CMD_CPU_RD_REG 4'h6
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`define CMD_WB_WR 4'h7
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`define CMD_WB_WR 4'h7
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`define CMD_WB_RD32 4'h8
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`define CMD_WB_RD32 4'h8
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`define CMD_WB_BLOCK_WR32 4'h9
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`define CMD_WB_BLOCK_WR32 4'h9
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`define CMD_WB_BLOCK_RD32 4'ha
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`define CMD_WB_BLOCK_RD32 4'ha
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`define CMD_RESET 4'hb
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`define CMD_RESET 4'hb
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`define CMD_READ_JTAG_ID 4'hc
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`define CMD_READ_JTAG_ID 4'hc
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`define CMD_GDB_DETACH 4'hd
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`define CMD_GDB_DETACH 4'hd
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`define CMD_WB_RD8 4'he /* Byte read is useful with a system with byte peripherals! */
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// commands:
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// commands:
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// 4'h1 jtag set instruction register (input: instruction value)
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// 4'h1 jtag set instruction register (input: instruction value)
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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
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// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
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// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
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// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
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// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
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// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
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// 4'h5 cpu wr reg (inputs: address, data)
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// 4'h5 cpu wr reg (inputs: address, data)
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// 4'h6 cpu rd reg (input: address; output: data)
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// 4'h6 cpu rd reg (input: address; output: data)
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// 4'h7 wb wr (inputs: address, size, data)
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// 4'h7 wb wr (inputs: address, size, data)
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// 4'h8 wb rd 32 (input: address; output: data)
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// 4'h8 wb rd 32 (input: address; output: data)
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// 4'h9 wb wr block 32 (inputs: address, length, data)
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// 4'h9 wb wr block 32 (inputs: address, length, data)
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// 4'ha wb rd block 32 (inputs: address, length; output: data)
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// 4'ha wb rd block 32 (inputs: address, length; output: data)
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// 4'hb reset
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// 4'hb reset
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// 4'hc read jtag id (output: data)
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// 4'hc read jtag id (output: data)
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`define SDRAM_BASE_ADDRESS 32'h00000000
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`define SDRAM_BASE_ADDRESS 32'h00000000
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