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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [Makefile.inc] - Diff between revs 480 and 485

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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [actel/] [ordb1a3pe1500/] [sw/] [Makefile.inc] - Diff between revs 480 and 485

Rev 480	Rev 485

`# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're`	`# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're`
`# in the board's software root path is.`	`# in the board's software root path is.`

`# Root from the board's sw/ path`	`# Root from the board's sw/ path`
`PROJ_ROOT=../../../..`	`PROJ_ROOT=../../../..`

`# Figure out actual path the common software directory`	`# Figure out actual path the common software directory`
`SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw`	`SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw`

`# Set the BOARD_PATH to point to the root of this board build`	`# Set the BOARD to be the path within the board/ path of the project that goes`
	`# to this project.`
`BOARD=actel/ordb1a3pe1500`	`BOARD=actel/ordb1a3pe1500`

`# Set RTL_VERILOG_INCLUDE_DIR so software`	`# Set RTL_VERILOG_INCLUDE_DIR so software`
`RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include`	`RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include`

`# Set the processor capability flags`	`# Set the processor capability flags`
`#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float`	`#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float`
`MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float`	`MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float`
`export MARCH_FLAGS`	`export MARCH_FLAGS`

`# Finally include the main software include file`	`# Finally include the main software include file`

`include $(SW_ROOT)/Makefile.inc`	`include $(SW_ROOT)/Makefile.inc`