######################################################################
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######################################################################
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#### ####
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#### ####
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#### ORPSoC Xilinx Synthesis Makefile ####
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#### ORPSoC Xilinx Synthesis Makefile ####
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#### ####
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#### ####
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#### Author(s): ####
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#### Author(s): ####
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#### - Julius Baxter, julius@opencores.org ####
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#### - Julius Baxter, julius@opencores.org ####
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#### ####
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#### ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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#### ####
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#### ####
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#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
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#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
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#### ####
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#### ####
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#### This source file may be used and distributed without ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### later version. ####
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#### ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### details. ####
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#### ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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# Name of the directory we're currently in
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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# We don't want the usbhostslave module to be pulled in during synthesis because
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# We don't want the usbhostslave module to be pulled in during synthesis because
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# we haven't copied the headers to our RTL director
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# we haven't copied the headers to our RTL director
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#COMMON_VERILOG_MODULES_EXCLUDE+= usbhostslave
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#COMMON_VERILOG_MODULES_EXCLUDE+= usbhostslave
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# The root path of the board build
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# The root path of the board build
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BOARD_ROOT ?=$(CUR_DIR)/../../..
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BOARD_ROOT ?=$(CUR_DIR)/../../..
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include $(BOARD_ROOT)/Makefile.inc
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include $(BOARD_ROOT)/Makefile.inc
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RTL_TOP ?=$(DESIGN_NAME)_top
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RTL_TOP ?=$(DESIGN_NAME)_top
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SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
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SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
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TIMESCALE_FILE=timescale.v
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TIMESCALE_FILE=timescale.v
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SYNDIR_TIMESCALE_FILE=$(SYN_RUN_DIR)/$(TIMESCALE_FILE)
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SYNDIR_TIMESCALE_FILE=$(SYN_RUN_DIR)/$(TIMESCALE_FILE)
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$(SYNDIR_TIMESCALE_FILE):
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$(SYNDIR_TIMESCALE_FILE):
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$(Q)echo "" > $@
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$(Q)echo "" > $@
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SYN_VERILOG_DEFINES=synthesis-defines.v
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SYN_VERILOG_DEFINES=synthesis-defines.v
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SYNDIR_SYN_VERILOG_DEFINES=$(SYN_RUN_DIR)/$(SYN_VERILOG_DEFINES)
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SYNDIR_SYN_VERILOG_DEFINES=$(SYN_RUN_DIR)/$(SYN_VERILOG_DEFINES)
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$(SYNDIR_SYN_VERILOG_DEFINES):
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$(SYNDIR_SYN_VERILOG_DEFINES):
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$(Q)echo "\`define SYNTHESIS" > $@
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$(Q)echo "\`define SYNTHESIS" > $@
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$(Q)echo "\`define XILINX" >> $@
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$(Q)echo "\`define XILINX" >> $@
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$(Q)echo "" >> $@
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$(Q)echo "" >> $@
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GENERATED_DEFINES = $(BOOTROM_VERILOG)
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GENERATED_DEFINES = $(BOOTROM_VERILOG)
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GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE)
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GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE)
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GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES)
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GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES)
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FPGA_PART ?=xc6slx45-2-csg324
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FPGA_PART ?=xc6slx45-2-csg324
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OPT_MODE ?=Speed
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OPT_MODE ?=Speed
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OPT_LEVEL ?=2
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OPT_LEVEL ?=2
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ifeq ($(V), 1)
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ifeq ($(V), 1)
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XILINX_FLAGS ?=
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XILINX_FLAGS ?=
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else
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else
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XILINX_FLAGS ?=-intstyle silent
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XILINX_FLAGS ?=-intstyle silent
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endif
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endif
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XILINX_XST_FLAGS ?= -power NO -glob_opt AllClockNets -write_timing_constraints NO -cross_clock_analysis NO -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -auto_bram_packing NO -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -async_to_sync NO -use_dsp48 auto -iobuf YES -max_fanout 100000 -bufg 32 -register_duplication YES -equivalent_register_removal YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -slice_utilization_ratio_maxmargin 5
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XILINX_XST_FLAGS ?= -power NO -glob_opt AllClockNets -write_timing_constraints NO -cross_clock_analysis NO -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -auto_bram_packing NO -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -async_to_sync NO -use_dsp48 auto -iobuf YES -max_fanout 100000 -bufg 32 -register_duplication YES -equivalent_register_removal YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -slice_utilization_ratio_maxmargin 5
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XCF_FILE=$(DESIGN_NAME).xcf
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XCF_FILE=$(DESIGN_NAME).xcf
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XST_FILE=$(DESIGN_NAME).xst
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XST_FILE=$(DESIGN_NAME).xst
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PRJ_FILE=$(DESIGN_NAME).prj
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PRJ_FILE=$(DESIGN_NAME).prj
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NGC_FILE=$(DESIGN_NAME).ngc
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NGC_FILE=$(DESIGN_NAME).ngc
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NETLIST_FILE=$(DESIGN_NAME).v
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NETLIST_FILE=$(DESIGN_NAME).v
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COREGEN_DIR=$(BOARD_SYN_DIR)/coregen
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COREGEN_DIR=$(BOARD_SYN_DIR)/coregen
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COREGEN_CGP_FILE=$(COREGEN_DIR)/coregen.cgp
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COREGEN_CGP_FILE=$(COREGEN_DIR)/coregen.cgp
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COREGEN_XCO_FILES=$(shell ls $(COREGEN_DIR)/*.xco)
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COREGEN_XCO_FILES=$(shell ls $(COREGEN_DIR)/*.xco)
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XST_PRJ_FILE_SRC_DECLARE=verilog work
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XST_PRJ_FILE_SRC_DECLARE=verilog work
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print-config:
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print-config:
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$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
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$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
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$(Q)echo "\tFPGA_PART="$(FPGA_PART)
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$(Q)echo "\tFPGA_PART="$(FPGA_PART)
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$(Q)echo "\tOPT_MODE="$(OPT_MODE)
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$(Q)echo "\tOPT_MODE="$(OPT_MODE)
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$(Q)echo "\tOTP_LEVEL="$(OPT_LEVEL)
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$(Q)echo "\tOTP_LEVEL="$(OPT_LEVEL)
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$(Q)echo "\tXILINX_XST_FLAGS="$(XILINX_XST_FLAGS)
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$(Q)echo "\tXILINX_XST_FLAGS="$(XILINX_XST_FLAGS)
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$(Q)echo
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$(Q)echo
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all: $(NGC_FILE)
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all: $(NGC_FILE)
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# Generate the .xst file
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# Generate the .xst file
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# See this page for information on options:
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# See this page for information on options:
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# http://www.xilinx.com/itp/xilinx4/data/docs/xst/command_line5.html
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# http://www.xilinx.com/itp/xilinx4/data/docs/xst/command_line5.html
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$(XST_FILE):
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$(XST_FILE):
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$(Q)echo; echo "\t#### Generating XST file ####"; echo
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$(Q)echo; echo "\t#### Generating XST file ####"; echo
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$(Q)echo "# XST Script for ORPSoC Synthesis" > $@
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$(Q)echo "# XST Script for ORPSoC Synthesis" > $@
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$(Q)echo "# This file is autogenerated - any changes will be overwritten" >> $@
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$(Q)echo "# This file is autogenerated - any changes will be overwritten" >> $@
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$(Q)echo "# See the Makefile in syn/xst/bin to make changes" >> $@
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$(Q)echo "# See the Makefile in syn/xst/bin to make changes" >> $@
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$(Q)echo "run" >> $@
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$(Q)echo "run" >> $@
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$(Q)echo "-ifn "$(PRJ_FILE) >> $@
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$(Q)echo "-ifn "$(PRJ_FILE) >> $@
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$(Q)echo "-ifmt mixed" >> $@
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$(Q)echo "-ifmt mixed" >> $@
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$(Q)echo "-top "$(RTL_TOP) >> $@
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$(Q)echo "-top "$(RTL_TOP) >> $@
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$(Q)echo "-ofmt NGC" >> $@
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$(Q)echo "-ofmt NGC" >> $@
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$(Q)echo "-ofn "$(NGC_FILE) >> $@
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$(Q)echo "-ofn "$(NGC_FILE) >> $@
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$(Q)echo "-p "$(FPGA_PART) >> $@
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$(Q)echo "-p "$(FPGA_PART) >> $@
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$(Q)echo "-opt_level "$(OPT_LEVEL) >> $@
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$(Q)echo "-opt_level "$(OPT_LEVEL) >> $@
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$(Q)echo "-opt_mode "$(OPT_MODE) >> $@
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$(Q)echo "-opt_mode "$(OPT_MODE) >> $@
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$(Q)echo "-uc "$(XCF_FILE) >> $@
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$(Q)echo "-uc "$(XCF_FILE) >> $@
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# $(Q)echo "elaborate " >> $@
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# $(Q)echo "elaborate " >> $@
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# $(Q)echo -n "-vlgpath \"" >> $@
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# $(Q)echo -n "-vlgpath \"" >> $@
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# option missing from XST - wtf?! $(Q)for vlogpath in $(VERILOG_SRC_PATHS); do \
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# option missing from XST - wtf?! $(Q)for vlogpath in $(VERILOG_SRC_PATHS); do \
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echo -n $$vlogpath" "; done >> $@
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echo -n $$vlogpath" "; done >> $@
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# $(Q)echo "\"" >> $@
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# $(Q)echo "\"" >> $@
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# Give board then common verilog include paths, hoping xst does a sensible thing
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# Give board then common verilog include paths, hoping xst does a sensible thing
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# and searches them in order.
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# and searches them in order.
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$(Q)echo "-vlgincdir { "$(BOARD_RTL_VERILOG_INCLUDE_DIR)" "$(COMMON_RTL_VERILOG_DIR)/include" "$(BOOTROM_SW_DIR) " }" >> $@
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$(Q)echo "-vlgincdir { "$(BOARD_RTL_VERILOG_INCLUDE_DIR)" "$(COMMON_RTL_VERILOG_DIR)/include" "$(BOOTROM_SW_DIR) " }" >> $@
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$(Q)echo >> $@
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$(Q)echo >> $@
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# Generate Xilinx project (.prj) file
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# Generate Xilinx project (.prj) file
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$(PRJ_FILE): $(RTL_VERILOG_SRC)
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$(PRJ_FILE): $(RTL_VERILOG_SRC)
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$(Q)echo; echo "\t#### Generating Xilinx PRJ file ####";
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$(Q)echo; echo "\t#### Generating Xilinx PRJ file ####";
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# $(Q)echo "# Autogenerated XST .prj file" > $@
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# $(Q)echo "# Autogenerated XST .prj file" > $@
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# $(Q)echo "# Any changes will be written over." >> $@
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# $(Q)echo "# Any changes will be written over." >> $@
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$(Q)for file in $(RTL_VERILOG_SRC); do \
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$(Q)for file in $(RTL_VERILOG_SRC); do \
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echo $(XST_PRJ_FILE_SRC_DECLARE) $$file >> $@ ; \
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echo $(XST_PRJ_FILE_SRC_DECLARE) $$file >> $@ ; \
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done
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done
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$(Q)echo >> $@
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$(Q)echo >> $@
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$(Q)echo
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$(Q)echo
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# Constraints file
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# Constraints file
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$(XCF_FILE):
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$(XCF_FILE):
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$(Q)echo; echo "\t#### Generating Xilinx XCF file ####"; echo
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$(Q)echo; echo "\t#### Generating Xilinx XCF file ####"; echo
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$(Q)echo "# Autogenerated XST .prj file" > $@
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$(Q)echo "# Autogenerated XST .prj file" > $@
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$(Q)echo "#" >> $@
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$(Q)echo "#" >> $@
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$(Q)echo "# Not much here, XST is smart enough to determine clocks through DCMs" >> $@
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$(Q)echo "# Not much here, XST is smart enough to determine clocks through DCMs" >> $@
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$(Q)echo "#" >> $@
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$(Q)echo "#" >> $@
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$(Q)echo "# 100 MHz user clock" >> $@
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$(Q)echo "# 100 MHz user clock" >> $@
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$(Q)echo "NET \"sys_clk_in\" TNM_NET = \"sys_clk_in_grp\";" >> $@
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$(Q)echo "NET \"sys_clk_in\" TNM_NET = \"sys_clk_in_grp\";" >> $@
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$(Q)echo "TIMESPEC \"TS_sys_clk_in\" = PERIOD \"sys_clk_in_grp\" 10 ns HIGH 50%;" >> $@
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$(Q)echo "TIMESPEC \"TS_sys_clk_in\" = PERIOD \"sys_clk_in_grp\" 10 ns HIGH 50%;" >> $@
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$(Q)echo "# Ignore the reset logic" >> $@
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$(Q)echo "# Ignore the reset logic" >> $@
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$(Q)echo "NET rst_n_pad_i* TIG;" >> $@
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$(Q)echo "NET rst_n_pad_i* TIG;" >> $@
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$(Q)echo "# Define the two clock domains as timespecs" >> $@
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$(Q)echo "# Define the two clock domains as timespecs" >> $@
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$(Q)echo "#NET dcm0_clkdv TNM_NET=\"wb_clk\";" >> $@
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$(Q)echo "#NET dcm0_clkdv TNM_NET=\"wb_clk\";" >> $@
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$(Q)echo "#TIMESPEC \"TS_wb_clk\" = PERIOD \"wb_clk\" 20 ns HIGH 10;" >> $@
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$(Q)echo "#TIMESPEC \"TS_wb_clk\" = PERIOD \"wb_clk\" 20 ns HIGH 10;" >> $@
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# Generate coregen cores
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# Generate coregen cores
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coregen:
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coregen:
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$(Q)echo; echo "#### Running CORE Gen ####"; echo
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$(Q)echo; echo "#### Running CORE Gen ####"; echo
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$(Q)(. $(XILINX_SETTINGS_SCRIPT))
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$(Q)$(shell cp $(COREGEN_XCO_FILES) .)
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$(Q)$(shell cp $(COREGEN_XCO_FILES) .)
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$(Q)$(shell cp $(COREGEN_CGP_FILE) .)
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$(Q)$(shell cp $(COREGEN_CGP_FILE) .)
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$(Q)for file in $(COREGEN_XCO_FILES); do \
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$(Q)for file in $(COREGEN_XCO_FILES); do \
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coregen -b $(notdir $$file) -p $(notdir $(COREGEN_CGP_FILE)) $(XILINX_FLAGS); \
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coregen -b $(notdir $$file) -p $(notdir $(COREGEN_CGP_FILE)) $(XILINX_FLAGS); \
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done
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done
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# XST command
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# XST command
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$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES) coregen
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$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES) coregen
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$(Q)echo; echo "\t#### Running XST ####"; echo;
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$(Q)echo; echo "\t#### Running XST ####"; echo;
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
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$(Q)xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS)
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$(Q)echo
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$(Q)echo
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netlist: $(NETLIST_FILE)
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netlist: $(NETLIST_FILE)
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# Netlist generation command
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# Netlist generation command
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$(NETLIST_FILE): $(NGC_FILE)
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$(NETLIST_FILE): $(NGC_FILE)
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$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;
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$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;
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$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \
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$(Q)netgen -sim -aka -dir . -ofmt verilog $< -w $@
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netgen -sim -aka -dir . -ofmt verilog $< -w $@ )
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clean:
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clean:
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$(Q)rm -rf *.* xst tmp _xmsgs xlnx_auto* *.lso
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$(Q)rm -rf *.* xst tmp _xmsgs xlnx_auto* *.lso
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clean-sw:
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clean-sw:
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$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean
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$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean
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distclean: clean-sw clean
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distclean: clean-sw clean
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.PRECIOUS : $(NGC_FILE) $(XST_FILE) $(XCF_FILE)
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.PRECIOUS : $(NGC_FILE) $(XST_FILE) $(XCF_FILE)
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