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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Ethernet MAC Stimulus ////
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//// ////
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//// Description ////
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//// Ethernet MAC stimulus tasks. Taken from the project ////
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//// testbench in the ethmac core. ////
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//// ////
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//// To Do: ////
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//// ////
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//// ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// - Igor Mohor, igorM@opencores.org ////
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//// - Julius Baxter julius.baxter@orsoc.se ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`define TIME $display("Time: %0t", $time)
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// Defines for ethernet test to trigger sending/receiving
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// Is straight forward when using RTL design, but if using netlist then paths to
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// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to
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// work with design put through Synplify, with hierarchy maintained.
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`define ETH_TOP dut.ethmac0
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`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram
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`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0
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`ifdef RTL_SIM
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`ifdef ethmac_IS_GATELEVEL
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`define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
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`define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
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`else
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`define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.DataOut[1];
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`define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.DataOut[0];
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`endif
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`endif
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`ifdef GATE_SIM
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`define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
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`define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
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`endif
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reg [15:0] eth_stim_rx_packet_length;
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reg [7:0] st_data;
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reg [31:0] lfsr;
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integer lfsr_last_byte;
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// Is number of ethernet packets to send if doing the eth-rx test.
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parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
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parameter eth_stim_num_rx_only_packet_size = 512;
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parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
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parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
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parameter eth_stim_num_rx_only_IPG = 800000; // ns
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// Do call/response test
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reg eth_stim_do_rx_reponse_to_tx;
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parameter num_tx_bds = 16;
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parameter num_tx_bds_mask = 4'hf;
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parameter num_rx_bds = 16;
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parameter num_rx_bds_mask = 4'hf;
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parameter max_eth_packet_size = 16'h0600;
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// If running eth-rxtxbig test (sending and receiving maximum packets), then
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// set this parameter to the max packet size, otherwise min packet size
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//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
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parameter rx_while_tx_min_packet_size = 32;
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// Use the smallest possible IPG
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parameter eth_stim_use_min_IPG = 0;
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parameter eth_stim_IPG_delay_max = 500_000; // Maximum 500uS ga
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//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
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parameter eth_stim_IPG_min_10mb = 9600; // 9.6 uS
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parameter eth_stim_IPG_min_100mb = 800; // 860+~100 = 960 nS 100MBit min IPG
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parameter eth_stim_check_rx_packet_contents = 1;
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parameter eth_stim_check_tx_packet_contents = 1;
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parameter eth_inject_errors = 0;
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// When running simulations where you don't want to feed packets to the design
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// like this...
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parameter eth_stim_disable_rx_stim = 0;
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// Delay between seeing that the buffer descriptor for an RX packet says it's
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// been received and ending up in the memory.
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// For 25MHz sdram controller, use following:
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//parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 2000);
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// For 64MHz sdram controller, use following:
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parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
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integer expected_rxbd;// init to 0
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integer expected_txbd;
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wire ethmac_rxen;
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wire ethmac_txen;
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assign ethmac_rxen = eth_stim_disable_rx_stim ? 0 : `ETH_MODER_RXEN_BIT;
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assign ethmac_txen = `ETH_MODER_TXEN_BIT;
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integer eth_rx_num_packets_sent = 0;
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integer eth_rx_num_packets_checked = 0;
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integer num_tx_packets = 1;
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integer rx_packet_lengths [0:1023]; // Array of packet lengths
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integer speed_loop;
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// When txen is (re)enabled, the tx bd pointer goes back to 0
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always @(posedge ethmac_txen)
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expected_txbd = 0;
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reg eth_stim_waiting;
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initial
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begin
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#1;
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//lfsr = 32'h84218421; // Init pseudo lfsr
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lfsr = 32'h00700001; // Init pseudo lfsr
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lfsr_last_byte = 0;
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eth_stim_waiting = 1;
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expected_rxbd = num_tx_bds; // init this here
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eth_stim_do_rx_reponse_to_tx = 0;
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while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
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begin
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#100;
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// If RX enable and not TX enable...
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if(ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
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begin
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if (eth_inject_errors)
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begin
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do_rx_only_stim(16, 64, 0, 0);
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do_rx_only_stim(128, 64, 1'b1, 8);
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do_rx_only_stim(256, 64, 1'b1, 4);
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eth_stim_waiting = 0;
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end
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else
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begin
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//do_rx_only_stim(eth_stim_num_rx_only_num_packets,
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//eth_stim_num_rx_only_packet_size, 0, 0);
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// Call packet send loop directly. No error injection.
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send_packet_loop(eth_stim_num_rx_only_num_packets,
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eth_stim_num_rx_only_packet_size,
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eth_stim_num_rx_only_packet_size_change,
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eth_stim_num_rx_only_packet_size_change_amount,
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eth_phy0.eth_speed, // Speed
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eth_stim_num_rx_only_IPG, // IPG
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48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
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0, 0);
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eth_stim_waiting = 0;
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end
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end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
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// If both RX and TX enabled
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else if (ethmac_rxen === 1'b1 & ethmac_txen===1'b1)
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begin
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// Both enabled - let's wait for the first packet transmitted
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// to see what stimulus we should provide
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while (num_tx_packets==1)
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#1000;
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$display("* ethmac RX/TX test request: %x", eth_phy0.tx_mem[0]);
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// Check the first received byte's value
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case (eth_phy0.tx_mem[0])
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0:
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begin
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// kickoff call/response here
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eth_stim_do_rx_reponse_to_tx = 1;
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end
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default:
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begin
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do_rx_while_tx_stim(1400);
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end
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endcase // case (eth_phy0.tx_mem[0])
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eth_stim_waiting = 0;
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end
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end // while (eth_stim_waiting)
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end // initial begin
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// Main Ethernet RX testing stimulus task.
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// Sends a set of packets at both speeds
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task do_rx_only_stim;
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input [31:0] num_packets;
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input [31:0] start_packet_size;
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input inject_errors;
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input [31:0] inject_errors_mod;
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begin
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for(speed_loop=1;speed_loop<3;speed_loop=speed_loop+1)
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begin
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send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
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speed_loop[0], 10000,
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48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
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inject_errors, inject_errors_mod);
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end
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end
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endtask // do_rx_stim
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// Generate RX packets while there's TX going on
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// Sends a set of packets at both speeds
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task do_rx_while_tx_stim;
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input [31:0] num_packets;
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reg [31:0] IPG; // Inter-packet gap
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reg [31:0] packet_size;
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integer j;
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begin
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for(j=0;j<num_packets;j=j+1)
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begin
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// Determine delay between RX packets:
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if (eth_stim_use_min_IPG)
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begin
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// Assign based on whether we're in 100mbit or 10mbit mode
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IPG = eth_phy0.eth_speed ? eth_stim_IPG_min_100mb :
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eth_stim_IPG_min_10mb;
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// Add a little bit of variability
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// Add up to 15
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IPG = IPG + ($random & 32'h000000f);
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end
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else
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begin
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IPG = $random;
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while (IPG > eth_stim_IPG_delay_max)
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IPG = IPG / 2;
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end
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$display("do_rx_while_tx IPG = %0d", IPG);
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// Determine size of next packet:
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if (rx_while_tx_min_packet_size == max_eth_packet_size)
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// We want to transmit biggest packets possible, easy case
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packet_size = max_eth_packet_size - 4;
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else
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begin
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// Constrained random sized packets
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packet_size = $random;
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while (packet_size > (max_eth_packet_size-4))
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packet_size = packet_size / 2;
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// Now divide by least significant bits of j
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packet_size = packet_size / {29'd0,j[1:0],1'b1};
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if (packet_size < 60)
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packet_size = packet_size + 60;
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end
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$display("do_rx_while_tx packet_size = %0d", packet_size);
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send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
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IPG, 48'h0012_3456_789a,
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48'h0708_090A_0B0C, 1, 1'b0, 0);
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// If RX enable went low, wait for it go high again
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if (ethmac_rxen===1'b0)
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begin
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while (ethmac_rxen===1'b0)
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begin
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@(posedge ethmac_rxen);
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#10000;
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end
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// RX disabled and when re-enabled we reset the buffer descriptor number
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expected_rxbd = num_tx_bds;
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end
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end // for (j=0;j<num_packets;j=j+1)
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end
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endtask // do_rx_stim
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// Registers used in detecting transmitted packets
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reg eth_stim_tx_loop_keep_polling;
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reg [31:0] ethmac_txbd_lenstat, ethmac_last_txbd_lenstat;
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reg eth_stim_detected_packet_tx;
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// If in call-response mode, whenever we receive a TX packet, we generate
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// one and send it back
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always @(negedge eth_stim_detected_packet_tx)
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begin
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if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
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// Continue if we are enabled
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do_rx_response_to_tx();
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end
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// Generate RX packet in rsponse to TX packet
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task do_rx_response_to_tx;
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//input unused;
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reg [31:0] IPG; // Inter-packet gap
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reg [31:0] packet_size;
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integer j;
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begin
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// Get packet size test wants us to send
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packet_size = {eth_phy0.tx_mem[0],eth_phy0.tx_mem[1],
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eth_phy0.tx_mem[2],eth_phy0.tx_mem[3]};
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IPG = {eth_phy0.tx_mem[4],eth_phy0.tx_mem[5],
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eth_phy0.tx_mem[6],eth_phy0.tx_mem[7]};
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$display("do_rx_response_to_tx IPG = %0d", IPG);
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if (packet_size == 0)
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begin
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// Constrained random sized packets
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packet_size = $random;
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while (packet_size > (max_eth_packet_size-4))
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packet_size = packet_size / 2;
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if (packet_size < 60)
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packet_size = packet_size + 60;
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end
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$display("do_rx_response_to_tx packet_size = %0d", packet_size);
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send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
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IPG, 48'h0012_3456_789a,
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48'h0708_090A_0B0C, 1, 1'b0, 0);
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// If RX enable went low, wait for it go high again
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if (ethmac_rxen===1'b0)
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begin
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while (ethmac_rxen===1'b0)
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begin
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@(posedge ethmac_rxen);
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#10000;
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end
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// RX disabled and when re-enabled we reset the buffer
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// descriptor number
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expected_rxbd = num_tx_bds;
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end
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end
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endtask // do_rx_response_to_tx
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//
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// always@() to check the TX buffer descriptors
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//
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always @(posedge ethmac_txen)
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begin
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ethmac_last_txbd_lenstat = 0;
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eth_stim_tx_loop_keep_polling=1;
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// Wait on the TxBD Ready bit
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while(eth_stim_tx_loop_keep_polling)
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begin
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#10;
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get_bd_lenstat(expected_txbd, ethmac_txbd_lenstat);
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// Check if we've finished transmitting this BD
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if (!ethmac_txbd_lenstat[15] & ethmac_last_txbd_lenstat[15])
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// Falling edge of TX BD Ready
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eth_stim_detected_packet_tx = 1;
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ethmac_last_txbd_lenstat = ethmac_txbd_lenstat;
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// If TX en goes low then exit
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if (!ethmac_txen)
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eth_stim_tx_loop_keep_polling = 0;
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else if (eth_stim_detected_packet_tx)
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begin
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// Wait until the eth_phy has finished receiving it
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while (eth_phy0.mtxen_i === 1'b1)
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#10;
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$display("(%t) Check TX packet: bd %d: 0x%h",$time,
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expected_txbd, ethmac_txbd_lenstat);
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// Check the TXBD, see if the packet transmitted OK
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if (ethmac_txbd_lenstat[8] | ethmac_txbd_lenstat[3])
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begin
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// Error occured
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`TIME;
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$display("*E TX Error of packet %0d detected.",
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num_tx_packets);
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$display(" TX BD %0d = 0x%h", expected_txbd,
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ethmac_txbd_lenstat);
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if (ethmac_txbd_lenstat[8])
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$display(" Underrun in MAC during TX");
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if (ethmac_txbd_lenstat[3])
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$display(" Retransmission limit hit");
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$finish;
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end
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else
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begin
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// Packet was OK, let's compare the contents we
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// received with those that were meant to be transmitted
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if (eth_stim_check_tx_packet_contents)
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begin
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check_tx_packet(expected_txbd);
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expected_txbd = (expected_txbd + 1) &
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num_tx_bds_mask;
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num_tx_packets = num_tx_packets + 1;
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eth_stim_detected_packet_tx = 0;
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end
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end
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end
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end // while (eth_stim_tx_loop_keep_polling)
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end // always @ (posedge ethmac_txen)
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//
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// Check packet TX'd by MAC was good
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//
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task check_tx_packet;
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input [31:0] tx_bd_num;
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reg [31:0] tx_bd_addr;
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reg [7:0] phy_byte;
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reg [31:0] txpnt_wb; // Pointer in array to where data should be
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reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM
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// part
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reg [21:0] buffer;
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reg [7:0] sdram_byte;
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reg [31:0] tx_len_bd;
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integer i;
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integer failure;
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begin
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failure = 0;
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get_bd_lenstat(tx_bd_num, tx_len_bd);
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tx_len_bd = {15'd0,tx_len_bd[31:16]};
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// Check, if length didn't have to be padded, that
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// amount transmitted was correct
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if ((tx_len_bd > 60)&(tx_len_bd != (eth_phy0.tx_len-4)))
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begin
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$display("*E TX packet sent length, %0d != length in TX BD, %0d",
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eth_phy0.tx_len-4, tx_len_bd);
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#100;
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$finish;
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end
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get_bd_addr(tx_bd_num, tx_bd_addr);
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// We're never going to be using more than about 256K of receive buffer
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// so let's lop off the top bit of the address pointer - we only want
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// the offset from the base of the memory bank
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txpnt_wb = {14'd0,tx_bd_addr[17:0]};
|
|
txpnt_sdram = tx_bd_addr[24:0];
|
|
|
|
// Variable we'll use for index in the PHY's TX buffer
|
|
buffer = 0; // Start of TX data
|
|
`ifdef VERSATILE_SDRAM
|
|
for (i=0;i<tx_len_bd;i=i+1)
|
|
begin
|
|
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
|
|
|
|
sdram0.get_byte(txpnt_sdram,sdram_byte);
|
|
|
|
phy_byte = eth_phy0.tx_mem[buffer];
|
|
// Debugging output
|
|
//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte);
|
|
if (phy_byte !== sdram_byte)
|
|
begin
|
|
`TIME;
|
|
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
|
|
failure = 1;
|
|
end
|
|
|
|
buffer = buffer + 1;
|
|
|
|
txpnt_sdram = txpnt_sdram+1;
|
|
|
|
end // for (i=0;i<tx_len_bd;i=i+1)
|
|
|
|
`else
|
|
$display("SET ME UP TO LOOK IN ANOTHER MEMORY!");
|
|
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
|
|
tx_bd_addr, txpnt_wb);
|
|
$finish;
|
|
`endif // !`ifdef VERSATILE_SDRAM
|
|
if (failure)
|
|
begin
|
|
#100
|
|
`TIME;
|
|
$display("*E Error transmitting packet %0d (%0d bytes). Finishing simulation", num_tx_packets, tx_len_bd);
|
|
get_bd_lenstat(tx_bd_num, tx_len_bd);
|
|
$display(" TXBD lenstat: 0x%0h",tx_len_bd);
|
|
$display(" TXBD address: 0x%0h",tx_bd_addr);
|
|
$finish;
|
|
end
|
|
else
|
|
begin
|
|
#1 $display( "(%0t)(%m) TX packet %0d: %0d bytes in memory OK!",$time,num_tx_packets, tx_len_bd);
|
|
|
|
end
|
|
|
|
|
|
end
|
|
endtask // check_tx_packet
|
|
|
|
//
|
|
// Task to send a set of packets
|
|
//
|
|
task send_packet_loop;
|
|
input [31:0] num_packets;
|
|
input [31:0] length;
|
|
input [1:0] length_change; // 0 = none, 1 = incr, 2 = decrement
|
|
input [31:0] length_change_size; // Size to change by
|
|
input speed;
|
|
input [31:0] back_to_back_delay; // #delay setting between packets
|
|
input [47:0] dst_mac;
|
|
input [47:0] src_mac;
|
|
input random_fill;
|
|
input random_errors;
|
|
input [31:0] random_error_mod;
|
|
integer j;
|
|
reg error_this_time;
|
|
integer error_type; // 0 = rxerr, 1=bad preamble 2=bad crc 3=TODO
|
|
reg [31:0] rx_bd_lenstat;
|
|
begin
|
|
error_type = 0;
|
|
error_this_time = 0;
|
|
|
|
if (num_packets == 0)
|
|
// Loop forever when num_packets is 0
|
|
num_packets = 32'h7fffffff;
|
|
|
|
|
|
if (speed & !(eth_phy0.control_bit14_10[13] === 1'b1))
|
|
begin
|
|
// write to phy's control register for 100Mbps
|
|
eth_phy0.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
|
|
// Swapping speeds, give some delay
|
|
#10000;
|
|
end
|
|
else if (!speed & !(eth_phy0.control_bit14_10[13] === 1'b0))
|
|
begin
|
|
eth_phy0.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
|
|
// Swapping speeds, give some delay
|
|
#10000;
|
|
end
|
|
|
|
eth_phy0.control_bit8_0 = 9'h1_00;
|
|
|
|
for(j=0;j<num_packets | length <32;j=j+1)
|
|
begin
|
|
eth_stim_rx_packet_length = length[15:0]; // Bytes
|
|
st_data = 8'h0F;
|
|
|
|
// setup RX packet in buffer - length is without CRC
|
|
set_rx_packet(0, eth_stim_rx_packet_length, 1'b0, dst_mac,
|
|
src_mac, 16'h0D0E, st_data, random_fill);
|
|
|
|
set_rx_addr_type(0, dst_mac, src_mac, 16'h0D0E);
|
|
|
|
// Error type 2 is cause CRC error
|
|
append_rx_crc(0, eth_stim_rx_packet_length, 1'b0,
|
|
(error_type==2));
|
|
|
|
if (error_this_time)
|
|
begin
|
|
if (error_type == 0)
|
|
// RX ERR assert during transmit
|
|
eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
|
|
8'hD5, 0,
|
|
eth_stim_rx_packet_length+4,
|
|
1'b0, 1'b1);
|
|
else if (error_type == 1)
|
|
// Incorrect preamble
|
|
eth_phy0.send_rx_packet(64'h0055_5f55_5555_5555, 4'h7,
|
|
8'hD5, 0,
|
|
eth_stim_rx_packet_length+4,
|
|
1'b0, 1'b0);
|
|
else
|
|
// Normal datapacket
|
|
eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7,
|
|
8'hD5, 0,
|
|
eth_stim_rx_packet_length+4,
|
|
1'b0, 1'b0);
|
|
end
|
|
else
|
|
eth_phy0.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5,
|
|
0, eth_stim_rx_packet_length+4, 1'b0,
|
|
1'b0);
|
|
|
|
|
|
// if RX enable still set (might have gone low during this packet
|
|
if (ethmac_rxen)
|
|
begin
|
|
if (error_this_time)
|
|
// Put in dummy length, checking function will skip...
|
|
rx_packet_lengths[(eth_rx_num_packets_sent& 12'h3ff)]=32'heeeeeeee;
|
|
else
|
|
rx_packet_lengths[(eth_rx_num_packets_sent & 12'h3ff)] = length;
|
|
|
|
eth_rx_num_packets_sent = eth_rx_num_packets_sent + 1;
|
|
|
|
end // if (ethmac_rxen)
|
|
else
|
|
begin
|
|
// Force the loop to finish up
|
|
j = num_packets;
|
|
end
|
|
|
|
|
|
// Inter-packet gap
|
|
#back_to_back_delay;
|
|
|
|
// Update length
|
|
if (length_change == 2'b01)
|
|
length = length + length_change_size;
|
|
|
|
if ((length_change == 2'b10) &&
|
|
((length - length_change_size) > 32))
|
|
length = length - length_change_size;
|
|
|
|
// Increment error type
|
|
if (error_this_time)
|
|
error_type = error_type + 1;
|
|
if (error_type > 3)
|
|
error_type = 0;
|
|
|
|
|
|
// Check if we should put in an error this time
|
|
if (j%random_error_mod == 0)
|
|
error_this_time = 1;
|
|
else
|
|
error_this_time = 0;
|
|
|
|
eth_phy0.rx_err(0);
|
|
|
|
// Now wait to check if we have filled up all the RX BDs and
|
|
// the this packet would start writing over them. Only really an
|
|
// issue when doing minimum IPG tests.
|
|
while(((eth_rx_num_packets_sent+1) - eth_rx_num_packets_checked)
|
|
== num_rx_bds)
|
|
#100;
|
|
|
|
|
|
end // for (j=0;j<num_packets | length <32;j=j+1)
|
|
end
|
|
endtask // send_packet_loop
|
|
|
|
// Local buffer of "sent" data to the ethernet MAC, we will check against
|
|
// Size of our local buffer in bytes
|
|
parameter eth_rx_sent_circbuf_size = (16*1024);
|
|
parameter eth_rx_sent_circbuf_size_mask = eth_rx_sent_circbuf_size - 1;
|
|
integer eth_rx_sent_circbuf_fill_ptr = 0;
|
|
integer eth_rx_sent_circbuf_read_ptr = 0;
|
|
// The actual buffer
|
|
reg [7:0] eth_rx_sent_circbuf [0:eth_rx_sent_circbuf_size-1];
|
|
|
|
/*
|
|
TASKS for set and check RX packets:
|
|
-----------------------------------
|
|
set_rx_packet
|
|
(rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
|
|
check_rx_packet
|
|
(rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
|
|
*/
|
|
task set_rx_packet;
|
|
input [31:0] rxpnt; // pointer to place in in the phy rx buffer we'll start at
|
|
input [15:0] len;
|
|
input plus_dribble_nibble; // if length is longer for one nibble
|
|
input [47:0] eth_dest_addr;
|
|
input [47:0] eth_source_addr;
|
|
input [15:0] eth_type_len;
|
|
input [7:0] eth_start_data;
|
|
input random_fill;
|
|
integer i, sd;
|
|
reg [47:0] dest_addr;
|
|
reg [47:0] source_addr;
|
|
reg [15:0] type_len;
|
|
reg [21:0] buffer;
|
|
reg delta_t;
|
|
|
|
begin
|
|
buffer = rxpnt[21:0];
|
|
dest_addr = eth_dest_addr;
|
|
source_addr = eth_source_addr;
|
|
type_len = eth_type_len;
|
|
sd = eth_start_data;
|
|
delta_t = 0;
|
|
for(i = 0; i < len; i = i + 1)
|
|
begin
|
|
if (i < 6)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = dest_addr[47:40];
|
|
dest_addr = dest_addr << 8;
|
|
end
|
|
else if (i < 12)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = source_addr[47:40];
|
|
source_addr = source_addr << 8;
|
|
end
|
|
else if (i < 14)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = type_len[15:8];
|
|
type_len = type_len << 8;
|
|
end
|
|
else
|
|
begin
|
|
if (random_fill)
|
|
begin
|
|
if (lfsr_last_byte == 0)
|
|
eth_phy0.rx_mem[buffer] = lfsr[15:8];
|
|
if (lfsr_last_byte == 1)
|
|
eth_phy0.rx_mem[buffer] = lfsr[23:16];
|
|
if (lfsr_last_byte == 2)
|
|
eth_phy0.rx_mem[buffer] = lfsr[31:24];
|
|
if (lfsr_last_byte == 3)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = lfsr[7:0];
|
|
lfsr = {lfsr[30:0],(((lfsr[31] ^ lfsr[6]) ^
|
|
lfsr[5]) ^ lfsr[1])};
|
|
lfsr_last_byte = 0;
|
|
end
|
|
else
|
|
lfsr_last_byte = lfsr_last_byte + 1;
|
|
|
|
end // if (random_fill)
|
|
else
|
|
eth_phy0.rx_mem[buffer] = sd[7:0];
|
|
sd = sd + 1;
|
|
end // else: !if(i < 14)
|
|
|
|
// Update our local buffer
|
|
eth_rx_sent_circbuf[eth_rx_sent_circbuf_fill_ptr]
|
|
= eth_phy0.rx_mem[buffer];
|
|
eth_rx_sent_circbuf_fill_ptr = (eth_rx_sent_circbuf_fill_ptr+1)&
|
|
eth_rx_sent_circbuf_size_mask;
|
|
|
|
buffer = buffer + 1;
|
|
end // for (i = 0; i < len; i = i + 1)
|
|
|
|
delta_t = !delta_t;
|
|
if (plus_dribble_nibble)
|
|
eth_phy0.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
|
|
delta_t = !delta_t;
|
|
end
|
|
endtask // set_rx_packet
|
|
|
|
|
|
|
|
|
|
task set_rx_addr_type;
|
|
input [31:0] rxpnt;
|
|
input [47:0] eth_dest_addr;
|
|
input [47:0] eth_source_addr;
|
|
input [15:0] eth_type_len;
|
|
integer i;
|
|
reg [47:0] dest_addr;
|
|
reg [47:0] source_addr;
|
|
reg [15:0] type_len;
|
|
reg [21:0] buffer;
|
|
reg delta_t;
|
|
begin
|
|
buffer = rxpnt[21:0];
|
|
dest_addr = eth_dest_addr;
|
|
source_addr = eth_source_addr;
|
|
type_len = eth_type_len;
|
|
delta_t = 0;
|
|
for(i = 0; i < 14; i = i + 1)
|
|
begin
|
|
if (i < 6)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = dest_addr[47:40];
|
|
dest_addr = dest_addr << 8;
|
|
end
|
|
else if (i < 12)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = source_addr[47:40];
|
|
source_addr = source_addr << 8;
|
|
end
|
|
else // if (i < 14)
|
|
begin
|
|
eth_phy0.rx_mem[buffer] = type_len[15:8];
|
|
type_len = type_len << 8;
|
|
end
|
|
buffer = buffer + 1;
|
|
end
|
|
delta_t = !delta_t;
|
|
end
|
|
endtask // set_rx_addr_type
|
|
|
|
|
|
// Check if we're using a synthesized version of eth module
|
|
`ifdef ethmac_IS_GATELEVEL
|
|
|
|
// Get the length/status register of the ethernet buffer descriptor
|
|
task get_bd_lenstat;
|
|
input [31:0] bd_num;// Number of ethernet BD to check
|
|
output [31:0] bd_lenstat;
|
|
`ifdef ACTEL
|
|
reg [8:0] tmp;
|
|
integer raddr;
|
|
`endif
|
|
begin
|
|
`ifdef ACTEL
|
|
|
|
// Pull from the Actel memory model
|
|
raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2));
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
|
|
bd_lenstat[8:0] = tmp[8:0];
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
|
|
bd_lenstat[17:9] = tmp[8:0];
|
|
|
|
raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2));
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
|
|
bd_lenstat[26:18] = tmp[8:0];
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
|
|
bd_lenstat[31:27] = tmp[4:0];
|
|
|
|
//$display("(%t) read eth bd lenstat %h",$time, bd_lenstat);
|
|
`endif
|
|
end
|
|
endtask // get_bd_lenstat
|
|
|
|
// Get the length/status register of the ethernet buffer descriptor
|
|
task get_bd_addr;
|
|
input [31:0] bd_num;// Number of the ethernet BD to check
|
|
output [31:0] bd_addr;
|
|
`ifdef ACTEL
|
|
reg [8:0] tmp;
|
|
integer raddr;
|
|
`endif
|
|
begin
|
|
`ifdef ACTEL
|
|
// Pull from the Actel memory model
|
|
raddr = `ETH_BD_RAM_PATH.\mem_tile.I_1 .get_address((bd_num*2)+1);
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)];
|
|
bd_addr[8:0] = tmp[8:0];
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile.I_1 .MEM_512_9[(raddr*2)+1];
|
|
bd_addr[17:9] = tmp[8:0];
|
|
|
|
raddr = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .get_address((bd_num*2)+1);
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)];
|
|
bd_addr[26:18] = tmp[8:0];
|
|
|
|
tmp = `ETH_BD_RAM_PATH.\mem_tile_0.I_1 .MEM_512_9[(raddr*2)+1];
|
|
bd_addr[31:27] = tmp[4:0];
|
|
|
|
//$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
|
|
`endif
|
|
end
|
|
endtask // get_bd_addr
|
|
|
|
`else // !`ifdef ethmac_IS_GATELEVEL
|
|
|
|
// Get the length/status register of the ethernet buffer descriptor
|
|
task get_bd_lenstat;
|
|
input [31:0] bd_num;// Number of ethernet BD to check
|
|
output [31:0] bd_lenstat;
|
|
begin
|
|
bd_lenstat = `ETH_BD_RAM_PATH.mem[(bd_num*2)];
|
|
end
|
|
endtask // get_bd_lenstat
|
|
|
|
// Get the length/status register of the ethernet buffer descriptor
|
|
task get_bd_addr;
|
|
input [31:0] bd_num;// Number of the ethernet BD to check
|
|
output [31:0] bd_addr;
|
|
begin
|
|
bd_addr = `ETH_BD_RAM_PATH.mem[((bd_num*2)+1)];
|
|
//$display("(%t) read eth bd%d addr %h",$time,bd_num, bd_addr);
|
|
end
|
|
endtask // get_bd_addr
|
|
`endif
|
|
|
|
// Always block triggered by finishing of transmission of new packet from
|
|
// send_packet_loop
|
|
integer eth_rx_packet_length_to_check;
|
|
|
|
always @*
|
|
begin
|
|
// Loop here until:
|
|
// 1 - packets sent is not equal to packets checked (ie. some to check)
|
|
// 2 - we're explicitly disabled for some reason
|
|
// 3 - Receive has been disabled in the MAC
|
|
while((eth_rx_num_packets_sent == eth_rx_num_packets_checked) ||
|
|
!eth_stim_check_rx_packet_contents || !(ethmac_rxen===1'b1))
|
|
#1000;
|
|
|
|
eth_rx_packet_length_to_check
|
|
= rx_packet_lengths[(eth_rx_num_packets_checked & 12'h3ff)];
|
|
|
|
if ( eth_rx_packet_length_to_check !== 32'heeeeeeee)
|
|
check_rx_packet(expected_rxbd, 0, eth_rx_packet_length_to_check);
|
|
|
|
eth_rx_num_packets_checked = eth_rx_num_packets_checked + 1;
|
|
|
|
expected_rxbd = expected_rxbd + 1;
|
|
|
|
// Wrap
|
|
if (expected_rxbd == (num_tx_bds + num_rx_bds))
|
|
expected_rxbd = num_tx_bds;
|
|
end
|
|
|
|
task check_rx_packet;
|
|
|
|
input [31:0] rx_bd_num;
|
|
input [31:0] rxpnt_phy; // Pointer in array of data in PHY
|
|
input [31:0] len;
|
|
|
|
reg [31:0] rx_bd_lenstat;
|
|
reg [31:0] rx_bd_addr;
|
|
reg [7:0] phy_byte;
|
|
|
|
reg [31:0] rxpnt_wb; // Pointer in array to where data should be
|
|
reg [24:0] rxpnt_sdram; // byte address from CPU in RAM
|
|
reg [15:0] sdram_short;
|
|
reg [7:0] sdram_byte;
|
|
//reg [7:0] phy_rx_mem [0:2000];
|
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integer i;
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integer failure;
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begin
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failure = 0;
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// Wait until the buffer descriptor indicates the packet has been
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// received...
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get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
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while (rx_bd_lenstat & 32'h00008000)// Check Empty bit
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begin
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#10;
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get_bd_lenstat(rx_bd_num, rx_bd_lenstat);
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//$display("(%t) check_rx_packet: poll bd %d: 0x%h",$time,
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// rx_bd_num, rx_bd_lenstat);
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end
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// Delay some time - takes a bit for the Wishbone FSM to pipe out the
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// packet over Wishbone and into whatever memory it's going into
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#Td_rx_packet_check;
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// Ok, buffer filled, let's get its offset in memory
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get_bd_addr(rx_bd_num, rx_bd_addr);
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$display("(%t) Check RX packet: bd %d: 0x%h, addr 0x%h",$time,
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rx_bd_num, rx_bd_lenstat, rx_bd_addr);
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// We're never going to be using more than about 256KB of receive buffer
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// so let's lop off the top bit of the address pointer - we only want
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// the offset from the base of the memory bank
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rxpnt_wb = {14'd0,rx_bd_addr[17:0]};
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rxpnt_sdram = rx_bd_addr[24:0];
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`ifdef VERSATILE_SDRAM
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// We'll look inside the SDRAM array
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// Hard coded for the SDRAM buffer area to be from the halfway mark in
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// memory (so starting in Bank2)
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// We'll be passed the offset from the beginning of the buffer area
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// in rxpnt_wb. This value will be in bytes.
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//$display("RAM pointer for BD is 0x%h, SDRAM addr is 0x%h", rx_bd_addr, rxpnt_sdram);
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for (i=0;i<len;i=i+1)
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begin
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sdram0.get_byte(rxpnt_sdram,sdram_byte);
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phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
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if (phy_byte !== sdram_byte)
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begin
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// `TIME;
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$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
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i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
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failure = 1;
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end
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eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
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eth_rx_sent_circbuf_size_mask;
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rxpnt_sdram = rxpnt_sdram+1;
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end // for (i=0;i<len;i=i+2)
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`else
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$display("SET ME UP TO LOOK IN ANOTHER MEMORY!");
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$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
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rx_bd_addr, rxpnt_wb);
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$finish;
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`endif // !`ifdef VERSATILE_SDRAM
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if (failure)
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begin
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#100
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`TIME;
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$display("*E Recieved packet %0d, length %0d bytes, had an error. Finishing simulation.", eth_rx_num_packets_checked, len);
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$finish;
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end
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else
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begin
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#1 $display( "(%0t)(%m) RX packet %0d: %0d bytes in memory OK!",$time,eth_rx_num_packets_checked, len);
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end
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end
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endtask // check_rx_packet
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//////////////////////////////////////////////////////////////
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// Ethernet CRC Basic tasks
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//////////////////////////////////////////////////////////////
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task append_rx_crc;
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input [31:0] rxpnt_phy; // source
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input [15:0] len; // length in bytes without CRC
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input plus_dribble_nibble; // if length is longer for one nibble
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input negated_crc; // if appended CRC is correct or not
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reg [31:0] crc;
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reg [7:0] tmp;
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reg [31:0] addr_phy;
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reg delta_t;
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begin
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addr_phy = rxpnt_phy + len;
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delta_t = 0;
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// calculate CRC from prepared packet
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paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
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if (negated_crc)
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crc = ~crc;
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delta_t = !delta_t;
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if (plus_dribble_nibble)
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begin
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tmp = eth_phy0.rx_mem[addr_phy];
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eth_phy0.rx_mem[addr_phy] = {crc[27:24], tmp[3:0]};
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eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
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eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
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eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
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eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
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end
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else
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begin
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eth_phy0.rx_mem[addr_phy] = crc[31:24];
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eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
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eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
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eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
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end
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end
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endtask // append_rx_crc
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task append_rx_crc_delayed;
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input [31:0] rxpnt_phy; // source
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input [15:0] len; // length in bytes without CRC
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input plus_dribble_nibble; // if length is longer for one nibble
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input negated_crc; // if appended CRC is correct or not
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reg [31:0] crc;
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reg [7:0] tmp;
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reg [31:0] addr_phy;
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reg delta_t;
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begin
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addr_phy = rxpnt_phy + len;
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delta_t = 0;
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// calculate CRC from prepared packet
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paralel_crc_phy_rx(rxpnt_phy+4, {16'h0, len}-4, plus_dribble_nibble, crc);
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if (negated_crc)
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crc = ~crc;
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delta_t = !delta_t;
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if (plus_dribble_nibble)
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begin
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tmp = eth_phy0.rx_mem[addr_phy];
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eth_phy0.rx_mem[addr_phy] = {crc[27:24], tmp[3:0]};
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eth_phy0.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
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eth_phy0.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
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eth_phy0.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
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eth_phy0.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
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end
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else
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begin
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eth_phy0.rx_mem[addr_phy] = crc[31:24];
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eth_phy0.rx_mem[addr_phy + 1] = crc[23:16];
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eth_phy0.rx_mem[addr_phy + 2] = crc[15:8];
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eth_phy0.rx_mem[addr_phy + 3] = crc[7:0];
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end
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end
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endtask // append_rx_crc_delayed
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// paralel CRC calculating for PHY RX
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task paralel_crc_phy_rx;
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input [31:0] start_addr; // start address
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input [31:0] len; // length of frame in Bytes without CRC length
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input plus_dribble_nibble; // if length is longer for one nibble
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output [31:0] crc_out;
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reg [21:0] addr_cnt; // only 22 address lines
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integer word_cnt;
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integer nibble_cnt;
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reg [31:0] load_reg;
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reg delta_t;
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reg [31:0] crc_next;
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reg [31:0] crc;
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reg crc_error;
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reg [3:0] data_in;
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integer i;
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begin
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#1 addr_cnt = start_addr[21:0];
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word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
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crc = 32'hFFFF_FFFF; // INITIAL value
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delta_t = 0;
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// length must include 4 bytes of ZEROs, to generate CRC
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// get number of nibbles from Byte length (2^1 = 2)
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if (plus_dribble_nibble)
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nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
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else
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nibble_cnt = ((len + 4) << 1);
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// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
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load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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while (nibble_cnt > 0)
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begin
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// wait for delta time
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delta_t = !delta_t;
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// shift data in
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if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
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data_in[3:0] = 4'h0;
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else
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data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
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crc_next[0] = (data_in[0] ^ crc[28]);
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crc_next[1] = (data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29]);
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crc_next[2] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[30]);
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crc_next[3] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30] ^ crc[31]);
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crc_next[4] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28] ^ crc[30] ^ crc[31]) ^ crc[0];
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crc_next[5] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[31]) ^ crc[1];
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crc_next[6] = (data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30]) ^ crc[ 2];
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crc_next[7] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28] ^ crc[30] ^ crc[31]) ^ crc[3];
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crc_next[8] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[31]) ^ crc[4];
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crc_next[9] = (data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30]) ^ crc[5];
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crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28] ^ crc[30] ^ crc[31]) ^ crc[6];
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crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[31]) ^ crc[7];
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crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28] ^ crc[29] ^ crc[30]) ^ crc[8];
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crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29] ^ crc[30] ^ crc[31]) ^ crc[9];
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crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30] ^ crc[31]) ^ crc[10];
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crc_next[15] = (data_in[3] ^ crc[31]) ^ crc[11];
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crc_next[16] = (data_in[0] ^ crc[28]) ^ crc[12];
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crc_next[17] = (data_in[1] ^ crc[29]) ^ crc[13];
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crc_next[18] = (data_in[2] ^ crc[30]) ^ crc[14];
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crc_next[19] = (data_in[3] ^ crc[31]) ^ crc[15];
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crc_next[20] = crc[16];
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crc_next[21] = crc[17];
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crc_next[22] = (data_in[0] ^ crc[28]) ^ crc[18];
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crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29] ^ crc[28]) ^ crc[19];
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crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30] ^ crc[29]) ^ crc[20];
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crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31] ^ crc[30]) ^ crc[21];
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crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31] ^ crc[28]) ^ crc[22];
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crc_next[27] = (data_in[1] ^ crc[29]) ^ crc[23];
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crc_next[28] = (data_in[2] ^ crc[30]) ^ crc[24];
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crc_next[29] = (data_in[3] ^ crc[31]) ^ crc[25];
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crc_next[30] = crc[26];
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crc_next[31] = crc[27];
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crc = crc_next;
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crc_error = crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
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case (nibble_cnt)
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9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
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!crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
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!crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
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!crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
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default: crc_out = crc_out;
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endcase
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// wait for delta time
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delta_t = !delta_t;
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// increment address and load new data
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if ((word_cnt+3) == 7)//4)
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begin
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// because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
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load_reg[31:24] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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load_reg[23:16] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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load_reg[15: 8] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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load_reg[ 7: 0] = eth_phy0.rx_mem[addr_cnt];
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addr_cnt = addr_cnt + 1;
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end
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// set new load bit position
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if((word_cnt+3) == 31)
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word_cnt = 16;
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else if ((word_cnt+3) == 23)
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word_cnt = 8;
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else if ((word_cnt+3) == 15)
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word_cnt = 0;
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else if ((word_cnt+3) == 7)
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word_cnt = 24;
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else
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word_cnt = word_cnt + 4;// - 4;
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// decrement nibble counter
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nibble_cnt = nibble_cnt - 1;
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// wait for delta time
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delta_t = !delta_t;
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end // while
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#1;
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end
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endtask // paralel_crc_phy_rx
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No newline at end of file
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No newline at end of file
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