//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/// ////
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/// ////
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/// ORPSoC ML501 testbench ////
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/// ORPSoC ML501 testbench ////
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/// ////
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/// ////
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/// Instantiate ORPSoC, monitors, provide stimulus ////
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/// Instantiate ORPSoC, monitors, provide stimulus ////
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/// ////
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/// ////
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/// Julius Baxter, julius@opencores.org ////
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/// Julius Baxter, julius@opencores.org ////
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/// ////
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/// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "orpsoc-defines.v"
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`include "orpsoc-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "test-defines.v"
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`include "test-defines.v"
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`include "timescale.v"
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`include "timescale.v"
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// Xilinx simulation:
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// Xilinx simulation:
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`include "glbl.v"
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`include "glbl.v"
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module orpsoc_testbench;
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module orpsoc_testbench;
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// Clock and reset signal registers
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// Clock and reset signal registers
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reg clk = 0;
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reg clk = 0;
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reg rst_n = 1; // Active LOW
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reg rst_n = 1; // Active LOW
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always
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always
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#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
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#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
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wire clk_n, clk_p;
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wire clk_n, clk_p;
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assign clk_p = clk;
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assign clk_p = clk;
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assign clk_n = ~clk;
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assign clk_n = ~clk;
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// Reset, ACTIVE LOW
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// Reset, ACTIVE LOW
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initial
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initial
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begin
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begin
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#1;
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#1;
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repeat (32) @(negedge clk)
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repeat (32) @(negedge clk)
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rst_n <= 1;
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rst_n <= 1;
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repeat (32) @(negedge clk)
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repeat (32) @(negedge clk)
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rst_n <= 0;
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rst_n <= 0;
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repeat (32) @(negedge clk)
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repeat (32) @(negedge clk)
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rst_n <= 1;
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rst_n <= 1;
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end
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end
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// Include design parameters file
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// Include design parameters file
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`include "orpsoc-params.v"
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`include "orpsoc-params.v"
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// Pullup bus for I2C
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// Pullup bus for I2C
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tri1 i2c_scl, i2c_sda;
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tri1 i2c_scl, i2c_sda;
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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wire tdo_pad_o;
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wire tdo_pad_o;
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wire tck_pad_i;
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wire tck_pad_i;
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wire tms_pad_i;
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wire tms_pad_i;
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wire tdi_pad_i;
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wire tdi_pad_i;
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`endif
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`endif
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`ifdef UART0
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`ifdef UART0
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wire uart0_stx_pad_o;
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wire uart0_stx_pad_o;
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wire uart0_srx_pad_i;
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wire uart0_srx_pad_i;
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`endif
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`endif
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`ifdef GPIO0
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`ifdef GPIO0
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wire [gpio0_io_width-1:0] gpio0_io;
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wire [gpio0_io_width-1:0] gpio0_io;
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`endif
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`endif
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`ifdef SPI0
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`ifdef SPI0
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wire spi0_mosi_o;
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wire spi0_mosi_o;
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wire spi0_miso_i;
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wire spi0_miso_i;
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wire spi0_sck_o;
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wire spi0_sck_o;
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wire spi0_hold_n_o;
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wire spi0_hold_n_o;
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wire spi0_w_n_o;
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wire spi0_w_n_o;
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wire [spi0_ss_width-1:0] spi0_ss_o;
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wire [spi0_ss_width-1:0] spi0_ss_o;
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`endif
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`endif
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`ifdef ETH0
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`ifdef ETH0
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wire mtx_clk_o;
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wire mtx_clk_o;
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wire [3:0] ethphy_mii_tx_d;
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wire [3:0] ethphy_mii_tx_d;
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wire ethphy_mii_tx_en;
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wire ethphy_mii_tx_en;
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wire ethphy_mii_tx_err;
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wire ethphy_mii_tx_err;
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wire mrx_clk_o;
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wire mrx_clk_o;
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wire [3:0] mrxd_o;
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wire [3:0] mrxd_o;
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wire mrxdv_o;
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wire mrxdv_o;
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wire mrxerr_o;
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wire mrxerr_o;
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wire mcoll_o;
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wire mcoll_o;
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wire mcrs_o;
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wire mcrs_o;
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wire ethphy_rst_n;
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wire ethphy_rst_n;
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wire eth0_mdc_pad_o;
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wire eth0_mdc_pad_o;
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wire eth0_md_pad_io;
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wire eth0_md_pad_io;
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`endif
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`endif
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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`include "xilinx_ddr2_params.v"
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`include "xilinx_ddr2_params.v"
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localparam DEVICE_WIDTH = 16; // Memory device data width
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localparam DEVICE_WIDTH = 16; // Memory device data width
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localparam real CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
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localparam real CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
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localparam real TCYC_200 = 5.0;
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localparam real TCYC_200 = 5.0;
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localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
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localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
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localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
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localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
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localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
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localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
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localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
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localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
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localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
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localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
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wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
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wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
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wire [DQS_WIDTH-1:0] ddr2_dqs_sdram;
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wire [DQS_WIDTH-1:0] ddr2_dqs_sdram;
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wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
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wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
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wire [DM_WIDTH-1:0] ddr2_dm_sdram;
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wire [DM_WIDTH-1:0] ddr2_dm_sdram;
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reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
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reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
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reg [CLK_WIDTH-1:0] ddr2_ck_sdram;
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reg [CLK_WIDTH-1:0] ddr2_ck_sdram;
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reg [CLK_WIDTH-1:0] ddr2_ck_n_sdram;
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reg [CLK_WIDTH-1:0] ddr2_ck_n_sdram;
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reg [ROW_WIDTH-1:0] ddr2_a_sdram;
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reg [ROW_WIDTH-1:0] ddr2_a_sdram;
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reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
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reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
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reg ddr2_ras_n_sdram;
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reg ddr2_ras_n_sdram;
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reg ddr2_cas_n_sdram;
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reg ddr2_cas_n_sdram;
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reg ddr2_we_n_sdram;
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reg ddr2_we_n_sdram;
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reg [CS_WIDTH-1:0] ddr2_cs_n_sdram;
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reg [CS_WIDTH-1:0] ddr2_cs_n_sdram;
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reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
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reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
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reg [ODT_WIDTH-1:0] ddr2_odt_sdram;
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reg [ODT_WIDTH-1:0] ddr2_odt_sdram;
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wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
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wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
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wire [DQS_WIDTH-1:0] ddr2_dqs_fpga;
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wire [DQS_WIDTH-1:0] ddr2_dqs_fpga;
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wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
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wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
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wire [DM_WIDTH-1:0] ddr2_dm_fpga;
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wire [DM_WIDTH-1:0] ddr2_dm_fpga;
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wire [CLK_WIDTH-1:0] ddr2_ck_fpga;
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wire [CLK_WIDTH-1:0] ddr2_ck_fpga;
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wire [CLK_WIDTH-1:0] ddr2_ck_n_fpga;
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wire [CLK_WIDTH-1:0] ddr2_ck_n_fpga;
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wire [ROW_WIDTH-1:0] ddr2_a_fpga;
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wire [ROW_WIDTH-1:0] ddr2_a_fpga;
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wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
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wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
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wire ddr2_ras_n_fpga;
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wire ddr2_ras_n_fpga;
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wire ddr2_cas_n_fpga;
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wire ddr2_cas_n_fpga;
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wire ddr2_we_n_fpga;
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wire ddr2_we_n_fpga;
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wire [CS_WIDTH-1:0] ddr2_cs_n_fpga;
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wire [CS_WIDTH-1:0] ddr2_cs_n_fpga;
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wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
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wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
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wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
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wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
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`endif
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`endif
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`ifdef XILINX_SSRAM
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`ifdef XILINX_SSRAM
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wire sram_clk;
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wire sram_clk;
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wire sram_clk_fb;
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wire sram_clk_fb;
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wire sram_adv_ld_n;
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wire sram_adv_ld_n;
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wire [3:0] sram_bw;
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wire [3:0] sram_bw;
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wire sram_cen;
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wire sram_cen;
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wire [21:1] sram_flash_addr;
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wire [21:1] sram_flash_addr;
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wire [31:0] sram_flash_data;
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wire [31:0] sram_flash_data;
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wire sram_flash_oe_n;
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wire sram_flash_oe_n;
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wire sram_flash_we_n;
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wire sram_flash_we_n;
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wire sram_mode;
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wire sram_mode;
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`endif
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`endif
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orpsoc_top dut
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orpsoc_top dut
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(
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(
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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.tms_pad_i (tms_pad_i),
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.tms_pad_i (tms_pad_i),
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.tck_pad_i (tck_pad_i),
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.tck_pad_i (tck_pad_i),
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.tdi_pad_i (tdi_pad_i),
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.tdi_pad_i (tdi_pad_i),
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.tdo_pad_o (tdo_pad_o),
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.tdo_pad_o (tdo_pad_o),
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`endif
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`endif
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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.ddr2_a (ddr2_a_fpga),
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.ddr2_a (ddr2_a_fpga),
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.ddr2_ba (ddr2_ba_fpga),
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.ddr2_ba (ddr2_ba_fpga),
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.ddr2_ras_n (ddr2_ras_n_fpga),
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.ddr2_ras_n (ddr2_ras_n_fpga),
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.ddr2_cas_n (ddr2_cas_n_fpga),
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.ddr2_cas_n (ddr2_cas_n_fpga),
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.ddr2_we_n (ddr2_we_n_fpga),
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.ddr2_we_n (ddr2_we_n_fpga),
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.ddr2_cs_n (ddr2_cs_n_fpga),
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.ddr2_cs_n (ddr2_cs_n_fpga),
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.ddr2_odt (ddr2_odt_fpga),
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.ddr2_odt (ddr2_odt_fpga),
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.ddr2_cke (ddr2_cke_fpga),
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.ddr2_cke (ddr2_cke_fpga),
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.ddr2_dm (ddr2_dm_fpga),
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.ddr2_dm (ddr2_dm_fpga),
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.ddr2_ck (ddr2_ck_fpga),
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.ddr2_ck (ddr2_ck_fpga),
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.ddr2_ck_n (ddr2_ck_n_fpga),
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.ddr2_ck_n (ddr2_ck_n_fpga),
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.ddr2_dq (ddr2_dq_fpga),
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.ddr2_dq (ddr2_dq_fpga),
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.ddr2_dqs (ddr2_dqs_fpga),
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.ddr2_dqs (ddr2_dqs_fpga),
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.ddr2_dqs_n (ddr2_dqs_n_fpga),
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.ddr2_dqs_n (ddr2_dqs_n_fpga),
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`endif
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`endif
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`ifdef XILINX_SSRAM
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`ifdef XILINX_SSRAM
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.sram_clk (sram_clk),
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.sram_clk (sram_clk),
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.sram_flash_addr (sram_flash_addr),
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.sram_flash_addr (sram_flash_addr),
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.sram_cen (sram_cen),
|
.sram_cen (sram_cen),
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.sram_flash_oe_n (sram_flash_oe_n),
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.sram_flash_oe_n (sram_flash_oe_n),
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.sram_flash_we_n (sram_flash_we_n),
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.sram_flash_we_n (sram_flash_we_n),
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.sram_bw (sram_bw),
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.sram_bw (sram_bw),
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.sram_adv_ld_n (sram_adv_ld_n),
|
.sram_adv_ld_n (sram_adv_ld_n),
|
.sram_mode (sram_mode),
|
.sram_mode (sram_mode),
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.sram_clk_fb (sram_clk_fb),
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.sram_clk_fb (sram_clk_fb),
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.sram_flash_data (sram_flash_data),
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.sram_flash_data (sram_flash_data),
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`endif
|
`endif
|
`ifdef UART0
|
`ifdef UART0
|
.uart0_stx_pad_o (uart0_stx_pad_o),
|
.uart0_stx_pad_o (uart0_stx_pad_o),
|
.uart0_srx_pad_i (uart0_srx_pad_i),
|
.uart0_srx_pad_i (uart0_srx_pad_i),
|
.uart0_stx_expheader_pad_o (uart0_stx_pad_o),
|
.uart0_stx_expheader_pad_o (uart0_stx_pad_o),
|
.uart0_srx_expheader_pad_i (uart0_srx_pad_i),
|
.uart0_srx_expheader_pad_i (uart0_srx_pad_i),
|
`endif
|
`endif
|
`ifdef SPI0
|
`ifdef SPI0
|
.spi0_sck_o (spi0_sck_o),
|
/*
|
|
via STARTUP_VIRTEX5
|
|
.spi0_sck_o (spi0_sck_o),
|
|
.spi0_miso_i (spi0_miso_i),
|
|
*/
|
.spi0_mosi_o (spi0_mosi_o),
|
.spi0_mosi_o (spi0_mosi_o),
|
.spi0_miso_i (spi0_miso_i),
|
|
.spi0_ss_o (spi0_ss_o),
|
.spi0_ss_o (spi0_ss_o),
|
`endif
|
`endif
|
`ifdef I2C0
|
`ifdef I2C0
|
.i2c0_sda_io (i2c_sda),
|
.i2c0_sda_io (i2c_sda),
|
.i2c0_scl_io (i2c_scl),
|
.i2c0_scl_io (i2c_scl),
|
`endif
|
`endif
|
`ifdef I2C1
|
`ifdef I2C1
|
.i2c1_sda_io (i2c_sda),
|
.i2c1_sda_io (i2c_sda),
|
.i2c1_scl_io (i2c_scl),
|
.i2c1_scl_io (i2c_scl),
|
`endif
|
`endif
|
`ifdef GPIO0
|
`ifdef GPIO0
|
.gpio0_io (gpio0_io),
|
.gpio0_io (gpio0_io),
|
`endif
|
`endif
|
`ifdef ETH0
|
`ifdef ETH0
|
.eth0_tx_clk (mtx_clk_o),
|
.eth0_tx_clk (mtx_clk_o),
|
.eth0_tx_data (ethphy_mii_tx_d),
|
.eth0_tx_data (ethphy_mii_tx_d),
|
.eth0_tx_en (ethphy_mii_tx_en),
|
.eth0_tx_en (ethphy_mii_tx_en),
|
.eth0_tx_er (ethphy_mii_tx_err),
|
.eth0_tx_er (ethphy_mii_tx_err),
|
.eth0_rx_clk (mrx_clk_o),
|
.eth0_rx_clk (mrx_clk_o),
|
.eth0_rx_data (mrxd_o),
|
.eth0_rx_data (mrxd_o),
|
.eth0_dv (mrxdv_o),
|
.eth0_dv (mrxdv_o),
|
.eth0_rx_er (mrxerr_o),
|
.eth0_rx_er (mrxerr_o),
|
.eth0_col (mcoll_o),
|
.eth0_col (mcoll_o),
|
.eth0_crs (mcrs_o),
|
.eth0_crs (mcrs_o),
|
.eth0_rst_n_o (ethphy_rst_n),
|
.eth0_rst_n_o (ethphy_rst_n),
|
.eth0_mdc_pad_o (eth0_mdc_pad_o),
|
.eth0_mdc_pad_o (eth0_mdc_pad_o),
|
.eth0_md_pad_io (eth0_md_pad_io),
|
.eth0_md_pad_io (eth0_md_pad_io),
|
`endif // `ifdef ETH0
|
`endif // `ifdef ETH0
|
|
|
.sys_clk_in_p (clk_p),
|
.sys_clk_in_p (clk_p),
|
.sys_clk_in_n (clk_n),
|
.sys_clk_in_n (clk_n),
|
|
|
.rst_n_pad_i (rst_n)
|
.rst_n_pad_i (rst_n)
|
);
|
);
|
|
|
//
|
//
|
// Instantiate OR1200 monitor
|
// Instantiate OR1200 monitor
|
//
|
//
|
or1200_monitor monitor();
|
or1200_monitor monitor();
|
|
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
`define CPU_ic_top or1200_ic_top
|
`define CPU_ic_top or1200_ic_top
|
`define CPU_dc_top or1200_dc_top
|
`define CPU_dc_top or1200_dc_top
|
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
|
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
|
always @(posedge ic_en)
|
always @(posedge ic_en)
|
$display("Or1200 IC enabled at %t", $time);
|
$display("Or1200 IC enabled at %t", $time);
|
|
|
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
|
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
|
always @(posedge dc_en)
|
always @(posedge dc_en)
|
$display("Or1200 DC enabled at %t", $time);
|
$display("Or1200 DC enabled at %t", $time);
|
`endif
|
`endif
|
|
|
|
|
`ifdef JTAG_DEBUG
|
`ifdef JTAG_DEBUG
|
`ifdef VPI_DEBUG
|
`ifdef VPI_DEBUG
|
// Debugging interface
|
// Debugging interface
|
vpi_debug_module vpi_dbg
|
vpi_debug_module vpi_dbg
|
(
|
(
|
.tms(tms_pad_i),
|
.tms(tms_pad_i),
|
.tck(tck_pad_i),
|
.tck(tck_pad_i),
|
.tdi(tdi_pad_i),
|
.tdi(tdi_pad_i),
|
.tdo(tdo_pad_o)
|
.tdo(tdo_pad_o)
|
);
|
);
|
`else
|
`else
|
// If no VPI debugging, tie off JTAG inputs
|
// If no VPI debugging, tie off JTAG inputs
|
assign tdi_pad_i = 1;
|
assign tdi_pad_i = 1;
|
assign tck_pad_i = 0;
|
assign tck_pad_i = 0;
|
assign tms_pad_i = 1;
|
assign tms_pad_i = 1;
|
`endif // !`ifdef VPI_DEBUG_ENABLE
|
`endif // !`ifdef VPI_DEBUG_ENABLE
|
`endif // `ifdef JTAG_DEBUG
|
`endif // `ifdef JTAG_DEBUG
|
|
|
`ifdef SPI0
|
`ifdef SPI0
|
|
// STARTUP_VIRTEX5 module routes these out on the board.
|
|
// So for now just connect directly to the internals here.
|
|
assign spi0_sck_o = dut.spi0_sck_o;
|
|
assign dut.spi0_miso_i = spi0_miso_i;
|
|
|
// SPI flash memory - M25P16 compatible SPI protocol
|
// SPI flash memory - M25P16 compatible SPI protocol
|
AT26DFxxx spi0_flash
|
AT26DFxxx
|
|
#(.MEMSIZE(2048*1024)) // 2MB flash on ML501
|
|
spi0_flash
|
(// Outputs
|
(// Outputs
|
.SO (spi0_miso_i),
|
.SO (spi0_miso_i),
|
// Inputs
|
// Inputs
|
.CSB (spi0_ss_o),
|
.CSB (spi0_ss_o),
|
.SCK (spi0_sck_o),
|
.SCK (spi0_sck_o),
|
.SI (spi0_mosi_o),
|
.SI (spi0_mosi_o),
|
.WPB (1'b1)
|
.WPB (1'b1)
|
);
|
);
|
|
|
|
|
`endif // `ifdef SPI0
|
`endif // `ifdef SPI0
|
|
|
`ifdef ETH0
|
`ifdef ETH0
|
|
|
/* TX/RXes packets and checks them, enabled when ethernet MAC is */
|
/* TX/RXes packets and checks them, enabled when ethernet MAC is */
|
`include "eth_stim.v"
|
`include "eth_stim.v"
|
|
|
eth_phy eth_phy0
|
eth_phy eth_phy0
|
(
|
(
|
// Outputs
|
// Outputs
|
.mtx_clk_o (mtx_clk_o),
|
.mtx_clk_o (mtx_clk_o),
|
.mrx_clk_o (mrx_clk_o),
|
.mrx_clk_o (mrx_clk_o),
|
.mrxd_o (mrxd_o[3:0]),
|
.mrxd_o (mrxd_o[3:0]),
|
.mrxdv_o (mrxdv_o),
|
.mrxdv_o (mrxdv_o),
|
.mrxerr_o (mrxerr_o),
|
.mrxerr_o (mrxerr_o),
|
.mcoll_o (mcoll_o),
|
.mcoll_o (mcoll_o),
|
.mcrs_o (mcrs_o),
|
.mcrs_o (mcrs_o),
|
.link_o (),
|
.link_o (),
|
.speed_o (),
|
.speed_o (),
|
.duplex_o (),
|
.duplex_o (),
|
.smii_clk_i (1'b0),
|
.smii_clk_i (1'b0),
|
.smii_sync_i (1'b0),
|
.smii_sync_i (1'b0),
|
.smii_rx_o (),
|
.smii_rx_o (),
|
// Inouts
|
// Inouts
|
.md_io (eth0_md_pad_io),
|
.md_io (eth0_md_pad_io),
|
// Inputs
|
// Inputs
|
`ifndef ETH0_PHY_RST
|
`ifndef ETH0_PHY_RST
|
// If no reset out from the design, hook up to the board's active low rst
|
// If no reset out from the design, hook up to the board's active low rst
|
.m_rst_n_i (rst_n),
|
.m_rst_n_i (rst_n),
|
`else
|
`else
|
.m_rst_n_i (ethphy_rst_n),
|
.m_rst_n_i (ethphy_rst_n),
|
`endif
|
`endif
|
.mtxd_i (ethphy_mii_tx_d[3:0]),
|
.mtxd_i (ethphy_mii_tx_d[3:0]),
|
.mtxen_i (ethphy_mii_tx_en),
|
.mtxen_i (ethphy_mii_tx_en),
|
.mtxerr_i (ethphy_mii_tx_err),
|
.mtxerr_i (ethphy_mii_tx_err),
|
.mdc_i (eth0_mdc_pad_o));
|
.mdc_i (eth0_mdc_pad_o));
|
|
|
`endif // `ifdef ETH0
|
`endif // `ifdef ETH0
|
|
|
`ifdef XILINX_SSRAM
|
`ifdef XILINX_SSRAM
|
wire [18:0] sram_a;
|
wire [18:0] sram_a;
|
wire [3:0] dqp;
|
wire [3:0] dqp;
|
|
|
assign sram_a[18:0] = sram_flash_addr[19:1];
|
assign sram_a[18:0] = sram_flash_addr[19:1];
|
wire sram_ce1b, sram_ce2, sram_ce3b;
|
wire sram_ce1b, sram_ce2, sram_ce3b;
|
assign sram_ce1b = 1'b0;
|
assign sram_ce1b = 1'b0;
|
assign sram_ce2 = 1'b1;
|
assign sram_ce2 = 1'b1;
|
assign sram_ce3b = 1'b0;
|
assign sram_ce3b = 1'b0;
|
assign sram_clk_fb = sram_clk;
|
assign sram_clk_fb = sram_clk;
|
|
|
cy7c1354 ssram0
|
cy7c1354 ssram0
|
(
|
(
|
// Inouts
|
// Inouts
|
// This model puts each parity bit after each byte, but the ML501's part
|
// This model puts each parity bit after each byte, but the ML501's part
|
// doesn't, so we wire up the data bus like so.
|
// doesn't, so we wire up the data bus like so.
|
.d ({dqp[3],sram_flash_data[31:24],
|
.d ({dqp[3],sram_flash_data[31:24],
|
dqp[2],sram_flash_data[23:16],
|
dqp[2],sram_flash_data[23:16],
|
dqp[1],sram_flash_data[15:8],
|
dqp[1],sram_flash_data[15:8],
|
dqp[0],sram_flash_data[7:0]}),
|
dqp[0],sram_flash_data[7:0]}),
|
// Inputs
|
// Inputs
|
.clk (sram_clk),
|
.clk (sram_clk),
|
.we_b (sram_flash_we_n),
|
.we_b (sram_flash_we_n),
|
.adv_lb (sram_adv_ld_n),
|
.adv_lb (sram_adv_ld_n),
|
.ce1b (sram_ce1b),
|
.ce1b (sram_ce1b),
|
.ce2 (sram_ce2),
|
.ce2 (sram_ce2),
|
.ce3b (sram_ce3b),
|
.ce3b (sram_ce3b),
|
.oeb (sram_flash_oe_n),
|
.oeb (sram_flash_oe_n),
|
.cenb (sram_cen),
|
.cenb (sram_cen),
|
.mode (sram_mode),
|
.mode (sram_mode),
|
.bws (sram_bw),
|
.bws (sram_bw),
|
.a (sram_a));
|
.a (sram_a));
|
`endif
|
`endif
|
|
|
`ifdef XILINX_DDR2
|
`ifdef XILINX_DDR2
|
`ifndef GATE_SIM
|
`ifndef GATE_SIM
|
defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0.SIM_ONLY = 1;
|
defparam dut.xilinx_ddr2_0.xilinx_ddr2_if0.ddr2_mig0.SIM_ONLY = 1;
|
`endif
|
`endif
|
|
|
always @( * ) begin
|
always @( * ) begin
|
ddr2_ck_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_fpga;
|
ddr2_ck_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_fpga;
|
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
|
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
|
ddr2_a_sdram <= #(TPROP_PCB_CTRL) ddr2_a_fpga;
|
ddr2_a_sdram <= #(TPROP_PCB_CTRL) ddr2_a_fpga;
|
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
|
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
|
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
|
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
|
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
|
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
|
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
|
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
|
ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
|
ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
|
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
|
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
|
ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
|
ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
|
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
|
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
|
end // always @ ( * )
|
end // always @ ( * )
|
|
|
// Model delays on bi-directional BUS
|
// Model delays on bi-directional BUS
|
genvar dqwd;
|
genvar dqwd;
|
generate
|
generate
|
for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
|
for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
|
wiredelay #
|
wiredelay #
|
(
|
(
|
.Delay_g (TPROP_PCB_DATA),
|
.Delay_g (TPROP_PCB_DATA),
|
.Delay_rd (TPROP_PCB_DATA_RD)
|
.Delay_rd (TPROP_PCB_DATA_RD)
|
)
|
)
|
u_delay_dq
|
u_delay_dq
|
(
|
(
|
.A (ddr2_dq_fpga[dqwd]),
|
.A (ddr2_dq_fpga[dqwd]),
|
.B (ddr2_dq_sdram[dqwd]),
|
.B (ddr2_dq_sdram[dqwd]),
|
.reset (rst_n)
|
.reset (rst_n)
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
genvar dqswd;
|
genvar dqswd;
|
generate
|
generate
|
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
|
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
|
wiredelay #
|
wiredelay #
|
(
|
(
|
.Delay_g (TPROP_DQS),
|
.Delay_g (TPROP_DQS),
|
.Delay_rd (TPROP_DQS_RD)
|
.Delay_rd (TPROP_DQS_RD)
|
)
|
)
|
u_delay_dqs
|
u_delay_dqs
|
(
|
(
|
.A (ddr2_dqs_fpga[dqswd]),
|
.A (ddr2_dqs_fpga[dqswd]),
|
.B (ddr2_dqs_sdram[dqswd]),
|
.B (ddr2_dqs_sdram[dqswd]),
|
.reset (rst_n)
|
.reset (rst_n)
|
);
|
);
|
|
|
wiredelay #
|
wiredelay #
|
(
|
(
|
.Delay_g (TPROP_DQS),
|
.Delay_g (TPROP_DQS),
|
.Delay_rd (TPROP_DQS_RD)
|
.Delay_rd (TPROP_DQS_RD)
|
)
|
)
|
u_delay_dqs_n
|
u_delay_dqs_n
|
(
|
(
|
.A (ddr2_dqs_n_fpga[dqswd]),
|
.A (ddr2_dqs_n_fpga[dqswd]),
|
.B (ddr2_dqs_n_sdram[dqswd]),
|
.B (ddr2_dqs_n_sdram[dqswd]),
|
.reset (rst_n)
|
.reset (rst_n)
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
|
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
|
parameter NUM_PROGRAM_WORDS=1048576;
|
parameter NUM_PROGRAM_WORDS=1048576;
|
integer ram_ptr, program_word_ptr, k;
|
integer ram_ptr, program_word_ptr, k;
|
reg [31:0] tmp_program_word;
|
reg [31:0] tmp_program_word;
|
reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB
|
reg [31:0] program_array [0:NUM_PROGRAM_WORDS-1]; // 1M words = 4MB
|
reg [8*16-1:0] ddr2_ram_mem_line; //8*16-bits= 8 shorts (half-words)
|
reg [8*16-1:0] ddr2_ram_mem_line; //8*16-bits= 8 shorts (half-words)
|
genvar i, j;
|
genvar i, j;
|
generate
|
generate
|
// if the data width is multiple of 16
|
// if the data width is multiple of 16
|
for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs // Loop of 1
|
for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs // Loop of 1
|
for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen // Loop of 4 (DQS_WIDTH=8)
|
for(i = 0; i < DQS_WIDTH/2; i = i+1) begin : gen // Loop of 4 (DQS_WIDTH=8)
|
initial
|
initial
|
begin
|
begin
|
|
|
`ifdef PRELOAD_RAM
|
`ifdef PRELOAD_RAM
|
`include "ddr2_model_preload.v"
|
`include "ddr2_model_preload.v"
|
`endif
|
`endif
|
|
end
|
|
|
ddr2_model u_mem0
|
ddr2_model u_mem0
|
(
|
(
|
.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),
|
.ck (ddr2_ck_sdram[CLK_WIDTH*i/DQS_WIDTH]),
|
.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),
|
.ck_n (ddr2_ck_n_sdram[CLK_WIDTH*i/DQS_WIDTH]),
|
.cke (ddr2_cke_sdram[j]),
|
.cke (ddr2_cke_sdram[j]),
|
.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]),
|
.cs_n (ddr2_cs_n_sdram[CS_WIDTH*i/DQS_WIDTH]),
|
.ras_n (ddr2_ras_n_sdram),
|
.ras_n (ddr2_ras_n_sdram),
|
.cas_n (ddr2_cas_n_sdram),
|
.cas_n (ddr2_cas_n_sdram),
|
.we_n (ddr2_we_n_sdram),
|
.we_n (ddr2_we_n_sdram),
|
.dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
|
.dm_rdqs (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
|
.ba (ddr2_ba_sdram),
|
.ba (ddr2_ba_sdram),
|
.addr (ddr2_a_sdram),
|
.addr (ddr2_a_sdram),
|
.dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
|
.dq (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
|
.dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]),
|
.dqs (ddr2_dqs_sdram[(2*(i+1))-1 : i*2]),
|
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]),
|
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1))-1 : i*2]),
|
.rdqs_n (),
|
.rdqs_n (),
|
.odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH])
|
.odt (ddr2_odt_sdram[ODT_WIDTH*i/DQS_WIDTH])
|
);
|
);
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
`endif
|
`endif
|
|
|
|
|
`ifdef VCD
|
`ifdef VCD
|
reg vcd_go = 0;
|
reg vcd_go = 0;
|
always @(vcd_go)
|
always @(vcd_go)
|
begin
|
begin
|
|
|
`ifdef VCD_DELAY
|
`ifdef VCD_DELAY
|
#(`VCD_DELAY);
|
#(`VCD_DELAY);
|
`endif
|
`endif
|
|
|
// Delay by x insns
|
// Delay by x insns
|
`ifdef VCD_DELAY_INSNS
|
`ifdef VCD_DELAY_INSNS
|
#10; // Delay until after the value becomes valid
|
#10; // Delay until after the value becomes valid
|
while (monitor.insns < `VCD_DELAY_INSNS)
|
while (monitor.insns < `VCD_DELAY_INSNS)
|
@(posedge clk);
|
@(posedge clk);
|
`endif
|
`endif
|
|
|
`ifdef SIMULATOR_MODELSIM
|
`ifdef SIMULATOR_MODELSIM
|
// Modelsim can GZip VCDs on the fly if given in the suffix
|
// Modelsim can GZip VCDs on the fly if given in the suffix
|
`define VCD_SUFFIX ".vcd.gz"
|
`define VCD_SUFFIX ".vcd.gz"
|
`else
|
`else
|
`define VCD_SUFFIX ".vcd"
|
`define VCD_SUFFIX ".vcd"
|
`endif
|
`endif
|
|
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
`endif
|
`endif
|
$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
|
`ifndef VCD_DEPTH
|
`ifndef VCD_DEPTH
|
`define VCD_DEPTH 0
|
`define VCD_DEPTH 0
|
`endif
|
`endif
|
$dumpvars(`VCD_DEPTH);
|
$dumpvars(`VCD_DEPTH);
|
|
|
end
|
end
|
`endif // `ifdef VCD
|
`endif // `ifdef VCD
|
|
|
initial
|
initial
|
begin
|
begin
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
|
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
|
`TEST_NAME_STRING );
|
`TEST_NAME_STRING );
|
`endif
|
`endif
|
|
|
`ifdef VCD
|
`ifdef VCD
|
vcd_go = 1;
|
vcd_go = 1;
|
`endif
|
`endif
|
|
|
end // initial begin
|
end // initial begin
|
|
|
`ifdef END_TIME
|
`ifdef END_TIME
|
initial begin
|
initial begin
|
#(`END_TIME);
|
#(`END_TIME);
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("* Finish simulation due to END_TIME being set at %t", $time);
|
$display("* Finish simulation due to END_TIME being set at %t", $time);
|
`endif
|
`endif
|
$finish;
|
$finish;
|
end
|
end
|
`endif
|
`endif
|
|
|
`ifdef END_INSNS
|
`ifdef END_INSNS
|
initial begin
|
initial begin
|
#10
|
#10
|
while (monitor.insns < `END_INSNS)
|
while (monitor.insns < `END_INSNS)
|
@(posedge clk);
|
@(posedge clk);
|
`ifndef SIM_QUIET
|
`ifndef SIM_QUIET
|
$display("* Finish simulation due to END_INSNS count (%d) reached at %t",
|
$display("* Finish simulation due to END_INSNS count (%d) reached at %t",
|
`END_INSNS, $time);
|
`END_INSNS, $time);
|
`endif
|
`endif
|
$finish;
|
$finish;
|
end
|
end
|
`endif
|
`endif
|
|
|
`ifdef UART0
|
`ifdef UART0
|
//
|
//
|
// UART0 decoder
|
// UART0 decoder
|
//
|
//
|
uart_decoder
|
uart_decoder
|
#(
|
#(
|
.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
|
.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
|
)
|
)
|
uart0_decoder
|
uart0_decoder
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.uart_tx(uart0_stx_pad_o)
|
.uart_tx(uart0_stx_pad_o)
|
);
|
);
|
|
|
// Loopback UART lines
|
// Loopback UART lines
|
assign uart0_srx_pad_i = uart0_stx_pad_o;
|
assign uart0_srx_pad_i = uart0_stx_pad_o;
|
|
|
`endif // `ifdef UART0
|
`endif // `ifdef UART0
|
|
|
endmodule // orpsoc_testbench
|
endmodule // orpsoc_testbench
|
|
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
|
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
|
// verilog-library-files:()
|
// verilog-library-files:()
|
// verilog-library-extensions:(".v" ".h")
|
// verilog-library-extensions:(".v" ".h")
|
// End:
|
// End:
|
|
|
|
|
