/*
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/*
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*
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*
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* Clock, reset generation unit for ML501 board
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* Clock, reset generation unit for ML501 board
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*
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*
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* Implements clock generation according to design defines
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* Implements clock generation according to design defines
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*
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*
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*/
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*/
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "orpsoc-defines.v"
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`include "orpsoc-defines.v"
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`include "synthesis-defines.v"
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`include "synthesis-defines.v"
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module clkgen
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module clkgen
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(
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(
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// Main clocks in, depending on board
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// Main clocks in, depending on board
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sys_clk_in_p, sys_clk_in_n,
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sys_clk_in_p, sys_clk_in_n,
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// Wishbone clock and reset out
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// Wishbone clock and reset out
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wb_clk_o,
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wb_clk_o,
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wb_rst_o,
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wb_rst_o,
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// JTAG clock
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// JTAG clock
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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tck_pad_i,
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tck_pad_i,
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dbg_tck_o,
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dbg_tck_o,
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`endif
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`endif
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// Main memory clocks
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// Main memory clocks
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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ddr2_if_clk_o,
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ddr2_if_clk_o,
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ddr2_if_rst_o,
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ddr2_if_rst_o,
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clk200_o,
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clk200_o,
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`endif
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`endif
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// Asynchronous, active low reset in
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// Asynchronous, active low reset in
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rst_n_pad_i
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rst_n_pad_i
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);
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);
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input sys_clk_in_p,sys_clk_in_n;
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input sys_clk_in_p,sys_clk_in_n;
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output wb_rst_o;
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output wb_rst_o;
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output wb_clk_o;
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output wb_clk_o;
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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input tck_pad_i;
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input tck_pad_i;
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output dbg_tck_o;
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output dbg_tck_o;
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`endif
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`endif
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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output ddr2_if_clk_o;
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output ddr2_if_clk_o;
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output ddr2_if_rst_o;
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output ddr2_if_rst_o;
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output clk200_o;
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output clk200_o;
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`endif
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`endif
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// Asynchronous, active low reset (pushbutton, typically)
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// Asynchronous, active low reset (pushbutton, typically)
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input rst_n_pad_i;
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input rst_n_pad_i;
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// First, deal with the asychronous reset
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// First, deal with the asychronous reset
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wire async_rst;
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wire async_rst;
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wire async_rst_n;
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wire async_rst_n;
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// Xilinx synthesis tools appear cluey enough to instantiate buffers when and
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// Xilinx synthesis tools appear cluey enough to instantiate buffers when and
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// where they're needed, so we do simple assigns for this tech.
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// where they're needed, so we do simple assigns for this tech.
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assign async_rst_n = rst_n_pad_i;
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assign async_rst_n = rst_n_pad_i;
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// Everyone likes active-high reset signals...
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// Everyone likes active-high reset signals...
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assign async_rst = ~async_rst_n;
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assign async_rst = ~async_rst_n;
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`ifdef JTAG_DEBUG
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`ifdef JTAG_DEBUG
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assign dbg_tck_o = tck_pad_i;
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assign dbg_tck_o = tck_pad_i;
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`endif
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`endif
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//
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//
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// Declare synchronous reset wires here
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// Declare synchronous reset wires here
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//
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//
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// An active-low synchronous reset signal (usually a PLL lock signal)
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// An active-low synchronous reset signal (usually a PLL lock signal)
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wire sync_rst_n;
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wire sync_rst_n;
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// An active-low synchronous reset from ethernet PLL
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// An active-low synchronous reset from ethernet PLL
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wire sync_eth_rst_n;
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wire sync_eth_rst_n;
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wire sys_clk_in_200;
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wire sys_clk_in_200;
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/* DCM0 wires */
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/* DCM0 wires */
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wire dcm0_clk0_prebufg, dcm0_clk0;
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wire dcm0_clk0_prebufg, dcm0_clk0;
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wire dcm0_clkfx_prebufg, dcm0_clkfx;
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wire dcm0_clkfx_prebufg, dcm0_clkfx;
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wire dcm0_clkdv_prebufg, dcm0_clkdv;
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wire dcm0_clkdv_prebufg, dcm0_clkdv;
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wire dcm0_locked;
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wire dcm0_locked;
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/* Dif. input buffer for 200MHz board clock, generate SE 200MHz */
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/* Dif. input buffer for 200MHz board clock, generate SE 200MHz */
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IBUFGDS_LVPECL_25 sys_clk_in_ibufds
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IBUFGDS_LVPECL_25 sys_clk_in_ibufds
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(
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(
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.O(sys_clk_in_200),
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.O(sys_clk_in_200),
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.I(sys_clk_in_p),
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.I(sys_clk_in_p),
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.IB(sys_clk_in_n));
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.IB(sys_clk_in_n));
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/* DCM providing main system/Wishbone clock */
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/* DCM providing main system/Wishbone clock */
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DCM_BASE dcm0
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DCM_BASE dcm0
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(
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(
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// Outputs
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// Outputs
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.CLK0 (dcm0_clk0_prebufg),
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.CLK0 (dcm0_clk0_prebufg),
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.CLK180 (),
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.CLK180 (),
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.CLK270 (),
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.CLK270 (),
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.CLK2X180 (),
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.CLK2X180 (),
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.CLK2X (),
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.CLK2X (),
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.CLK90 (),
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.CLK90 (),
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.CLKDV (dcm0_clkdv_prebufg),
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.CLKDV (dcm0_clkdv_prebufg),
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.CLKFX180 (),
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.CLKFX180 (),
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.CLKFX (dcm0_clkfx_prebufg),
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.CLKFX (dcm0_clkfx_prebufg),
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.LOCKED (dcm0_locked),
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.LOCKED (dcm0_locked),
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// Inputs
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// Inputs
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.CLKFB (dcm0_clk0),
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.CLKFB (dcm0_clk0),
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.CLKIN (sys_clk_in_200),
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.CLKIN (sys_clk_in_200),
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.RST (1'b0));
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.RST (1'b0));
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// Generate 266 MHz from CLKFX
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// Generate 266 MHz from CLKFX
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defparam dcm0.CLKFX_MULTIPLY = 4;
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defparam dcm0.CLKFX_MULTIPLY = 4;
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defparam dcm0.CLKFX_DIVIDE = 3;
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defparam dcm0.CLKFX_DIVIDE = 3;
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// Generate 50 MHz from CLKDV
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// Generate 66 MHz from CLKDV
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defparam dcm0.CLKDV_DIVIDE = 4.0;
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defparam dcm0.CLKDV_DIVIDE = 3.0;
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BUFG dcm0_clk0_bufg
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BUFG dcm0_clk0_bufg
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(// Outputs
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(// Outputs
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.O (dcm0_clk0),
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.O (dcm0_clk0),
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// Inputs
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// Inputs
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.I (dcm0_clk0_prebufg));
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.I (dcm0_clk0_prebufg));
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BUFG dcm0_clkfx_bufg
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BUFG dcm0_clkfx_bufg
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(// Outputs
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(// Outputs
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.O (dcm0_clkfx),
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.O (dcm0_clkfx),
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// Inputs
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// Inputs
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.I (dcm0_clkfx_prebufg));
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.I (dcm0_clkfx_prebufg));
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BUFG dcm0_clkdv_bufg
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BUFG dcm0_clkdv_bufg
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(// Outputs
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(// Outputs
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.O (dcm0_clkdv),
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.O (dcm0_clkdv),
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// Inputs
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// Inputs
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.I (dcm0_clkdv_prebufg));
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.I (dcm0_clkdv_prebufg));
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assign wb_clk_o = dcm0_clkdv;
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assign wb_clk_o = dcm0_clkdv;
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assign sync_rst_n = dcm0_locked;
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assign sync_rst_n = dcm0_locked;
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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assign ddr2_if_clk_o = dcm0_clkfx; // 266MHz
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assign ddr2_if_clk_o = dcm0_clkfx; // 266MHz
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assign clk200_o = dcm0_clk0; // 200MHz
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assign clk200_o = dcm0_clk0; // 200MHz
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`endif
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`endif
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//
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//
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// Reset generation
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// Reset generation
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//
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//
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//
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//
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// Reset generation for wishbone
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// Reset generation for wishbone
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reg [15:0] wb_rst_shr;
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reg [15:0] wb_rst_shr;
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always @(posedge wb_clk_o or posedge async_rst)
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always @(posedge wb_clk_o or posedge async_rst)
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if (async_rst)
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if (async_rst)
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wb_rst_shr <= 16'hffff;
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wb_rst_shr <= 16'hffff;
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else
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else
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wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
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wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
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assign wb_rst_o = wb_rst_shr[15];
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assign wb_rst_o = wb_rst_shr[15];
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`ifdef XILINX_DDR2
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`ifdef XILINX_DDR2
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// Reset generation for DDR2 controller
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// Reset generation for DDR2 controller
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reg [15:0] ddr2_if_rst_shr;
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reg [15:0] ddr2_if_rst_shr;
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always @(posedge ddr2_if_clk_o or posedge async_rst)
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always @(posedge ddr2_if_clk_o or posedge async_rst)
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if (async_rst)
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if (async_rst)
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ddr2_if_rst_shr <= 16'hffff;
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ddr2_if_rst_shr <= 16'hffff;
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else
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else
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ddr2_if_rst_shr <= {ddr2_if_rst_shr[14:0], ~(sync_rst_n)};
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ddr2_if_rst_shr <= {ddr2_if_rst_shr[14:0], ~(sync_rst_n)};
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assign ddr2_if_rst_o = ddr2_if_rst_shr[15];
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assign ddr2_if_rst_o = ddr2_if_rst_shr[15];
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`endif
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`endif
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endmodule // clkgen
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endmodule // clkgen
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