/*
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/*
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* Wrapper for Xilinx MIG'd DDR2 controller, allowing 3 masters
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* Wrapper for Xilinx MIG'd DDR2 controller, allowing 3 masters
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* to contol the single interface.
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* to contol the single interface.
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*/
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*/
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module xilinx_ddr2
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module xilinx_ddr2
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(
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(
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// Inputs
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// Inputs
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input [31:0] wbm0_adr_i,
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input [31:0] wbm0_adr_i,
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input [1:0] wbm0_bte_i,
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input [1:0] wbm0_bte_i,
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input [2:0] wbm0_cti_i,
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input [2:0] wbm0_cti_i,
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input wbm0_cyc_i,
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input wbm0_cyc_i,
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input [31:0] wbm0_dat_i,
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input [31:0] wbm0_dat_i,
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input [3:0] wbm0_sel_i,
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input [3:0] wbm0_sel_i,
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input wbm0_stb_i,
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input wbm0_stb_i,
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input wbm0_we_i,
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input wbm0_we_i,
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// Outputs
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// Outputs
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output wbm0_ack_o,
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output wbm0_ack_o,
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output wbm0_err_o,
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output wbm0_err_o,
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output wbm0_rty_o,
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output wbm0_rty_o,
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output [31:0] wbm0_dat_o,
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output [31:0] wbm0_dat_o,
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// Inputs
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// Inputs
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input [31:0] wbm1_adr_i,
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input [31:0] wbm1_adr_i,
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input [1:0] wbm1_bte_i,
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input [1:0] wbm1_bte_i,
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input [2:0] wbm1_cti_i,
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input [2:0] wbm1_cti_i,
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input wbm1_cyc_i,
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input wbm1_cyc_i,
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input [31:0] wbm1_dat_i,
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input [31:0] wbm1_dat_i,
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input [3:0] wbm1_sel_i,
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input [3:0] wbm1_sel_i,
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input wbm1_stb_i,
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input wbm1_stb_i,
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input wbm1_we_i,
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input wbm1_we_i,
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// Outputs
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// Outputs
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output wbm1_ack_o,
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output wbm1_ack_o,
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output wbm1_err_o,
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output wbm1_err_o,
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output wbm1_rty_o,
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output wbm1_rty_o,
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output [31:0] wbm1_dat_o,
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output [31:0] wbm1_dat_o,
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// Inputs
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// Inputs
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input [31:0] wbm2_adr_i,
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input [31:0] wbm2_adr_i,
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input [1:0] wbm2_bte_i,
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input [1:0] wbm2_bte_i,
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input [2:0] wbm2_cti_i,
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input [2:0] wbm2_cti_i,
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input wbm2_cyc_i,
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input wbm2_cyc_i,
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input [31:0] wbm2_dat_i,
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input [31:0] wbm2_dat_i,
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input [3:0] wbm2_sel_i,
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input [3:0] wbm2_sel_i,
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input wbm2_stb_i,
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input wbm2_stb_i,
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input wbm2_we_i,
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input wbm2_we_i,
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// Outputs
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// Outputs
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output wbm2_ack_o,
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output wbm2_ack_o,
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output wbm2_err_o,
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output wbm2_err_o,
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output wbm2_rty_o,
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output wbm2_rty_o,
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output [31:0] wbm2_dat_o,
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output [31:0] wbm2_dat_o,
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input wb_clk,
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input wb_clk,
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input wb_rst,
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input wb_rst,
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output [12:0] ddr2_a,
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output [12:0] ddr2_a,
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output [1:0] ddr2_ba,
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output [1:0] ddr2_ba,
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output ddr2_ras_n,
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output ddr2_ras_n,
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output ddr2_cas_n,
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output ddr2_cas_n,
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output ddr2_we_n,
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output ddr2_we_n,
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output [1:0] ddr2_cs_n,
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output [1:0] ddr2_cs_n,
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output [1:0] ddr2_odt,
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output [1:0] ddr2_odt,
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output [1:0] ddr2_cke,
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output [1:0] ddr2_cke,
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output [7:0] ddr2_dm,
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output [7:0] ddr2_dm,
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inout [63:0] ddr2_dq,
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inout [63:0] ddr2_dq,
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inout [7:0] ddr2_dqs,
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inout [7:0] ddr2_dqs,
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inout [7:0] ddr2_dqs_n,
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inout [7:0] ddr2_dqs_n,
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output [1:0] ddr2_ck,
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output [1:0] ddr2_ck,
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output [1:0] ddr2_ck_n,
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output [1:0] ddr2_ck_n,
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input ddr2_if_clk,
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input ddr2_if_clk,
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input clk200,
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input clk200,
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input ddr2_if_rst
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input ddr2_if_rst
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);
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);
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// Internal wires to actual RAM
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// Internal wires to actual RAM
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wire [31:0] wbs_ram_adr_i;
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wire [31:0] wbs_ram_adr_i;
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wire [1:0] wbs_ram_bte_i;
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wire [1:0] wbs_ram_bte_i;
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wire [2:0] wbs_ram_cti_i;
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wire [2:0] wbs_ram_cti_i;
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wire wbs_ram_cyc_i;
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wire wbs_ram_cyc_i;
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wire [31:0] wbs_ram_dat_i;
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wire [31:0] wbs_ram_dat_i;
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wire [3:0] wbs_ram_sel_i;
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wire [3:0] wbs_ram_sel_i;
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wire wbs_ram_stb_i;
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wire wbs_ram_stb_i;
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wire wbs_ram_we_i;
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wire wbs_ram_we_i;
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wire wbs_ram_ack_o;
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wire wbs_ram_ack_o;
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wire [31:0] wbs_ram_dat_o;
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wire [31:0] wbs_ram_dat_o;
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reg [2:0] input_select, last_selected;
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reg [2:0] input_select, last_selected;
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wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
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wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
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// Wires allowing selection of new input
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// Wires allowing selection of new input
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assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
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assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
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!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
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!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
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assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
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assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
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!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
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!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
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assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
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assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
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!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
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!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
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// Master select logic
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// Master select logic
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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if (wb_rst)
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if (wb_rst)
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input_select <= 0;
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input_select <= 0;
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else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
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else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
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| (input_select[2] & !wbm2_cyc_i))
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| (input_select[2] & !wbm2_cyc_i))
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input_select <= 0;
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input_select <= 0;
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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input_select <= 3'b001;
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input_select <= 3'b001;
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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input_select <= 3'b010;
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input_select <= 3'b010;
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else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
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else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
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input_select <= 3'b100;
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input_select <= 3'b100;
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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if (wb_rst)
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if (wb_rst)
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last_selected <= 0;
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last_selected <= 0;
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
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last_selected <= 3'b001;
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last_selected <= 3'b001;
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
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last_selected <= 3'b010;
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last_selected <= 3'b010;
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else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
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else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
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last_selected <= 3'b100;
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last_selected <= 3'b100;
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// Mux input signals to RAM (default to wbm0)
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// Mux input signals to RAM (default to wbm0)
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assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
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assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
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(input_select[1]) ? wbm1_adr_i :
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(input_select[1]) ? wbm1_adr_i :
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(input_select[0]) ? wbm0_adr_i : 0;
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(input_select[0]) ? wbm0_adr_i : 0;
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assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
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assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
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(input_select[1]) ? wbm1_bte_i :
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(input_select[1]) ? wbm1_bte_i :
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(input_select[0]) ? wbm0_bte_i : 0;
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(input_select[0]) ? wbm0_bte_i : 0;
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assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
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assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
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(input_select[1]) ? wbm1_cti_i :
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(input_select[1]) ? wbm1_cti_i :
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(input_select[0]) ? wbm0_cti_i : 0;
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(input_select[0]) ? wbm0_cti_i : 0;
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assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
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assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
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(input_select[1]) ? wbm1_cyc_i :
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(input_select[1]) ? wbm1_cyc_i :
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(input_select[0]) ? wbm0_cyc_i : 0;
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(input_select[0]) ? wbm0_cyc_i : 0;
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assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
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assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
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(input_select[1]) ? wbm1_dat_i :
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(input_select[1]) ? wbm1_dat_i :
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(input_select[0]) ? wbm0_dat_i : 0;
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(input_select[0]) ? wbm0_dat_i : 0;
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assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
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assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
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(input_select[1]) ? wbm1_sel_i :
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(input_select[1]) ? wbm1_sel_i :
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(input_select[0]) ? wbm0_sel_i : 0;
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(input_select[0]) ? wbm0_sel_i : 0;
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assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
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assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
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(input_select[1]) ? wbm1_stb_i :
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(input_select[1]) ? wbm1_stb_i :
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(input_select[0]) ? wbm0_stb_i : 0;
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(input_select[0]) ? wbm0_stb_i : 0;
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assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
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assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
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(input_select[1]) ? wbm1_we_i :
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(input_select[1]) ? wbm1_we_i :
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(input_select[0]) ? wbm0_we_i : 0;
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(input_select[0]) ? wbm0_we_i : 0;
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// Output from RAM, gate the ACK, ERR, RTY signals appropriately
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// Output from RAM, gate the ACK, ERR, RTY signals appropriately
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assign wbm0_dat_o = wbs_ram_dat_o;
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assign wbm0_dat_o = wbs_ram_dat_o;
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assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
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assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
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assign wbm0_err_o = 0;
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assign wbm0_err_o = 0;
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assign wbm0_rty_o = 0;
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assign wbm0_rty_o = 0;
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assign wbm1_dat_o = wbs_ram_dat_o;
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assign wbm1_dat_o = wbs_ram_dat_o;
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assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
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assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
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assign wbm1_err_o = 0;
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assign wbm1_err_o = 0;
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assign wbm1_rty_o = 0;
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assign wbm1_rty_o = 0;
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assign wbm2_dat_o = wbs_ram_dat_o;
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assign wbm2_dat_o = wbs_ram_dat_o;
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assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
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assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
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assign wbm2_err_o = 0;
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assign wbm2_err_o = 0;
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assign wbm2_rty_o = 0;
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assign wbm2_rty_o = 0;
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xilinx_ddr2_if xilinx_ddr2_if0
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xilinx_ddr2_if xilinx_ddr2_if0
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(
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(
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.wb_dat_o (wbs_ram_dat_o),
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.wb_dat_o (wbs_ram_dat_o),
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.wb_ack_o (wbs_ram_ack_o),
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.wb_ack_o (wbs_ram_ack_o),
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.wb_adr_i (wbs_ram_adr_i[31:0]),
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.wb_adr_i (wbs_ram_adr_i[31:0]),
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.wb_stb_i (wbs_ram_stb_i),
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.wb_stb_i (wbs_ram_stb_i),
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.wb_cti_i (wbs_ram_cti_i),
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.wb_bte_i (wbs_ram_bte_i),
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.wb_cyc_i (wbs_ram_cyc_i),
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.wb_cyc_i (wbs_ram_cyc_i),
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.wb_we_i (wbs_ram_we_i),
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.wb_we_i (wbs_ram_we_i),
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.wb_sel_i (wbs_ram_sel_i[3:0]),
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.wb_sel_i (wbs_ram_sel_i[3:0]),
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.wb_dat_i (wbs_ram_dat_i[31:0]),
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.wb_dat_i (wbs_ram_dat_i[31:0]),
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.ddr2_a (ddr2_a[12:0]),
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.ddr2_a (ddr2_a[12:0]),
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.ddr2_ba (ddr2_ba[1:0]),
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.ddr2_ba (ddr2_ba[1:0]),
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.ddr2_ras_n (ddr2_ras_n),
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.ddr2_ras_n (ddr2_ras_n),
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.ddr2_cas_n (ddr2_cas_n),
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.ddr2_cas_n (ddr2_cas_n),
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.ddr2_we_n (ddr2_we_n),
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.ddr2_we_n (ddr2_we_n),
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.ddr2_cs_n (ddr2_cs_n),
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.ddr2_cs_n (ddr2_cs_n),
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.ddr2_odt (ddr2_odt),
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.ddr2_odt (ddr2_odt),
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.ddr2_cke (ddr2_cke),
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.ddr2_cke (ddr2_cke),
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.ddr2_dm (ddr2_dm[7:0]),
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.ddr2_dm (ddr2_dm[7:0]),
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.ddr2_ck (ddr2_ck[1:0]),
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.ddr2_ck (ddr2_ck[1:0]),
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.ddr2_ck_n (ddr2_ck_n[1:0]),
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.ddr2_ck_n (ddr2_ck_n[1:0]),
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.ddr2_dq (ddr2_dq[63:0]),
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.ddr2_dq (ddr2_dq[63:0]),
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.ddr2_dqs (ddr2_dqs[7:0]),
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.ddr2_dqs (ddr2_dqs[7:0]),
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.ddr2_dqs_n (ddr2_dqs_n[7:0]),
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.ddr2_dqs_n (ddr2_dqs_n[7:0]),
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.ddr2_if_clk (ddr2_if_clk),
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.ddr2_if_clk (ddr2_if_clk),
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.idly_clk_200 (clk200),
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.idly_clk_200 (clk200),
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.ddr2_if_rst (ddr2_if_rst),
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.ddr2_if_rst (ddr2_if_rst),
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.wb_clk (wb_clk),
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.wb_clk (wb_clk),
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.wb_rst (wb_rst));
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.wb_rst (wb_rst));
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endmodule
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endmodule
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