#ifndef _BOARD_H_
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#define _BOARD_H_
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#define IN_CLK 50000000 // Hz
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#define IN_CLK 50000000 // Hz
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//#define IN_CLK 32000000 // Hz
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//#define IN_CLK 32000000 // Hz
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//#define IN_CLK 30000000 // HZ
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//#define IN_CLK 30000000 // HZ
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//#define IN_CLK 24000000 // HZ
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//#define IN_CLK 24000000 // HZ
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//#define IN_CLK 20000000 // HZ
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//#define IN_CLK 20000000 // HZ
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//#define IN_CLK 18000000 // HZ
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//#define IN_CLK 18000000 // HZ
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//#define IN_CLK 16000000 // HZ
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//#define IN_CLK 16000000 // HZ
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//
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//
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// ROM bootloader
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// ROM bootloader
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//
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//
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// Uncomment the appropriate bootloader define. This will effect the bootrom.S
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// Uncomment the appropriate bootloader define. This will effect the bootrom.S
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// file, which is compiled and converted into Verilog for inclusion at
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// file, which is compiled and converted into Verilog for inclusion at
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// synthesis time. See bootloader/bootloader.S for details on each option.
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// synthesis time. See bootloader/bootloader.S for details on each option.
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//#define BOOTROM_SPI_FLASH
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#define BOOTROM_SPI_FLASH
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#define BOOTROM_GOTO_RESET
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//#define BOOTROM_GOTO_RESET
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//#define BOOTROM_LOOP_AT_ZERO
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//#define BOOTROM_LOOP_AT_ZERO
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//#define BOOTROM_LOOP_IN_ROM
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//#define BOOTROM_LOOP_IN_ROM
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// Address bootloader should start from in FLASH
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#define BOOTROM_ADDR_BYTE2 0x1c
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#define BOOTROM_ADDR_BYTE1 0x00
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#define BOOTROM_ADDR_BYTE0 0x00
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// Causes SPI bootloader to loop if SPI didn't give correct size of image
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#define SPI_RETRY_IF_INSANE_SIZEWORD
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//
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//
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// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
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// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
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//
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//
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#define SDRAM_BASE 0x0
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#define SDRAM_BASE 0x0
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#define GPIO_0_BASE 0x91000000
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#define GPIO_0_BASE 0x91000000
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#define UART0_BASE 0x90000000
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#define UART0_BASE 0x90000000
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#define UART0_IRQ 2
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#define UART0_IRQ 2
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#define UART0_BAUD_RATE 115200
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#define UART0_BAUD_RATE 115200
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#define SPI0_BASE 0xb0000000
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#define SPI0_BASE 0xb0000000
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#define SPI0_IRQ 6
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#define SPI0_IRQ 6
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#define I2C_0_BASE 0xa0000000
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#define I2C_0_BASE 0xa0000000
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#define I2C_0_IRQ 10
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#define I2C_0_IRQ 10
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#define I2C_1_BASE 0xa1000000
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#define I2C_1_BASE 0xa1000000
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#define I2C_1_IRQ 11
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#define I2C_1_IRQ 11
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#define ETH0_BASE 0x92000000
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#define ETH0_BASE 0x92000000
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#define ETH0_IRQ 4
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#define ETH0_IRQ 4
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#define ETH_MACADDR0 0x00
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#define ETH_MACADDR0 0x00
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#define ETH_MACADDR1 0x12
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#define ETH_MACADDR1 0x12
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#define ETH_MACADDR2 0x34
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#define ETH_MACADDR2 0x34
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#define ETH_MACADDR3 0x56
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#define ETH_MACADDR3 0x56
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#define ETH_MACADDR4 0x78
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#define ETH_MACADDR4 0x78
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#define ETH_MACADDR5 0x9a
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#define ETH_MACADDR5 0x9a
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//
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//
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// OR1200 tick timer period define
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// OR1200 tick timer period define
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//
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//
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#define TICKS_PER_SEC 100
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#define TICKS_PER_SEC 100
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#endif
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#endif
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