//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// eth_rxethmac.v ////
|
//// eth_rxethmac.v ////
|
//// ////
|
//// ////
|
//// This file is part of the Ethernet IP core project ////
|
//// This file is part of the Ethernet IP core project ////
|
//// http://www.opencores.org/project,ethmac ////
|
//// http://www.opencores.org/project,ethmac ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Igor Mohor (igorM@opencores.org) ////
|
//// - Igor Mohor (igorM@opencores.org) ////
|
//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
|
//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
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//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
|
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
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//// ////
|
//// ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// file. ////
|
//// file. ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
|
//// Copyright (C) 2001 Authors ////
|
//// Copyright (C) 2001 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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|
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`include "timescale.v"
|
`include "timescale.v"
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|
|
|
|
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
|
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
|
HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
|
HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
|
ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
|
ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
|
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
|
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
|
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
|
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
|
PassAll, ControlFrmAddressOK
|
PassAll, ControlFrmAddressOK
|
);
|
);
|
|
|
input MRxClk;
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input MRxClk;
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input MRxDV;
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input MRxDV;
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input [3:0] MRxD;
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input [3:0] MRxD;
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input Transmitting;
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input Transmitting;
|
input HugEn;
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input HugEn;
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input DlyCrcEn;
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input DlyCrcEn;
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input [15:0] MaxFL;
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input [15:0] MaxFL;
|
input r_IFG;
|
input r_IFG;
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input Reset;
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input Reset;
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input [47:0] MAC; // Station Address
|
input [47:0] MAC; // Station Address
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input r_Bro; // broadcast disable
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input r_Bro; // broadcast disable
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input r_Pro; // promiscuous enable
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input r_Pro; // promiscuous enable
|
input [31:0] r_HASH0; // lower 4 bytes Hash Table
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input [31:0] r_HASH0; // lower 4 bytes Hash Table
|
input [31:0] r_HASH1; // upper 4 bytes Hash Table
|
input [31:0] r_HASH1; // upper 4 bytes Hash Table
|
input PassAll;
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input PassAll;
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input ControlFrmAddressOK;
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input ControlFrmAddressOK;
|
|
|
output [7:0] RxData;
|
output [7:0] RxData;
|
output RxValid;
|
output RxValid;
|
output RxStartFrm;
|
output RxStartFrm;
|
output RxEndFrm;
|
output RxEndFrm;
|
output [15:0] ByteCnt;
|
output [15:0] ByteCnt;
|
output ByteCntEq0;
|
output ByteCntEq0;
|
output ByteCntGreat2;
|
output ByteCntGreat2;
|
output ByteCntMaxFrame;
|
output ByteCntMaxFrame;
|
output CrcError;
|
output CrcError;
|
output StateIdle;
|
output StateIdle;
|
output StatePreamble;
|
output StatePreamble;
|
output StateSFD;
|
output StateSFD;
|
output [1:0] StateData;
|
output [1:0] StateData;
|
output RxAbort;
|
output RxAbort;
|
output AddressMiss;
|
output AddressMiss;
|
|
|
reg [7:0] RxData;
|
reg [7:0] RxData;
|
reg RxValid;
|
reg RxValid;
|
reg RxStartFrm;
|
reg RxStartFrm;
|
reg RxEndFrm;
|
reg RxEndFrm;
|
reg Broadcast;
|
reg Broadcast;
|
reg Multicast;
|
reg Multicast;
|
reg [5:0] CrcHash;
|
reg [5:0] CrcHash;
|
reg CrcHashGood;
|
reg CrcHashGood;
|
reg DelayData;
|
reg DelayData;
|
reg [7:0] LatchedByte;
|
reg [7:0] LatchedByte;
|
reg [7:0] RxData_d;
|
reg [7:0] RxData_d;
|
reg RxValid_d;
|
reg RxValid_d;
|
reg RxStartFrm_d;
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reg RxStartFrm_d;
|
reg RxEndFrm_d;
|
reg RxEndFrm_d;
|
|
|
wire MRxDEqD;
|
wire MRxDEqD;
|
wire MRxDEq5;
|
wire MRxDEq5;
|
wire StateDrop;
|
wire StateDrop;
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wire ByteCntEq1;
|
wire ByteCntEq1;
|
wire ByteCntEq2;
|
wire ByteCntEq2;
|
wire ByteCntEq3;
|
wire ByteCntEq3;
|
wire ByteCntEq4;
|
wire ByteCntEq4;
|
wire ByteCntEq5;
|
wire ByteCntEq5;
|
wire ByteCntEq6;
|
wire ByteCntEq6;
|
wire ByteCntEq7;
|
wire ByteCntEq7;
|
wire ByteCntSmall7;
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wire ByteCntSmall7;
|
wire [31:0] Crc;
|
wire [31:0] Crc;
|
wire Enable_Crc;
|
wire Enable_Crc;
|
wire Initialize_Crc;
|
wire Initialize_Crc;
|
wire [3:0] Data_Crc;
|
wire [3:0] Data_Crc;
|
wire GenerateRxValid;
|
wire GenerateRxValid;
|
wire GenerateRxStartFrm;
|
wire GenerateRxStartFrm;
|
wire GenerateRxEndFrm;
|
wire GenerateRxEndFrm;
|
wire DribbleRxEndFrm;
|
wire DribbleRxEndFrm;
|
wire [3:0] DlyCrcCnt;
|
wire [3:0] DlyCrcCnt;
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wire IFGCounterEq24;
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wire IFGCounterEq24;
|
|
|
assign MRxDEqD = MRxD == 4'hd;
|
assign MRxDEqD = MRxD == 4'hd;
|
assign MRxDEq5 = MRxD == 4'h5;
|
assign MRxDEq5 = MRxD == 4'h5;
|
|
|
|
|
// Rx State Machine module
|
// Rx State Machine module
|
eth_rxstatem rxstatem1
|
eth_rxstatem rxstatem1
|
(
|
(
|
.MRxClk(MRxClk),
|
.MRxClk(MRxClk),
|
.Reset(Reset),
|
.Reset(Reset),
|
.MRxDV(MRxDV),
|
.MRxDV(MRxDV),
|
.ByteCntEq0(ByteCntEq0),
|
.ByteCntEq0(ByteCntEq0),
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.ByteCntGreat2(ByteCntGreat2),
|
.ByteCntGreat2(ByteCntGreat2),
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.Transmitting(Transmitting),
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.Transmitting(Transmitting),
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.MRxDEq5(MRxDEq5),
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.MRxDEq5(MRxDEq5),
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.MRxDEqD(MRxDEqD),
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.MRxDEqD(MRxDEqD),
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.IFGCounterEq24(IFGCounterEq24),
|
.IFGCounterEq24(IFGCounterEq24),
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.ByteCntMaxFrame(ByteCntMaxFrame),
|
.ByteCntMaxFrame(ByteCntMaxFrame),
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.StateData(StateData),
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.StateData(StateData),
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.StateIdle(StateIdle),
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.StateIdle(StateIdle),
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.StatePreamble(StatePreamble),
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.StatePreamble(StatePreamble),
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.StateSFD(StateSFD),
|
.StateSFD(StateSFD),
|
.StateDrop(StateDrop)
|
.StateDrop(StateDrop)
|
);
|
);
|
|
|
|
|
// Rx Counters module
|
// Rx Counters module
|
eth_rxcounters rxcounters1
|
eth_rxcounters rxcounters1
|
(.MRxClk(MRxClk),
|
(.MRxClk(MRxClk),
|
.Reset(Reset),
|
.Reset(Reset),
|
.MRxDV(MRxDV),
|
.MRxDV(MRxDV),
|
.StateIdle(StateIdle),
|
.StateIdle(StateIdle),
|
.StateSFD(StateSFD),
|
.StateSFD(StateSFD),
|
.StateData(StateData),
|
.StateData(StateData),
|
.StateDrop(StateDrop),
|
.StateDrop(StateDrop),
|
.StatePreamble(StatePreamble),
|
.StatePreamble(StatePreamble),
|
.MRxDEqD(MRxDEqD),
|
.MRxDEqD(MRxDEqD),
|
.DlyCrcEn(DlyCrcEn),
|
.DlyCrcEn(DlyCrcEn),
|
.DlyCrcCnt(DlyCrcCnt),
|
.DlyCrcCnt(DlyCrcCnt),
|
.Transmitting(Transmitting),
|
.Transmitting(Transmitting),
|
.MaxFL(MaxFL),
|
.MaxFL(MaxFL),
|
.r_IFG(r_IFG),
|
.r_IFG(r_IFG),
|
.HugEn(HugEn),
|
.HugEn(HugEn),
|
.IFGCounterEq24(IFGCounterEq24),
|
.IFGCounterEq24(IFGCounterEq24),
|
.ByteCntEq0(ByteCntEq0),
|
.ByteCntEq0(ByteCntEq0),
|
.ByteCntEq1(ByteCntEq1),
|
.ByteCntEq1(ByteCntEq1),
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.ByteCntEq2(ByteCntEq2),
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.ByteCntEq2(ByteCntEq2),
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.ByteCntEq3(ByteCntEq3),
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.ByteCntEq3(ByteCntEq3),
|
.ByteCntEq4(ByteCntEq4),
|
.ByteCntEq4(ByteCntEq4),
|
.ByteCntEq5(ByteCntEq5),
|
.ByteCntEq5(ByteCntEq5),
|
.ByteCntEq6(ByteCntEq6),
|
.ByteCntEq6(ByteCntEq6),
|
.ByteCntEq7(ByteCntEq7),
|
.ByteCntEq7(ByteCntEq7),
|
.ByteCntGreat2(ByteCntGreat2),
|
.ByteCntGreat2(ByteCntGreat2),
|
.ByteCntSmall7(ByteCntSmall7),
|
.ByteCntSmall7(ByteCntSmall7),
|
.ByteCntMaxFrame(ByteCntMaxFrame),
|
.ByteCntMaxFrame(ByteCntMaxFrame),
|
.ByteCntOut(ByteCnt)
|
.ByteCntOut(ByteCnt)
|
);
|
);
|
|
|
// Rx Address Check
|
// Rx Address Check
|
|
|
eth_rxaddrcheck rxaddrcheck1
|
eth_rxaddrcheck rxaddrcheck1
|
(.MRxClk(MRxClk),
|
(.MRxClk(MRxClk),
|
.Reset( Reset),
|
.Reset( Reset),
|
.RxData(RxData),
|
.RxData(RxData),
|
.Broadcast (Broadcast),
|
.Broadcast (Broadcast),
|
.r_Bro (r_Bro),
|
.r_Bro (r_Bro),
|
.r_Pro(r_Pro),
|
.r_Pro(r_Pro),
|
.ByteCntEq6(ByteCntEq6),
|
.ByteCntEq6(ByteCntEq6),
|
.ByteCntEq7(ByteCntEq7),
|
.ByteCntEq7(ByteCntEq7),
|
.ByteCntEq2(ByteCntEq2),
|
.ByteCntEq2(ByteCntEq2),
|
.ByteCntEq3(ByteCntEq3),
|
.ByteCntEq3(ByteCntEq3),
|
.ByteCntEq4(ByteCntEq4),
|
.ByteCntEq4(ByteCntEq4),
|
.ByteCntEq5(ByteCntEq5),
|
.ByteCntEq5(ByteCntEq5),
|
.HASH0(r_HASH0),
|
.HASH0(r_HASH0),
|
.HASH1(r_HASH1),
|
.HASH1(r_HASH1),
|
.CrcHash(CrcHash),
|
.CrcHash(CrcHash),
|
.CrcHashGood(CrcHashGood),
|
.CrcHashGood(CrcHashGood),
|
.StateData(StateData),
|
.StateData(StateData),
|
.Multicast(Multicast),
|
.Multicast(Multicast),
|
.MAC(MAC),
|
.MAC(MAC),
|
.RxAbort(RxAbort),
|
.RxAbort(RxAbort),
|
.RxEndFrm(RxEndFrm),
|
.RxEndFrm(RxEndFrm),
|
.AddressMiss(AddressMiss),
|
.AddressMiss(AddressMiss),
|
.PassAll(PassAll),
|
.PassAll(PassAll),
|
.ControlFrmAddressOK(ControlFrmAddressOK)
|
.ControlFrmAddressOK(ControlFrmAddressOK)
|
);
|
);
|
|
|
|
|
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
|
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
|
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
|
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
|
DlyCrcCnt[3:0] < 4'h9;
|
DlyCrcCnt[3:0] < 4'h9;
|
|
|
assign Data_Crc[0] = MRxD[3];
|
assign Data_Crc[0] = MRxD[3];
|
assign Data_Crc[1] = MRxD[2];
|
assign Data_Crc[1] = MRxD[2];
|
assign Data_Crc[2] = MRxD[1];
|
assign Data_Crc[2] = MRxD[1];
|
assign Data_Crc[3] = MRxD[0];
|
assign Data_Crc[3] = MRxD[0];
|
|
|
|
|
// Connecting module Crc
|
// Connecting module Crc
|
eth_crc crcrx
|
eth_crc crcrx
|
(.Clk(MRxClk),
|
(.Clk(MRxClk),
|
.Reset(Reset),
|
.Reset(Reset),
|
.Data(Data_Crc),
|
.Data(Data_Crc),
|
.Enable(Enable_Crc),
|
.Enable(Enable_Crc),
|
.Initialize(Initialize_Crc),
|
.Initialize(Initialize_Crc),
|
.Crc(Crc), .CrcError(CrcError)
|
.Crc(Crc), .CrcError(CrcError)
|
);
|
);
|
|
|
|
|
|
|
// Latching CRC for use in the hash table
|
// Latching CRC for use in the hash table
|
|
|
always @ (posedge MRxClk)
|
always @ (posedge MRxClk)
|
begin
|
begin
|
CrcHashGood <= StateData[0] & ByteCntEq6;
|
CrcHashGood <= StateData[0] & ByteCntEq6;
|
end
|
end
|
|
|
always @ (posedge MRxClk)
|
always @ (posedge MRxClk)
|
begin
|
begin
|
if(Reset | StateIdle)
|
if(Reset | StateIdle)
|
CrcHash[5:0] <= 6'h0;
|
CrcHash[5:0] <= 6'h0;
|
else
|
else
|
if(StateData[0] & ByteCntEq6)
|
if(StateData[0] & ByteCntEq6)
|
CrcHash[5:0] <= Crc[31:26];
|
CrcHash[5:0] <= Crc[31:26];
|
end
|
end
|
|
|
|
|
// Output byte stream
|
// Output byte stream
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
RxData_d[7:0] <= 8'h0;
|
RxData_d[7:0] <= 8'h0;
|
DelayData <= 1'b0;
|
DelayData <= 1'b0;
|
LatchedByte[7:0] <= 8'h0;
|
LatchedByte[7:0] <= 8'h0;
|
RxData[7:0] <= 8'h0;
|
RxData[7:0] <= 8'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Latched byte
|
// Latched byte
|
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
|
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
|
|
|
DelayData <= StateData[0];
|
DelayData <= StateData[0];
|
|
|
if(GenerateRxValid)
|
if(GenerateRxValid)
|
// Data goes through only in data state
|
// Data goes through only in data state
|
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}};
|
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}};
|
else
|
else
|
if(~DelayData)
|
if(~DelayData)
|
// Delaying data to be valid for two cycles.
|
// Delaying data to be valid for two cycles.
|
// Zero when not active.
|
// Zero when not active.
|
RxData_d[7:0] <= 8'h0;
|
RxData_d[7:0] <= 8'h0;
|
|
|
RxData[7:0] <= RxData_d[7:0]; // Output data byte
|
RxData[7:0] <= RxData_d[7:0]; // Output data byte
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
Broadcast <= 1'b0;
|
Broadcast <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
|
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
|
Broadcast <= 1'b0;
|
Broadcast <= 1'b0;
|
else
|
else
|
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
|
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
|
Broadcast <= 1'b1;
|
Broadcast <= 1'b1;
|
else
|
else
|
if(RxAbort | RxEndFrm)
|
if(RxAbort | RxEndFrm)
|
Broadcast <= 1'b0;
|
Broadcast <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
Multicast <= 1'b0;
|
Multicast <= 1'b0;
|
else
|
else
|
begin
|
begin
|
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
|
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
|
Multicast <= 1'b1;
|
Multicast <= 1'b1;
|
else if(RxAbort | RxEndFrm)
|
else if(RxAbort | RxEndFrm)
|
Multicast <= 1'b0;
|
Multicast <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
|
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
RxValid_d <= 1'b0;
|
RxValid_d <= 1'b0;
|
RxValid <= 1'b0;
|
RxValid <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxValid_d <= GenerateRxValid;
|
RxValid_d <= GenerateRxValid;
|
RxValid <= RxValid_d;
|
RxValid <= RxValid_d;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign GenerateRxStartFrm = StateData[0] &
|
assign GenerateRxStartFrm = StateData[0] &
|
((ByteCntEq1 & ~DlyCrcEn) |
|
((ByteCntEq1 & ~DlyCrcEn) |
|
((DlyCrcCnt == 4'h3) & DlyCrcEn));
|
((DlyCrcCnt == 4'h3) & DlyCrcEn));
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
RxStartFrm_d <= 1'b0;
|
RxStartFrm_d <= 1'b0;
|
RxStartFrm <= 1'b0;
|
RxStartFrm <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxStartFrm_d <= GenerateRxStartFrm;
|
RxStartFrm_d <= GenerateRxStartFrm;
|
RxStartFrm <= RxStartFrm_d;
|
RxStartFrm <= RxStartFrm_d;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign GenerateRxEndFrm = StateData[0] &
|
assign GenerateRxEndFrm = StateData[0] &
|
(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
|
(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
|
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
|
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
|
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
RxEndFrm_d <= 1'b0;
|
RxEndFrm_d <= 1'b0;
|
RxEndFrm <= 1'b0;
|
RxEndFrm <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxEndFrm_d <= GenerateRxEndFrm;
|
RxEndFrm_d <= GenerateRxEndFrm;
|
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
|
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
