//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth.v ////
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//// eth.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/project,ethmac ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is available in the Readme.txt ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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`include "ethmac_defines.v"
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`include "ethmac_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module ethmac // renamed jb
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module ethmac // renamed jb
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(
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(
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// WISHBONE common
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// WISHBONE common
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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// WISHBONE slave
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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// WISHBONE master
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// WISHBONE master
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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m_wb_cti_o, m_wb_bte_o,
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m_wb_cti_o, m_wb_bte_o,
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`endif
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`endif
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//TX
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//TX
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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//RX
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//RX
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i,
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mcrs_pad_i,
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// MIIM
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// MIIM
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mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
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mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
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int_o
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int_o
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// Bist
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// Bist
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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mbist_si_i, // bist scan serial in
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mbist_si_i, // bist scan serial in
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mbist_so_o, // bist scan serial out
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mbist_so_o, // bist scan serial out
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mbist_ctrl_i // bist chain shift control
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mbist_ctrl_i // bist chain shift control
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`endif
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`endif
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);
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);
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parameter Tp = 1;
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// WISHBONE common
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// WISHBONE common
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input wb_clk_i; // WISHBONE clock
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input wb_clk_i; // WISHBONE clock
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input wb_rst_i; // WISHBONE reset
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input wb_rst_i; // WISHBONE reset
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input [31:0] wb_dat_i; // WISHBONE data input
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input [31:0] wb_dat_i; // WISHBONE data input
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output [31:0] wb_dat_o; // WISHBONE data output
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output [31:0] wb_dat_o; // WISHBONE data output
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output wb_err_o; // WISHBONE error output
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output wb_err_o; // WISHBONE error output
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// WISHBONE slave
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// WISHBONE slave
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input [11:2] wb_adr_i; // WISHBONE address input
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input [11:2] wb_adr_i; // WISHBONE address input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input wb_we_i; // WISHBONE write enable input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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// WISHBONE master
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// WISHBONE master
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output [31:0] m_wb_adr_o;
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output [31:0] m_wb_adr_o;
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output [3:0] m_wb_sel_o;
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output [3:0] m_wb_sel_o;
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output m_wb_we_o;
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output m_wb_we_o;
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input [31:0] m_wb_dat_i;
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input [31:0] m_wb_dat_i;
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output [31:0] m_wb_dat_o;
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output [31:0] m_wb_dat_o;
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output m_wb_cyc_o;
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output m_wb_cyc_o;
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output m_wb_stb_o;
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output m_wb_stb_o;
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input m_wb_ack_i;
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input m_wb_ack_i;
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input m_wb_err_i;
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input m_wb_err_i;
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wire [29:0] m_wb_adr_tmp;
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wire [29:0] m_wb_adr_tmp;
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [2:0] m_wb_cti_o; // Cycle Type Identifier
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output [1:0] m_wb_bte_o; // Burst Type Extension
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output [1:0] m_wb_bte_o; // Burst Type Extension
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`endif
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`endif
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// Tx
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// Tx
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxerr_pad_o; // Transmit error (to PHY)
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output mtxerr_pad_o; // Transmit error (to PHY)
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// Rx
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// Rx
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input mrx_clk_pad_i; // Receive clock (from PHY)
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input mrx_clk_pad_i; // Receive clock (from PHY)
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input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
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input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
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input mrxdv_pad_i; // Receive data valid (from PHY)
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input mrxdv_pad_i; // Receive data valid (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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// Common Tx and Rx
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// Common Tx and Rx
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input mcoll_pad_i; // Collision (from PHY)
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input mcoll_pad_i; // Collision (from PHY)
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input mcrs_pad_i; // Carrier sense (from PHY)
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input mcrs_pad_i; // Carrier sense (from PHY)
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// MII Management interface
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// MII Management interface
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input md_pad_i; // MII data input (from I/O cell)
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input md_pad_i; // MII data input (from I/O cell)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output md_pad_o; // MII data output (to I/O cell)
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output md_pad_o; // MII data output (to I/O cell)
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output md_padoe_o; // MII data output enable (to I/O cell)
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output md_padoe_o; // MII data output enable (to I/O cell)
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output int_o; // Interrupt output
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output int_o; // Interrupt output
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// Bist
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// Bist
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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input mbist_si_i; // bist scan serial in
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input mbist_si_i; // bist scan serial in
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output mbist_so_o; // bist scan serial out
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output mbist_so_o; // bist scan serial out
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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`endif
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`endif
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`ifdef WISHBONE_DEBUG
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`ifdef WISHBONE_DEBUG
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wire [31:0] wb_dbg_dat0;
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wire [31:0] wb_dbg_dat0;
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`endif
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`endif
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wire [7:0] r_ClkDiv;
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wire [7:0] r_ClkDiv;
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wire r_MiiNoPre;
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wire r_MiiNoPre;
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wire [15:0] r_CtrlData;
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wire [15:0] r_CtrlData;
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wire [4:0] r_FIAD;
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wire [4:0] r_FIAD;
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wire [4:0] r_RGAD;
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wire [4:0] r_RGAD;
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wire r_WCtrlData;
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wire r_WCtrlData;
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wire r_RStat;
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wire r_RStat;
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wire r_ScanStat;
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wire r_ScanStat;
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wire NValid_stat;
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wire NValid_stat;
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wire Busy_stat;
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wire Busy_stat;
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wire LinkFail;
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wire LinkFail;
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wire [15:0] Prsd; // Read Status Data (data read from the PHY)
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wire [15:0] Prsd; // Read Status Data (data read
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// from the PHY)
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wire WCtrlDataStart;
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wire WCtrlDataStart;
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wire RStatStart;
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wire RStatStart;
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wire UpdateMIIRX_DATAReg;
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wire UpdateMIIRX_DATAReg;
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wire TxStartFrm;
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wire TxStartFrm;
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wire TxEndFrm;
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wire TxEndFrm;
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wire TxUsedData;
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wire TxUsedData;
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wire [7:0] TxData;
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wire [7:0] TxData;
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wire TxRetry;
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wire TxRetry;
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wire TxAbort;
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wire TxAbort;
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wire TxUnderRun;
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wire TxUnderRun;
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wire TxDone;
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wire TxDone;
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reg WillSendControlFrame_sync1;
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reg WillSendControlFrame_sync1;
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reg WillSendControlFrame_sync2;
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reg WillSendControlFrame_sync2;
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reg WillSendControlFrame_sync3;
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reg WillSendControlFrame_sync3;
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reg RstTxPauseRq;
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reg RstTxPauseRq;
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reg TxPauseRq_sync1;
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reg TxPauseRq_sync1;
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reg TxPauseRq_sync2;
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reg TxPauseRq_sync2;
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reg TxPauseRq_sync3;
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reg TxPauseRq_sync3;
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reg TPauseRq;
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reg TPauseRq;
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// Connecting Miim module
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// Connecting Miim module
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eth_miim miim1
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eth_miim miim1
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(
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(
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.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
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.Clk(wb_clk_i),
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.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
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.Reset(wb_rst_i),
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.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
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.Divider(r_ClkDiv),
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.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
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.NoPre(r_MiiNoPre),
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.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
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.CtrlData(r_CtrlData),
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.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
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.Rgad(r_RGAD),
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.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
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.Fiad(r_FIAD),
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.WCtrlData(r_WCtrlData),
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.RStat(r_RStat),
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.ScanStat(r_ScanStat),
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.Mdi(md_pad_i),
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.Mdo(md_pad_o),
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.MdoEn(md_padoe_o),
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.Mdc(mdc_pad_o),
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.Busy(Busy_stat),
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.Prsd(Prsd),
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.LinkFail(LinkFail),
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.Nvalid(NValid_stat),
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.WCtrlDataStart(WCtrlDataStart),
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.RStatStart(RStatStart),
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.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
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);
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);
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wire [3:0] RegCs; // Connected to registers
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wire [3:0] RegCs; // Connected to registers
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire r_RecSmall; // Receive small frames
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wire r_RecSmall; // Receive small frames
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wire r_LoopBck; // Loopback
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wire r_LoopBck; // Loopback
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wire r_TxEn; // Tx Enable
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wire r_TxEn; // Tx Enable
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wire r_RxEn; // Rx Enable
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wire r_RxEn; // Rx Enable
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wire MRxDV_Lb; // Muxed MII receive data valid
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wire MRxDV_Lb; // Muxed MII receive data valid
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wire MRxErr_Lb; // Muxed MII Receive Error
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wire MRxErr_Lb; // Muxed MII Receive Error
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wire [3:0] MRxD_Lb; // Muxed MII Receive Data
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wire [3:0] MRxD_Lb; // Muxed MII Receive Data
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wire Transmitting; // Indication that TxEthMAC is transmitting
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wire Transmitting; // Indication that TxEthMAC is transmitting
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wire r_HugEn; // Huge packet enable
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wire r_HugEn; // Huge packet enable
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wire r_DlyCrcEn; // Delayed CRC enabled
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wire r_DlyCrcEn; // Delayed CRC enabled
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wire [15:0] r_MaxFL; // Maximum frame length
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wire [15:0] r_MaxFL; // Maximum frame length
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wire [15:0] r_MinFL; // Minimum frame length
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wire [15:0] r_MinFL; // Minimum frame length
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wire ShortFrame;
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wire ShortFrame;
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wire DribbleNibble; // Extra nibble received
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wire DribbleNibble; // Extra nibble received
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wire ReceivedPacketTooBig; // Received packet is too big
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wire ReceivedPacketTooBig; // Received packet is too big
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wire [47:0] r_MAC; // MAC address
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wire [47:0] r_MAC; // MAC address
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wire LoadRxStatus; // Rx status was loaded
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wire LoadRxStatus; // Rx status was loaded
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wire [31:0] r_HASH0; // HASH table, lower 4 bytes
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wire [31:0] r_HASH0; // HASH table, lower 4 bytes
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wire [31:0] r_HASH1; // HASH table, upper 4 bytes
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wire [31:0] r_HASH1; // HASH table, upper 4 bytes
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wire [7:0] r_TxBDNum; // Receive buffer descriptor number
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wire [7:0] r_TxBDNum; // Receive buffer descriptor number
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wire [6:0] r_IPGT; //
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wire [6:0] r_IPGT; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR2; //
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wire [6:0] r_IPGR2; //
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wire [5:0] r_CollValid; //
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wire [5:0] r_CollValid; //
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wire [15:0] r_TxPauseTV; // Transmit PAUSE value
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wire [15:0] r_TxPauseTV; // Transmit PAUSE value
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wire r_TxPauseRq; // Transmit PAUSE request
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wire r_TxPauseRq; // Transmit PAUSE request
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|
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wire [3:0] r_MaxRet; //
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wire [3:0] r_MaxRet; //
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wire r_NoBckof; //
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wire r_NoBckof; //
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wire r_ExDfrEn; //
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wire r_ExDfrEn; //
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wire r_TxFlow; // Tx flow control enable
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wire r_TxFlow; // Tx flow control enable
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire r_IFG; // Minimum interframe gap for incoming packets
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|
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxE_IRQ; // Interrupt Tx Error
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wire TxE_IRQ; // Interrupt Tx Error
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxE_IRQ; // Interrupt Rx Error
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wire RxE_IRQ; // Interrupt Rx Error
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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|
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//wire DWord;
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//wire DWord;
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wire ByteSelected;
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wire ByteSelected;
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wire BDAck;
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wire BDAck;
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
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wire [3:0] BDCs; // Buffer descriptor CS
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wire [3:0] BDCs; // Buffer descriptor CS
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
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// but data is not valid.
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// but data is not valid.
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wire r_Pad;
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wire r_Pad;
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wire r_CrcEn;
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wire r_CrcEn;
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wire r_FullD;
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wire r_FullD;
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wire r_Pro;
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wire r_Pro;
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wire r_Bro;
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wire r_Bro;
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wire r_NoPre;
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wire r_NoPre;
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wire r_RxFlow;
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wire r_RxFlow;
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wire r_PassAll;
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wire r_PassAll;
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wire TxCtrlEndFrm;
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wire TxCtrlEndFrm;
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wire StartTxDone;
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wire StartTxDone;
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wire SetPauseTimer;
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wire SetPauseTimer;
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wire TxUsedDataIn;
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wire TxUsedDataIn;
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wire TxDoneIn;
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wire TxDoneIn;
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wire TxAbortIn;
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wire TxAbortIn;
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wire PerPacketPad;
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wire PerPacketPad;
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wire PadOut;
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wire PadOut;
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wire PerPacketCrcEn;
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wire PerPacketCrcEn;
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wire CrcEnOut;
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wire CrcEnOut;
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wire TxStartFrmOut;
|
wire TxStartFrmOut;
|
wire TxEndFrmOut;
|
wire TxEndFrmOut;
|
wire ReceivedPauseFrm;
|
wire ReceivedPauseFrm;
|
wire ControlFrmAddressOK;
|
wire ControlFrmAddressOK;
|
wire RxStatusWriteLatched_sync2;
|
wire RxStatusWriteLatched_sync2;
|
wire LateCollision;
|
wire LateCollision;
|
wire DeferIndication;
|
wire DeferIndication;
|
wire LateCollLatched;
|
wire LateCollLatched;
|
wire DeferLatched;
|
wire DeferLatched;
|
wire RstDeferLatched;
|
wire RstDeferLatched;
|
wire CarrierSenseLost;
|
wire CarrierSenseLost;
|
|
|
wire temp_wb_ack_o;
|
wire temp_wb_ack_o;
|
wire [31:0] temp_wb_dat_o;
|
wire [31:0] temp_wb_dat_o;
|
wire temp_wb_err_o;
|
wire temp_wb_err_o;
|
|
|
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
reg temp_wb_ack_o_reg;
|
reg temp_wb_ack_o_reg;
|
reg [31:0] temp_wb_dat_o_reg;
|
reg [31:0] temp_wb_dat_o_reg;
|
reg temp_wb_err_o_reg;
|
reg temp_wb_err_o_reg;
|
`endif
|
`endif
|
|
|
//assign DWord = &wb_sel_i;
|
//assign DWord = &wb_sel_i;
|
assign ByteSelected = |wb_sel_i;
|
assign ByteSelected = |wb_sel_i;
|
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
|
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
|
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
|
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
|
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
|
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
|
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
|
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
|
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
|
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
|
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
|
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
|
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
|
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
|
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
|
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
|
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
|
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
|
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
|
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
|
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
|
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
|
|
|
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
assign wb_ack_o = temp_wb_ack_o_reg;
|
assign wb_ack_o = temp_wb_ack_o_reg;
|
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
|
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
|
assign wb_err_o = temp_wb_err_o_reg;
|
assign wb_err_o = temp_wb_err_o_reg;
|
`else
|
`else
|
assign wb_ack_o = temp_wb_ack_o;
|
assign wb_ack_o = temp_wb_ack_o;
|
assign wb_dat_o[31:0] = temp_wb_dat_o;
|
assign wb_dat_o[31:0] = temp_wb_dat_o;
|
assign wb_err_o = temp_wb_err_o;
|
assign wb_err_o = temp_wb_err_o;
|
`endif
|
`endif
|
|
|
`ifdef ETH_AVALON_BUS
|
`ifdef ETH_AVALON_BUS
|
// As Avalon has no corresponding "error" signal, I (erroneously) will
|
// As Avalon has no corresponding "error" signal, I (erroneously) will
|
// send an ack to Avalon, even when accessing undefined memory. This
|
// send an ack to Avalon, even when accessing undefined memory. This
|
// is a grey area in Avalon vs. Wishbone specs: My understanding
|
// is a grey area in Avalon vs. Wishbone specs: My understanding
|
// is that Avalon expects all memory addressable by the addr bus feeding
|
// is that Avalon expects all memory addressable by the addr bus feeding
|
// a slave to be, at the very minimum, readable.
|
// a slave to be, at the very minimum, readable.
|
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
|
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
|
`else // WISHBONE
|
`else // WISHBONE
|
assign temp_wb_ack_o = (|RegCs) | BDAck;
|
assign temp_wb_ack_o = (|RegCs) | BDAck;
|
`endif
|
`endif
|
|
|
`ifdef ETH_REGISTERED_OUTPUTS
|
`ifdef ETH_REGISTERED_OUTPUTS
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
temp_wb_ack_o_reg <= 1'b0;
|
temp_wb_ack_o_reg <= 1'b0;
|
temp_wb_dat_o_reg <= 32'h0;
|
temp_wb_dat_o_reg <= 32'h0;
|
temp_wb_err_o_reg <= 1'b0;
|
temp_wb_err_o_reg <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
|
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
|
temp_wb_dat_o_reg <= temp_wb_dat_o;
|
temp_wb_dat_o_reg <= temp_wb_dat_o;
|
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
|
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
|
|
|
|
// Connecting Ethernet registers
|
// Connecting Ethernet registers
|
eth_registers ethreg1
|
eth_registers ethreg1
|
(
|
(
|
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
|
.DataIn(wb_dat_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.Address(wb_adr_i[9:2]),
|
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
|
.Rw(wb_we_i),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
|
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
|
.Cs(RegCs),
|
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.Clk(wb_clk_i),
|
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
|
.Reset(wb_rst_i),
|
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
|
.DataOut(RegDataOut),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.r_RecSmall(r_RecSmall),
|
|
|
|
.r_Pad(r_Pad),
|
|
.r_HugEn(r_HugEn),
|
|
.r_CrcEn(r_CrcEn),
|
|
|
|
.r_DlyCrcEn(r_DlyCrcEn),
|
|
.r_FullD(r_FullD),
|
|
|
|
.r_ExDfrEn(r_ExDfrEn),
|
|
.r_NoBckof(r_NoBckof),
|
|
.r_LoopBck(r_LoopBck),
|
|
|
|
.r_IFG(r_IFG),
|
|
.r_Pro(r_Pro),
|
|
.r_Iam(),
|
|
|
|
.r_Bro(r_Bro),
|
|
.r_NoPre(r_NoPre),
|
|
.r_TxEn(r_TxEn),
|
|
|
|
.r_RxEn(r_RxEn),
|
|
.Busy_IRQ(Busy_IRQ),
|
|
.RxE_IRQ(RxE_IRQ),
|
|
|
|
.RxB_IRQ(RxB_IRQ),
|
|
.TxE_IRQ(TxE_IRQ),
|
|
.TxB_IRQ(TxB_IRQ),
|
|
|
.r_IPGT(r_IPGT),
|
.r_IPGT(r_IPGT),
|
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
|
|
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
|
.r_IPGR1(r_IPGR1),
|
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
|
.r_IPGR2(r_IPGR2),
|
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
|
.r_MinFL(r_MinFL),
|
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
|
|
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
|
.r_MaxFL(r_MaxFL),
|
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
|
.r_MaxRet(r_MaxRet),
|
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
|
.r_CollValid(r_CollValid),
|
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
|
|
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
|
.r_TxFlow(r_TxFlow),
|
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
|
.r_RxFlow(r_RxFlow),
|
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
|
.r_PassAll(r_PassAll),
|
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
|
|
|
.r_MiiNoPre(r_MiiNoPre),
|
|
.r_ClkDiv(r_ClkDiv),
|
|
|
|
.r_WCtrlData(r_WCtrlData),
|
|
.r_RStat(r_RStat),
|
|
.r_ScanStat(r_ScanStat),
|
|
|
|
.r_RGAD(r_RGAD),
|
|
.r_FIAD(r_FIAD),
|
|
.r_CtrlData(r_CtrlData),
|
|
|
|
.NValid_stat(NValid_stat),
|
|
.Busy_stat(Busy_stat),
|
|
|
|
.LinkFail(LinkFail),
|
|
.r_MAC(r_MAC),
|
|
.WCtrlDataStart(WCtrlDataStart),
|
|
|
|
.RStatStart(RStatStart),
|
|
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
|
|
.Prsd(Prsd),
|
|
|
|
.r_TxBDNum(r_TxBDNum),
|
|
.int_o(int_o),
|
|
|
|
.r_HASH0(r_HASH0),
|
|
.r_HASH1(r_HASH1),
|
|
.r_TxPauseRq(r_TxPauseRq),
|
|
|
|
.r_TxPauseTV(r_TxPauseTV),
|
|
.RstTxPauseRq(RstTxPauseRq),
|
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
|
|
|
.StartTxDone(StartTxDone),
|
|
.TxClk(mtx_clk_pad_i),
|
|
.RxClk(mrx_clk_pad_i),
|
|
|
.dbg_dat(wb_dbg_dat0),
|
.dbg_dat(wb_dbg_dat0),
|
|
|
.SetPauseTimer(SetPauseTimer)
|
.SetPauseTimer(SetPauseTimer)
|
|
|
);
|
);
|
|
|
|
|
|
|
wire [7:0] RxData;
|
wire [7:0] RxData;
|
wire RxValid;
|
wire RxValid;
|
wire RxStartFrm;
|
wire RxStartFrm;
|
wire RxEndFrm;
|
wire RxEndFrm;
|
wire RxAbort;
|
wire RxAbort;
|
|
|
wire WillTransmit; // Will transmit (to RxEthMAC)
|
wire WillTransmit; // Will transmit (to RxEthMAC)
|
wire ResetCollision; // Reset Collision (for synchronizing collision)
|
wire ResetCollision; // Reset Collision (for synchronizing
|
|
// collision)
|
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
|
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
|
wire WillSendControlFrame;
|
wire WillSendControlFrame;
|
wire ReceiveEnd;
|
wire ReceiveEnd;
|
wire ReceivedPacketGood;
|
wire ReceivedPacketGood;
|
wire ReceivedLengthOK;
|
wire ReceivedLengthOK;
|
wire InvalidSymbol;
|
wire InvalidSymbol;
|
wire LatchedCrcError;
|
wire LatchedCrcError;
|
wire RxLateCollision;
|
wire RxLateCollision;
|
wire [3:0] RetryCntLatched;
|
wire [3:0] RetryCntLatched;
|
wire [3:0] RetryCnt;
|
wire [3:0] RetryCnt;
|
wire StartTxAbort;
|
wire StartTxAbort;
|
wire MaxCollisionOccured;
|
wire MaxCollisionOccured;
|
wire RetryLimit;
|
wire RetryLimit;
|
wire StatePreamble;
|
wire StatePreamble;
|
wire [1:0] StateData;
|
wire [1:0] StateData;
|
|
|
// Connecting MACControl
|
// Connecting MACControl
|
eth_maccontrol maccontrol1
|
eth_maccontrol maccontrol1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.MTxClk(mtx_clk_pad_i),
|
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
|
.TPauseRq(TPauseRq),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxPauseTV(r_TxPauseTV),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
|
.TxDataIn(TxData),
|
.RxData(RxData), .RxValid(RxValid),
|
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.TxStartFrmIn(TxStartFrm),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
|
.TxEndFrmIn(TxEndFrm),
|
|
|
|
.TxUsedDataIn(TxUsedDataIn),
|
|
.TxDoneIn(TxDoneIn),
|
|
|
|
.TxAbortIn(TxAbortIn),
|
|
.MRxClk(mrx_clk_pad_i),
|
|
|
|
.RxData(RxData),
|
|
.RxValid(RxValid),
|
|
|
|
.RxStartFrm(RxStartFrm),
|
|
.RxEndFrm(RxEndFrm),
|
|
|
|
.ReceiveEnd(ReceiveEnd),
|
|
.ReceivedPacketGood(ReceivedPacketGood),
|
|
|
.TxFlow(r_TxFlow),
|
.TxFlow(r_TxFlow),
|
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
|
|
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
|
.RxFlow(r_RxFlow),
|
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
|
.DlyCrcEn(r_DlyCrcEn),
|
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
|
|
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
|
.MAC(r_MAC),
|
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
|
.PadIn(r_Pad | PerPacketPad),
|
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
|
|
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
|
.PadOut(PadOut),
|
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
|
.CrcEnIn(r_CrcEn | PerPacketCrcEn),
|
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
|
|
|
.CrcEnOut(CrcEnOut),
|
|
.TxReset(wb_rst_i),
|
|
|
|
.RxReset(wb_rst_i),
|
|
.ReceivedLengthOK(ReceivedLengthOK),
|
|
|
|
.TxDataOut(TxDataOut),
|
|
.TxStartFrmOut(TxStartFrmOut),
|
|
|
|
.TxEndFrmOut(TxEndFrmOut),
|
|
.TxUsedDataOut(TxUsedData),
|
|
|
|
.TxDoneOut(TxDone),
|
|
.TxAbortOut(TxAbort),
|
|
|
|
.WillSendControlFrame(WillSendControlFrame),
|
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
|
|
|
.ReceivedPauseFrm(ReceivedPauseFrm),
|
|
.ControlFrmAddressOK(ControlFrmAddressOK),
|
|
|
.SetPauseTimer(SetPauseTimer),
|
.SetPauseTimer(SetPauseTimer),
|
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
|
|
|
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
|
|
.r_PassAll(r_PassAll)
|
);
|
);
|
|
|
|
|
|
|
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
|
wire TxCarrierSense; // Synchronized CarrierSense (to Tx
|
|
// clock)
|
wire Collision; // Synchronized Collision
|
wire Collision; // Synchronized Collision
|
|
|
reg CarrierSense_Tx1;
|
reg CarrierSense_Tx1;
|
reg CarrierSense_Tx2;
|
reg CarrierSense_Tx2;
|
reg Collision_Tx1;
|
reg Collision_Tx1;
|
reg Collision_Tx2;
|
reg Collision_Tx2;
|
|
|
reg RxEnSync; // Synchronized Receive Enable
|
reg RxEnSync; // Synchronized Receive Enable
|
reg WillTransmit_q;
|
reg WillTransmit_q;
|
reg WillTransmit_q2;
|
reg WillTransmit_q2;
|
|
|
|
|
|
|
// Muxed MII receive data valid
|
// Muxed MII receive data valid
|
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
|
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
|
|
|
// Muxed MII Receive Error
|
// Muxed MII Receive Error
|
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
|
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
|
|
|
// Muxed MII Receive Data
|
// Muxed MII Receive Data
|
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
|
|
|
|
|
|
// Connecting TxEthMAC
|
// Connecting TxEthMAC
|
eth_txethmac txethmac1
|
eth_txethmac txethmac1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
|
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.MTxClk(mtx_clk_pad_i),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.Reset(wb_rst_i),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.CarrierSense(TxCarrierSense),
|
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
|
|
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
|
.Collision(Collision),
|
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
|
.TxData(TxDataOut),
|
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
|
.TxStartFrm(TxStartFrmOut),
|
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
|
|
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
|
.TxUnderRun(TxUnderRun),
|
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
|
.TxEndFrm(TxEndFrmOut),
|
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
|
.Pad(PadOut),
|
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
|
|
|
.MinFL(r_MinFL),
|
|
.CrcEn(CrcEnOut),
|
|
.FullD(r_FullD),
|
|
|
|
.HugEn(r_HugEn),
|
|
.DlyCrcEn(r_DlyCrcEn),
|
|
.IPGT(r_IPGT),
|
|
|
|
.IPGR1(r_IPGR1),
|
|
.IPGR2(r_IPGR2),
|
|
.CollValid(r_CollValid),
|
|
|
|
.MaxRet(r_MaxRet),
|
|
.NoBckof(r_NoBckof),
|
|
.ExDfrEn(r_ExDfrEn),
|
|
|
|
.MaxFL(r_MaxFL),
|
|
.MTxEn(mtxen_pad_o),
|
|
.MTxD(mtxd_pad_o),
|
|
|
|
.MTxErr(mtxerr_pad_o),
|
|
.TxUsedData(TxUsedDataIn),
|
|
.TxDone(TxDoneIn),
|
|
|
|
.TxRetry(TxRetry),
|
|
.TxAbort(TxAbortIn),
|
|
.WillTransmit(WillTransmit),
|
|
|
|
.ResetCollision(ResetCollision),
|
|
.RetryCnt(RetryCnt),
|
|
.StartTxDone(StartTxDone),
|
|
|
|
.StartTxAbort(StartTxAbort),
|
|
.MaxCollisionOccured(MaxCollisionOccured),
|
|
.LateCollision(LateCollision),
|
|
|
|
.DeferIndication(DeferIndication),
|
|
.StatePreamble(StatePreamble),
|
|
.StateData(StateData)
|
);
|
);
|
|
|
|
|
|
|
|
|
wire [15:0] RxByteCnt;
|
wire [15:0] RxByteCnt;
|
wire RxByteCntEq0;
|
wire RxByteCntEq0;
|
wire RxByteCntGreat2;
|
wire RxByteCntGreat2;
|
wire RxByteCntMaxFrame;
|
wire RxByteCntMaxFrame;
|
wire RxCrcError;
|
wire RxCrcError;
|
wire RxStateIdle;
|
wire RxStateIdle;
|
wire RxStatePreamble;
|
wire RxStatePreamble;
|
wire RxStateSFD;
|
wire RxStateSFD;
|
wire [1:0] RxStateData;
|
wire [1:0] RxStateData;
|
wire AddressMiss;
|
wire AddressMiss;
|
|
|
|
|
|
|
// Connecting RxEthMAC
|
// Connecting RxEthMAC
|
eth_rxethmac rxethmac1
|
eth_rxethmac rxethmac1
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.MRxClk(mrx_clk_pad_i),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
|
.MRxDV(MRxDV_Lb),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.MRxD(MRxD_Lb),
|
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
|
|
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
|
.Transmitting(Transmitting),
|
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
|
.HugEn(r_HugEn),
|
.StateSFD(RxStateSFD), .StateData(RxStateData),
|
.DlyCrcEn(r_DlyCrcEn),
|
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
|
|
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
|
.MaxFL(r_MaxFL),
|
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
|
.r_IFG(r_IFG),
|
|
.Reset(wb_rst_i),
|
|
|
|
.RxData(RxData),
|
|
.RxValid(RxValid),
|
|
.RxStartFrm(RxStartFrm),
|
|
|
|
.RxEndFrm(RxEndFrm),
|
|
.ByteCnt(RxByteCnt),
|
|
|
|
.ByteCntEq0(RxByteCntEq0),
|
|
.ByteCntGreat2(RxByteCntGreat2),
|
|
.ByteCntMaxFrame(RxByteCntMaxFrame),
|
|
|
|
.CrcError(RxCrcError),
|
|
.StateIdle(RxStateIdle),
|
|
.StatePreamble(RxStatePreamble),
|
|
|
|
.StateSFD(RxStateSFD),
|
|
.StateData(RxStateData),
|
|
|
|
.MAC(r_MAC),
|
|
.r_Pro(r_Pro),
|
|
.r_Bro(r_Bro),
|
|
|
|
.r_HASH0(r_HASH0),
|
|
.r_HASH1(r_HASH1),
|
|
.RxAbort(RxAbort),
|
|
|
|
.AddressMiss(AddressMiss),
|
|
.PassAll(r_PassAll),
|
|
.ControlFrmAddressOK(ControlFrmAddressOK)
|
);
|
);
|
|
|
|
|
// MII Carrier Sense Synchronization
|
// MII Carrier Sense Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
CarrierSense_Tx1 <= 1'b0;
|
CarrierSense_Tx1 <= 1'b0;
|
CarrierSense_Tx2 <= 1'b0;
|
CarrierSense_Tx2 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
CarrierSense_Tx1 <= mcrs_pad_i;
|
CarrierSense_Tx1 <= mcrs_pad_i;
|
CarrierSense_Tx2 <= CarrierSense_Tx1;
|
CarrierSense_Tx2 <= CarrierSense_Tx1;
|
end
|
end
|
end
|
end
|
|
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
|
|
|
|
// MII Collision Synchronization
|
// MII Collision Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
Collision_Tx1 <= 1'b0;
|
Collision_Tx1 <= 1'b0;
|
Collision_Tx2 <= 1'b0;
|
Collision_Tx2 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Collision_Tx1 <= mcoll_pad_i;
|
Collision_Tx1 <= mcoll_pad_i;
|
if(ResetCollision)
|
if(ResetCollision)
|
Collision_Tx2 <= 1'b0;
|
Collision_Tx2 <= 1'b0;
|
else
|
else
|
if(Collision_Tx1)
|
if(Collision_Tx1)
|
Collision_Tx2 <= 1'b1;
|
Collision_Tx2 <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Synchronized Collision
|
// Synchronized Collision
|
assign Collision = ~r_FullD & Collision_Tx2;
|
assign Collision = ~r_FullD & Collision_Tx2;
|
|
|
|
|
|
|
// Delayed WillTransmit
|
// Delayed WillTransmit
|
always @ (posedge mrx_clk_pad_i)
|
always @ (posedge mrx_clk_pad_i)
|
begin
|
begin
|
WillTransmit_q <= WillTransmit;
|
WillTransmit_q <= WillTransmit;
|
WillTransmit_q2 <= WillTransmit_q;
|
WillTransmit_q2 <= WillTransmit_q;
|
end
|
end
|
|
|
|
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
|
|
|
|
|
|
// Synchronized Receive Enable
|
// Synchronized Receive Enable
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RxEnSync <= 1'b0;
|
RxEnSync <= 1'b0;
|
else
|
else
|
if(~mrxdv_pad_i)
|
if(~mrxdv_pad_i)
|
RxEnSync <= r_RxEn;
|
RxEnSync <= r_RxEn;
|
end
|
end
|
|
|
|
|
|
|
// Synchronizing WillSendControlFrame to WB_CLK;
|
// Synchronizing WillSendControlFrame to WB_CLK;
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WillSendControlFrame_sync1 <= 1'b0;
|
WillSendControlFrame_sync1 <= 1'b0;
|
else
|
else
|
WillSendControlFrame_sync1 <= WillSendControlFrame;
|
WillSendControlFrame_sync1 <= WillSendControlFrame;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WillSendControlFrame_sync2 <= 1'b0;
|
WillSendControlFrame_sync2 <= 1'b0;
|
else
|
else
|
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
|
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
WillSendControlFrame_sync3 <= 1'b0;
|
WillSendControlFrame_sync3 <= 1'b0;
|
else
|
else
|
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
|
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RstTxPauseRq <= 1'b0;
|
RstTxPauseRq <= 1'b0;
|
else
|
else
|
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
|
RstTxPauseRq <= WillSendControlFrame_sync2 &
|
|
~WillSendControlFrame_sync3;
|
end
|
end
|
|
|
|
|
|
|
|
|
// TX Pause request Synchronization
|
// TX Pause request Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
TxPauseRq_sync1 <= 1'b0;
|
TxPauseRq_sync1 <= 1'b0;
|
TxPauseRq_sync2 <= 1'b0;
|
TxPauseRq_sync2 <= 1'b0;
|
TxPauseRq_sync3 <= 1'b0;
|
TxPauseRq_sync3 <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
|
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
|
TxPauseRq_sync2 <= TxPauseRq_sync1;
|
TxPauseRq_sync2 <= TxPauseRq_sync1;
|
TxPauseRq_sync3 <= TxPauseRq_sync2;
|
TxPauseRq_sync3 <= TxPauseRq_sync2;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
TPauseRq <= 1'b0;
|
TPauseRq <= 1'b0;
|
else
|
else
|
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
|
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
|
end
|
end
|
|
|
|
|
wire LatchedMRxErr;
|
wire LatchedMRxErr;
|
reg RxAbort_latch;
|
reg RxAbort_latch;
|
reg RxAbort_sync1;
|
reg RxAbort_sync1;
|
reg RxAbort_wb;
|
reg RxAbort_wb;
|
reg RxAbortRst_sync1;
|
reg RxAbortRst_sync1;
|
reg RxAbortRst;
|
reg RxAbortRst;
|
|
|
// Synchronizing RxAbort to the WISHBONE clock
|
// Synchronizing RxAbort to the WISHBONE clock
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
RxAbort_latch <= 1'b0;
|
RxAbort_latch <= 1'b0;
|
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
|
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
|
|
~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
|
RxAbort_latch <= 1'b1;
|
RxAbort_latch <= 1'b1;
|
else if(RxAbortRst)
|
else if(RxAbortRst)
|
RxAbort_latch <= 1'b0;
|
RxAbort_latch <= 1'b0;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
RxAbort_sync1 <= 1'b0;
|
RxAbort_sync1 <= 1'b0;
|
RxAbort_wb <= 1'b0;
|
RxAbort_wb <= 1'b0;
|
RxAbort_wb <= 1'b0;
|
RxAbort_wb <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxAbort_sync1 <= RxAbort_latch;
|
RxAbort_sync1 <= RxAbort_latch;
|
RxAbort_wb <= RxAbort_sync1;
|
RxAbort_wb <= RxAbort_sync1;
|
end
|
end
|
end
|
end
|
|
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
begin
|
begin
|
RxAbortRst_sync1 <= 1'b0;
|
RxAbortRst_sync1 <= 1'b0;
|
RxAbortRst <= 1'b0;
|
RxAbortRst <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
RxAbortRst_sync1 <= RxAbort_wb;
|
RxAbortRst_sync1 <= RxAbort_wb;
|
RxAbortRst <= RxAbortRst_sync1;
|
RxAbortRst <= RxAbortRst_sync1;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
// Connecting Wishbone module
|
// Connecting Wishbone module
|
eth_wishbone wishbone
|
eth_wishbone wishbone
|
(
|
(
|
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
|
|
|
.WB_CLK_I(wb_clk_i),
|
|
.WB_DAT_I(wb_dat_i),
|
|
|
.WB_DAT_O(BD_WB_DAT_O),
|
.WB_DAT_O(BD_WB_DAT_O),
|
|
|
// WISHBONE slave
|
// WISHBONE slave
|
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
|
|
.BDCs(BDCs), .WB_ACK_O(BDAck),
|
.WB_ADR_I(wb_adr_i[9:2]),
|
|
.WB_WE_I(wb_we_i),
|
|
|
|
.BDCs(BDCs),
|
|
.WB_ACK_O(BDAck),
|
|
|
|
|
.Reset(wb_rst_i),
|
.Reset(wb_rst_i),
|
|
|
// WISHBONE master
|
// WISHBONE master
|
.m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
|
|
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
|
.m_wb_adr_o(m_wb_adr_tmp),
|
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
|
.m_wb_sel_o(m_wb_sel_o),
|
|
.m_wb_we_o(m_wb_we_o),
|
|
|
|
.m_wb_dat_i(m_wb_dat_i),
|
|
.m_wb_dat_o(m_wb_dat_o),
|
|
.m_wb_cyc_o(m_wb_cyc_o),
|
|
|
|
.m_wb_stb_o(m_wb_stb_o),
|
|
.m_wb_ack_i(m_wb_ack_i),
|
|
.m_wb_err_i(m_wb_err_i),
|
|
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
|
|
|
.m_wb_cti_o(m_wb_cti_o),
|
|
.m_wb_bte_o(m_wb_bte_o),
|
`endif
|
`endif
|
|
|
|
|
//TX
|
//TX
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
|
.TxUsedData(TxUsedData), .TxData(TxData),
|
.MTxClk(mtx_clk_pad_i),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxStartFrm(TxStartFrm),
|
|
.TxEndFrm(TxEndFrm),
|
|
|
|
.TxUsedData(TxUsedData),
|
|
.TxData(TxData),
|
|
|
|
.TxRetry(TxRetry),
|
|
.TxAbort(TxAbort),
|
|
.TxUnderRun(TxUnderRun),
|
|
|
.TxDone(TxDone),
|
.TxDone(TxDone),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
|
|
|
.PerPacketCrcEn(PerPacketCrcEn),
|
|
.PerPacketPad(PerPacketPad),
|
|
|
// Register
|
// Register
|
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
|
|
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
|
.r_TxEn(r_TxEn),
|
|
.r_RxEn(r_RxEn),
|
|
.r_TxBDNum(r_TxBDNum),
|
|
|
|
.r_RxFlow(r_RxFlow),
|
|
.r_PassAll(r_PassAll),
|
|
|
//RX
|
//RX
|
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
|
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.MRxClk(mrx_clk_pad_i),
|
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
|
.RxData(RxData),
|
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.RxValid(RxValid),
|
|
|
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
|
.RxStartFrm(RxStartFrm),
|
|
.RxEndFrm(RxEndFrm),
|
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
|
|
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
|
.Busy_IRQ(Busy_IRQ),
|
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
|
.RxE_IRQ(RxE_IRQ),
|
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
|
.RxB_IRQ(RxB_IRQ),
|
|
|
|
.TxE_IRQ(TxE_IRQ),
|
|
.TxB_IRQ(TxB_IRQ),
|
|
|
|
|
|
.RxAbort(RxAbort_wb),
|
|
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
|
|
|
|
|
|
.InvalidSymbol(InvalidSymbol),
|
|
.LatchedCrcError(LatchedCrcError),
|
|
.RxLength(RxByteCnt),
|
|
|
|
.RxLateCollision(RxLateCollision),
|
|
.ShortFrame(ShortFrame),
|
|
.DribbleNibble(DribbleNibble),
|
|
|
|
.ReceivedPacketTooBig(ReceivedPacketTooBig),
|
|
.LoadRxStatus(LoadRxStatus),
|
|
.RetryCntLatched(RetryCntLatched),
|
|
|
|
.RetryLimit(RetryLimit),
|
|
.LateCollLatched(LateCollLatched),
|
|
.DeferLatched(DeferLatched),
|
|
|
.RstDeferLatched(RstDeferLatched),
|
.RstDeferLatched(RstDeferLatched),
|
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
|
|
|
.CarrierSenseLost(CarrierSenseLost),
|
|
.ReceivedPacketGood(ReceivedPacketGood),
|
|
.AddressMiss(AddressMiss),
|
|
|
.ReceivedPauseFrm(ReceivedPauseFrm)
|
.ReceivedPauseFrm(ReceivedPauseFrm)
|
|
|
`ifdef ETH_BIST
|
`ifdef ETH_BIST
|
,
|
,
|
|
|
.mbist_si_i (mbist_si_i),
|
.mbist_si_i (mbist_si_i),
|
|
|
.mbist_so_o (mbist_so_o),
|
.mbist_so_o (mbist_so_o),
|
|
|
.mbist_ctrl_i (mbist_ctrl_i)
|
.mbist_ctrl_i (mbist_ctrl_i)
|
`endif
|
`endif
|
`ifdef WISHBONE_DEBUG
|
`ifdef WISHBONE_DEBUG
|
,
|
,
|
|
|
.dbg_dat0(wb_dbg_dat0)
|
.dbg_dat0(wb_dbg_dat0)
|
`endif
|
`endif
|
|
|
);
|
);
|
|
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
|
|
|
// Connecting MacStatus module
|
// Connecting MacStatus module
|
eth_macstatus macstatus1
|
eth_macstatus macstatus1
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
|
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.MRxClk(mrx_clk_pad_i),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.Reset(wb_rst_i),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
|
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
|
.ReceiveEnd(ReceiveEnd),
|
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
|
.ReceivedPacketGood(ReceivedPacketGood),
|
|
.ReceivedLengthOK(ReceivedLengthOK),
|
|
|
|
.RxCrcError(RxCrcError),
|
|
.MRxErr(MRxErr_Lb),
|
|
.MRxDV(MRxDV_Lb),
|
|
|
|
.RxStateSFD(RxStateSFD),
|
|
.RxStateData(RxStateData),
|
|
.RxStatePreamble(RxStatePreamble),
|
|
|
|
.RxStateIdle(RxStateIdle),
|
|
.Transmitting(Transmitting),
|
|
.RxByteCnt(RxByteCnt),
|
|
|
|
.RxByteCntEq0(RxByteCntEq0),
|
|
.RxByteCntGreat2(RxByteCntGreat2),
|
|
.RxByteCntMaxFrame(RxByteCntMaxFrame),
|
|
|
.InvalidSymbol(InvalidSymbol),
|
.InvalidSymbol(InvalidSymbol),
|
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
|
|
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
|
.MRxD(MRxD_Lb),
|
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
|
.LatchedCrcError(LatchedCrcError),
|
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
|
.Collision(mcoll_pad_i),
|
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
|
|
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
|
.CollValid(r_CollValid),
|
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
|
.RxLateCollision(RxLateCollision),
|
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
|
.r_RecSmall(r_RecSmall),
|
|
|
|
.r_MinFL(r_MinFL),
|
|
.r_MaxFL(r_MaxFL),
|
|
.ShortFrame(ShortFrame),
|
|
|
|
.DribbleNibble(DribbleNibble),
|
|
.ReceivedPacketTooBig(ReceivedPacketTooBig),
|
|
.r_HugEn(r_HugEn),
|
|
|
|
.LoadRxStatus(LoadRxStatus),
|
|
.RetryCnt(RetryCnt),
|
|
.StartTxDone(StartTxDone),
|
|
|
|
.StartTxAbort(StartTxAbort),
|
|
.RetryCntLatched(RetryCntLatched),
|
|
.MTxClk(mtx_clk_pad_i),
|
|
|
|
.MaxCollisionOccured(MaxCollisionOccured),
|
|
.RetryLimit(RetryLimit),
|
|
.LateCollision(LateCollision),
|
|
|
|
.LateCollLatched(LateCollLatched),
|
|
.DeferIndication(DeferIndication),
|
|
.DeferLatched(DeferLatched),
|
|
|
.RstDeferLatched(RstDeferLatched),
|
.RstDeferLatched(RstDeferLatched),
|
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
|
|
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
|
.TxStartFrm(TxStartFrmOut),
|
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
|
.StatePreamble(StatePreamble),
|
|
.StateData(StateData),
|
|
|
|
.CarrierSense(CarrierSense_Tx2),
|
|
.CarrierSenseLost(CarrierSenseLost),
|
|
.TxUsedData(TxUsedDataIn),
|
|
|
|
.LatchedMRxErr(LatchedMRxErr),
|
|
.Loopback(r_LoopBck),
|
|
.r_FullD(r_FullD)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
