//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's DC FSM ////
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//// OR1200's DC FSM ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Data cache state machine ////
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//// Data cache state machine ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - Test error during line read or write ////
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//// - Test error during line read or write ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Julius Baxter, julius@opencores.org ////
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//// - Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_dc_fsm.v,v $
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// $Log: or1200_dc_fsm.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed.
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// Bugs fixed.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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`define OR1200_DCFSM_IDLE 3'd0
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`define OR1200_DCFSM_IDLE 3'd0
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`define OR1200_DCFSM_CLOADSTORE 3'd1
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`define OR1200_DCFSM_CLOADSTORE 3'd1
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`define OR1200_DCFSM_LOOP2 3'd2
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`define OR1200_DCFSM_LOOP2 3'd2
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`define OR1200_DCFSM_LOOP3 3'd3
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`define OR1200_DCFSM_LOOP3 3'd3
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`define OR1200_DCFSM_LOOP4 3'd4
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`define OR1200_DCFSM_LOOP4 3'd4
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`define OR1200_DCFSM_FLUSH5 3'd5
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`define OR1200_DCFSM_FLUSH5 3'd5
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`define OR1200_DCFSM_INV6 3'd6
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`define OR1200_DCFSM_INV6 3'd6
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`define OR1200_DCFSM_WAITSPRCS7 3'd7
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`define OR1200_DCFSM_WAITSPRCS7 3'd7
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//
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//
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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// Data cache FSM for cache line of 16 bytes (4x singleword)
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//
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//
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module or1200_dc_fsm
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module or1200_dc_fsm
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(
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(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f to top level DC
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// Internal i/f to top level DC
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dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
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dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
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tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
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tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
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dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack,
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dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack,
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first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr,
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first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr,
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dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush,
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dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush,
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dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
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dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input dc_en;
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input dc_en;
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input dcqmem_cycstb_i;
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input dcqmem_cycstb_i;
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input dcqmem_ci_i;
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input dcqmem_ci_i;
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input dcqmem_we_i;
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input dcqmem_we_i;
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input [3:0] dcqmem_sel_i;
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input [3:0] dcqmem_sel_i;
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input tagcomp_miss;
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input tagcomp_miss;
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input biudata_valid;
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input biudata_valid;
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input biudata_error;
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input biudata_error;
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input [31:0] lsu_addr;
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input [31:0] lsu_addr;
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output [3:0] dcram_we;
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output [3:0] dcram_we;
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output biu_read;
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output biu_read;
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output biu_write;
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output biu_write;
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output dcram_di_sel;
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output dcram_di_sel;
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output biu_do_sel;
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output biu_do_sel;
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output first_hit_ack;
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output first_hit_ack;
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output first_miss_ack;
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output first_miss_ack;
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output first_miss_err;
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output first_miss_err;
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output burst;
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output burst;
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output tag_we;
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output tag_we;
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output tag_valid;
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output tag_valid;
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output [31:0] dc_addr;
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output [31:0] dc_addr;
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input dc_no_writethrough;
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input dc_no_writethrough;
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output tag_dirty;
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output tag_dirty;
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input dirty;
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input dirty;
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input [`OR1200_DCTAG_W-2:0] tag;
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input [`OR1200_DCTAG_W-2:0] tag;
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input tag_v;
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input tag_v;
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input dc_block_flush;
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input dc_block_flush;
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input dc_block_writeback;
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input dc_block_writeback;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output mtspr_dc_done;
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output mtspr_dc_done;
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input spr_cswe;
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input spr_cswe;
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|
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:0] addr_r;
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reg [31:0] addr_r;
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reg [2:0] state;
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reg [2:0] state;
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reg [2:0] cnt;
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reg [`OR1200_DCLS-1:0] cnt;
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reg hitmiss_eval;
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reg hitmiss_eval;
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reg store;
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reg store;
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reg load;
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reg load;
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reg cache_inhibit;
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reg cache_inhibit;
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reg cache_miss;
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reg cache_miss;
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reg cache_dirty_needs_writeback;
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reg cache_dirty_needs_writeback;
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reg did_early_load_ack;
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reg did_early_load_ack;
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reg cache_spr_block_flush;
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reg cache_spr_block_flush;
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reg cache_spr_block_writeback;
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reg cache_spr_block_writeback;
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reg cache_wb;
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reg cache_wb;
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wire load_hit_ack;
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wire load_hit_ack;
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wire load_miss_ack;
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wire load_miss_ack;
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wire load_inhibit_ack;
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wire load_inhibit_ack;
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wire store_hit_ack;
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wire store_hit_ack;
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wire store_hit_writethrough_ack;
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wire store_hit_writethrough_ack;
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wire store_miss_writethrough_ack;
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wire store_miss_writethrough_ack;
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wire store_inhibit_ack;
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wire store_inhibit_ack;
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wire store_miss_ack;
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wire store_miss_ack;
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wire dcram_we_after_line_load;
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wire dcram_we_after_line_load;
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wire dcram_we_during_line_load;
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wire dcram_we_during_line_load;
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wire tagram_we_end_of_loadstore_loop;
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wire tagram_we_end_of_loadstore_loop;
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wire tagram_dirty_bit_set;
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wire tagram_dirty_bit_set;
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wire writethrough;
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wire writethrough;
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wire cache_inhibit_with_eval;
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wire cache_inhibit_with_eval;
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wire [1:0] next_addr_word;
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wire [(`OR1200_DCLS-1)-2:0] next_addr_word;
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//
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//
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// Cache inhibit
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// Cache inhibit
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//
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//
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|
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// Indicates whether cache is inhibited, during hitmiss_eval and after
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// Indicates whether cache is inhibited, during hitmiss_eval and after
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assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
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assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
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(!hitmiss_eval & cache_inhibit);
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(!hitmiss_eval & cache_inhibit);
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|
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//
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//
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// Generate of DCRAM write enables
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// Generate of DCRAM write enables
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//
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//
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// WE when non-writethrough, and had to wait for a line to load.
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// WE when non-writethrough, and had to wait for a line to load.
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assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
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assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
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dcqmem_we_i & !cache_dirty_needs_writeback &
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dcqmem_we_i & !cache_dirty_needs_writeback &
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!did_early_load_ack;
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!did_early_load_ack;
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// WE when receiving the data cache line
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// WE when receiving the data cache line
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assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load &
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assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load &
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biudata_valid;
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biudata_valid;
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assign dcram_we =(// Write when hit - make sure it is only when hit - could
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assign dcram_we =(// Write when hit - make sure it is only when hit - could
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// maybe be doing write through and don't want to corrupt
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// maybe be doing write through and don't want to corrupt
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// cache lines corresponding to the writethrough addr_r.
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// cache lines corresponding to the writethrough addr_r.
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({4{store_hit_ack | store_hit_writethrough_ack}} |
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({4{store_hit_ack | store_hit_writethrough_ack}} |
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// Write after load of line
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// Write after load of line
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{4{dcram_we_after_line_load}}) &
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{4{dcram_we_after_line_load}}) &
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dcqmem_sel_i ) |
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dcqmem_sel_i ) |
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// Write during load
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// Write during load
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{4{dcram_we_during_line_load}};
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{4{dcram_we_during_line_load}};
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//
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//
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// Tag RAM signals
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// Tag RAM signals
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//
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//
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// WE to tag RAM when we finish loading a line.
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// WE to tag RAM when we finish loading a line.
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assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) &
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assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) &
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biudata_valid & !(|cnt));
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biudata_valid & !(|cnt));
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|
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`ifndef OR1200_DC_WRITETHROUGH
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`ifndef OR1200_DC_WRITETHROUGH
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// No writethrough, so mark a line dirty whenever we write to it
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// No writethrough, so mark a line dirty whenever we write to it
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assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
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assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
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|
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// Generate done signal for MTSPR instructions that may block execution
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// Generate done signal for MTSPR instructions that may block execution
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assign mtspr_dc_done = // Either DC disabled or we're not selected, or
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assign mtspr_dc_done = // Either DC disabled or we're not selected, or
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!dc_en | !spr_cswe |
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!dc_en | !spr_cswe |
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// Requested address not valid or writeback and !dirty
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// Requested address not valid or writeback and !dirty
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((state==`OR1200_DCFSM_FLUSH5) &
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((state==`OR1200_DCFSM_FLUSH5) &
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(!tag_v | (cache_spr_block_writeback & !dirty))) |
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(!tag_v | (cache_spr_block_writeback & !dirty))) |
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// Writeback or flush is finished
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// Writeback or flush is finished
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((state==`OR1200_DCFSM_LOOP3) &
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((state==`OR1200_DCFSM_LOOP3) &
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(cache_spr_block_flush | cache_spr_block_writeback))|
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(cache_spr_block_flush | cache_spr_block_writeback))|
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// Invalidate of clean line finished
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// Invalidate of clean line finished
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((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
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((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
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|
|
|
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`else
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`else
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`ifdef OR1200_DC_NOSTACKWRITETHROUGH
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`ifdef OR1200_DC_NOSTACKWRITETHROUGH
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// For dirty bit setting when having writethrough but not for stack
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// For dirty bit setting when having writethrough but not for stack
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assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
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assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
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`else
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`else
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// Lines will never be dirty if always writethrough
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// Lines will never be dirty if always writethrough
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assign tagram_dirty_bit_set = 0;
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assign tagram_dirty_bit_set = 0;
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`endif
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`endif
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|
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assign mtspr_dc_done = 1'b1;
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assign mtspr_dc_done = 1'b1;
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|
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`endif
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`endif
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|
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assign tag_dirty = tagram_dirty_bit_set;
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assign tag_dirty = tagram_dirty_bit_set;
|
|
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// WE to tag RAM
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// WE to tag RAM
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assign tag_we = tagram_we_end_of_loadstore_loop |
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assign tag_we = tagram_we_end_of_loadstore_loop |
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tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
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tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
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|
|
|
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// Valid bit
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// Valid bit
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// Set valid when end of line load, or marking dirty (is still valid)
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// Set valid when end of line load, or marking dirty (is still valid)
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assign tag_valid = ( tagram_we_end_of_loadstore_loop &
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assign tag_valid = ( tagram_we_end_of_loadstore_loop &
|
(load | (store & cache_spr_block_writeback)) ) |
|
(load | (store & cache_spr_block_writeback)) ) |
|
tagram_dirty_bit_set;
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tagram_dirty_bit_set;
|
|
|
|
|
|
|
//
|
//
|
// BIU read and write
|
// BIU read and write
|
//
|
//
|
|
|
assign biu_read = // Bus read request when:
|
assign biu_read = // Bus read request when:
|
// 1) Have a miss and not dirty or a load with inhibit
|
// 1) Have a miss and not dirty or a load with inhibit
|
((state == `OR1200_DCFSM_CLOADSTORE) &
|
((state == `OR1200_DCFSM_CLOADSTORE) &
|
(((hitmiss_eval & tagcomp_miss & !dirty &
|
(((hitmiss_eval & tagcomp_miss & !dirty &
|
!(store & writethrough)) |
|
!(store & writethrough)) |
|
(load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |
|
(load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |
|
// 2) In the loop and loading
|
// 2) In the loop and loading
|
((state == `OR1200_DCFSM_LOOP2) & load);
|
((state == `OR1200_DCFSM_LOOP2) & load);
|
|
|
|
|
assign biu_write = // Bus write request when:
|
assign biu_write = // Bus write request when:
|
// 1) Have a miss and dirty or store with inhibit
|
// 1) Have a miss and dirty or store with inhibit
|
((state == `OR1200_DCFSM_CLOADSTORE) &
|
((state == `OR1200_DCFSM_CLOADSTORE) &
|
(((hitmiss_eval & tagcomp_miss & dirty) |
|
(((hitmiss_eval & tagcomp_miss & dirty) |
|
(store & writethrough)) |
|
(store & writethrough)) |
|
(store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |
|
(store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |
|
// 2) In the loop and storing
|
// 2) In the loop and storing
|
((state == `OR1200_DCFSM_LOOP2) & store);
|
((state == `OR1200_DCFSM_LOOP2) & store);
|
|
|
//
|
//
|
// Select for data to actual cache RAM (from LSU or BIU)
|
// Select for data to actual cache RAM (from LSU or BIU)
|
//
|
//
|
// Data to DCRAM - from external bus when loading (from IU when store)
|
// Data to DCRAM - from external bus when loading (from IU when store)
|
assign dcram_di_sel = load;
|
assign dcram_di_sel = load;
|
// Data to external bus - always from IU except in case of bursting back
|
// Data to external bus - always from IU except in case of bursting back
|
// the line to memory. (1 selects DCRAM)
|
// the line to memory. (1 selects DCRAM)
|
assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
|
assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
|
|
|
// 2-bit wire for calculating next word of burst write
|
// 3-bit wire for calculating next word of burst write, depending on
|
assign next_addr_word = addr_r[3:2] + 1;
|
// line size of data cache.
|
|
assign next_addr_word = addr_r[`OR1200_DCLS-1:2] + 1;
|
|
|
// Address to cache RAM (tag address also derived from this)
|
// Address to cache RAM (tag address also derived from this)
|
assign dc_addr =
|
assign dc_addr =
|
// First check if we've got a block flush or WB op
|
// First check if we've got a block flush or WB op
|
((dc_block_flush & !cache_spr_block_flush) |
|
((dc_block_flush & !cache_spr_block_flush) |
|
(dc_block_writeback & !cache_spr_block_writeback)) ?
|
(dc_block_writeback & !cache_spr_block_writeback)) ?
|
spr_dat_i :
|
spr_dat_i :
|
(state==`OR1200_DCFSM_FLUSH5) ? addr_r:
|
(state==`OR1200_DCFSM_FLUSH5) ? addr_r:
|
// If no SPR action, then always put out address from LSU
|
// If no SPR action, then always put out address from LSU
|
(state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :
|
(state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :
|
// Next, if in writeback loop, when ACKed must immediately
|
// Next, if in writeback loop, when ACKed must immediately
|
// output next word address (the RAM address takes a cycle
|
// output next word address (the RAM address takes a cycle
|
// to increment, but it's needed immediately for burst)
|
// to increment, but it's needed immediately for burst)
|
// otherwise, output our registered address.
|
// otherwise, output our registered address.
|
(state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
|
(state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
|
{addr_r[31:4], next_addr_word, 2'b00} : addr_r;
|
{addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
|
|
|
`ifdef OR1200_DC_WRITETHROUGH
|
`ifdef OR1200_DC_WRITETHROUGH
|
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
|
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
|
assign writethrough = !dc_no_writethrough;
|
assign writethrough = !dc_no_writethrough;
|
`else
|
`else
|
assign writethrough = 1;
|
assign writethrough = 1;
|
`endif
|
`endif
|
`else
|
`else
|
assign writethrough = 0;
|
assign writethrough = 0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// ACK generation for LSU
|
// ACK generation for LSU
|
//
|
//
|
|
|
// ACK for when it's a cache hit
|
// ACK for when it's a cache hit
|
assign first_hit_ack = load_hit_ack | store_hit_ack |
|
assign first_hit_ack = load_hit_ack | store_hit_ack |
|
store_hit_writethrough_ack |
|
store_hit_writethrough_ack |
|
store_miss_writethrough_ack |
|
store_miss_writethrough_ack |
|
store_inhibit_ack | store_miss_ack ;
|
store_inhibit_ack | store_miss_ack ;
|
|
|
// ACK for when it's a cache miss - load only, is used in MUX for data back
|
// ACK for when it's a cache miss - load only, is used in MUX for data back
|
// LSU straight off external data bus. In
|
// LSU straight off external data bus. In
|
// this was is also used for cache inhibit
|
// this was is also used for cache inhibit
|
// loads.
|
// loads.
|
assign first_miss_ack = load_miss_ack | load_inhibit_ack;
|
assign first_miss_ack = load_miss_ack | load_inhibit_ack;
|
|
|
// ACK cache hit on load
|
// ACK cache hit on load
|
assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
|
hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
|
|
|
// ACK cache hit on store, no writethrough
|
// ACK cache hit on store, no writethrough
|
assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
|
hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
|
store & !writethrough;
|
store & !writethrough;
|
|
|
// ACK cache hit on store with writethrough
|
// ACK cache hit on store with writethrough
|
assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
!cache_miss & !cache_inhibit &
|
!cache_miss & !cache_inhibit &
|
store & writethrough & biudata_valid;
|
store & writethrough & biudata_valid;
|
|
|
// ACK cache miss on store with writethrough
|
// ACK cache miss on store with writethrough
|
assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
cache_miss & !cache_inhibit &
|
cache_miss & !cache_inhibit &
|
store & writethrough & biudata_valid;
|
store & writethrough & biudata_valid;
|
|
|
// ACK store when cacheinhibit
|
// ACK store when cacheinhibit
|
assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
store & cache_inhibit & biudata_valid;
|
store & cache_inhibit & biudata_valid;
|
|
|
|
|
// Get the _early_ ack on first ACK back from wishbone during load only
|
// Get the _early_ ack on first ACK back from wishbone during load only
|
// Condition is that we're in the loop - that it's the first ack we get (can
|
// Condition is that we're in the loop - that it's the first ack we get (can
|
// tell from value of cnt), and we're loading a line to read from it (not
|
// tell from value of cnt), and we're loading a line to read from it (not
|
// loading to write to it, in the case of a write without writethrough.)
|
// loading to write to it, in the case of a write without writethrough.)
|
assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
|
assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
|
(cnt==`OR1200_DCLS-1) & biudata_valid &
|
(cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid &
|
!(dcqmem_we_i & !writethrough));
|
!(dcqmem_we_i & !writethrough));
|
|
|
assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
|
load & cache_inhibit & biudata_valid;
|
load & cache_inhibit & biudata_valid;
|
|
|
// This will be case of write through disabled, and had to load a line.
|
// This will be case of write through disabled, and had to load a line.
|
assign store_miss_ack = dcram_we_after_line_load;
|
assign store_miss_ack = dcram_we_after_line_load;
|
|
|
assign first_miss_err = biudata_error & dcqmem_cycstb_i;
|
assign first_miss_err = biudata_error & dcqmem_cycstb_i;
|
|
|
// Signal burst when in the load/store loop. We will always try to burst.
|
// Signal burst when in the load/store loop. We will always try to burst.
|
assign burst = (state == `OR1200_DCFSM_LOOP2);
|
assign burst = (state == `OR1200_DCFSM_LOOP2);
|
|
|
//
|
//
|
// Main DC FSM
|
// Main DC FSM
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
state <= `OR1200_DCFSM_IDLE;
|
state <= `OR1200_DCFSM_IDLE;
|
addr_r <= 32'b0;
|
addr_r <= 32'd0;
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
store <= 1'b0;
|
store <= 1'b0;
|
load <= 1'b0;
|
load <= 1'b0;
|
cnt <= 3'd0;
|
cnt <= `OR1200_DCLS'd0;
|
cache_miss <= 1'b0;
|
cache_miss <= 1'b0;
|
cache_dirty_needs_writeback <= 1'b0;
|
cache_dirty_needs_writeback <= 1'b0;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
did_early_load_ack <= 1'b0;
|
did_early_load_ack <= 1'b0;
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
end
|
end
|
else
|
else
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
|
|
`OR1200_DCFSM_IDLE : begin
|
`OR1200_DCFSM_IDLE : begin
|
if (dc_en & (dc_block_flush | dc_block_writeback))
|
if (dc_en & (dc_block_flush | dc_block_writeback))
|
begin
|
begin
|
cache_spr_block_flush <= dc_block_flush;
|
cache_spr_block_flush <= dc_block_flush;
|
cache_spr_block_writeback <= dc_block_writeback;
|
cache_spr_block_writeback <= dc_block_writeback;
|
hitmiss_eval <= 1'b1;
|
hitmiss_eval <= 1'b1;
|
state <= `OR1200_DCFSM_FLUSH5;
|
state <= `OR1200_DCFSM_FLUSH5;
|
addr_r <= spr_dat_i;
|
addr_r <= spr_dat_i;
|
end
|
end
|
else if (dc_en & dcqmem_cycstb_i)
|
else if (dc_en & dcqmem_cycstb_i)
|
begin
|
begin
|
state <= `OR1200_DCFSM_CLOADSTORE;
|
state <= `OR1200_DCFSM_CLOADSTORE;
|
hitmiss_eval <= 1'b1;
|
hitmiss_eval <= 1'b1;
|
store <= dcqmem_we_i;
|
store <= dcqmem_we_i;
|
load <= !dcqmem_we_i;
|
load <= !dcqmem_we_i;
|
end
|
end
|
|
|
|
|
end // case: `OR1200_DCFSM_IDLE
|
end // case: `OR1200_DCFSM_IDLE
|
|
|
`OR1200_DCFSM_CLOADSTORE: begin
|
`OR1200_DCFSM_CLOADSTORE: begin
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
if (hitmiss_eval) begin
|
if (hitmiss_eval) begin
|
cache_inhibit <= dcqmem_ci_i; // Check for cache inhibit here
|
cache_inhibit <= dcqmem_ci_i; // Check for cache inhibit here
|
cache_miss <= tagcomp_miss;
|
cache_miss <= tagcomp_miss;
|
cache_dirty_needs_writeback <= dirty;
|
cache_dirty_needs_writeback <= dirty;
|
addr_r <= lsu_addr;
|
addr_r <= lsu_addr;
|
end
|
end
|
|
|
// Evaluate any cache line load/stores in first cycle:
|
// Evaluate any cache line load/stores in first cycle:
|
//
|
//
|
if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
|
if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
|
!dcqmem_ci_i)
|
!dcqmem_ci_i)
|
begin
|
begin
|
// Miss - first either:
|
// Miss - first either:
|
// 1) write back dirty line
|
// 1) write back dirty line
|
if (dirty) begin
|
if (dirty) begin
|
// Address for writeback
|
// Address for writeback
|
addr_r <= {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
|
addr_r <= {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
|
load <= 1'b0;
|
load <= 1'b0;
|
store <= 1'b1;
|
store <= 1'b1;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
$display("%t: dcache miss and dirty", $time);
|
$display("%t: dcache miss and dirty", $time);
|
`endif
|
`endif
|
end
|
end
|
// 2) load requested line
|
// 2) load requested line
|
else begin
|
else begin
|
addr_r <= lsu_addr;
|
addr_r <= lsu_addr;
|
load <= 1'b1;
|
load <= 1'b1;
|
store <= 1'b0;
|
store <= 1'b0;
|
end // else: !if(dirty)
|
end // else: !if(dirty)
|
state <= `OR1200_DCFSM_LOOP2;
|
state <= `OR1200_DCFSM_LOOP2;
|
// Set the counter for the burst accesses
|
// Set the counter for the burst accesses
|
cnt <= `OR1200_DCLS-1;
|
cnt <= ((1 << `OR1200_DCLS) - 4);
|
end
|
end
|
else if (// Strobe goes low
|
else if (// Strobe goes low
|
!dcqmem_cycstb_i |
|
!dcqmem_cycstb_i |
|
// Cycle finishes
|
// Cycle finishes
|
(!hitmiss_eval & (biudata_valid | biudata_error)) |
|
(!hitmiss_eval & (biudata_valid | biudata_error)) |
|
// Cache hit in first cycle....
|
// Cache hit in first cycle....
|
(hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
|
(hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
|
// .. and you're not doing a writethrough store..
|
// .. and you're not doing a writethrough store..
|
!(store & writethrough))) begin
|
!(store & writethrough))) begin
|
state <= `OR1200_DCFSM_IDLE;
|
state <= `OR1200_DCFSM_IDLE;
|
load <= 1'b0;
|
load <= 1'b0;
|
store <= 1'b0;
|
store <= 1'b0;
|
cache_inhibit <= 1'b0;
|
cache_inhibit <= 1'b0;
|
cache_dirty_needs_writeback <= 1'b0;
|
cache_dirty_needs_writeback <= 1'b0;
|
end
|
end
|
end // case: `OR1200_DCFSM_CLOADSTORE
|
end // case: `OR1200_DCFSM_CLOADSTORE
|
|
|
`OR1200_DCFSM_LOOP2 : begin // loop/abort
|
`OR1200_DCFSM_LOOP2 : begin // loop/abort
|
if (!dc_en| biudata_error) begin
|
if (!dc_en| biudata_error) begin
|
state <= `OR1200_DCFSM_IDLE;
|
state <= `OR1200_DCFSM_IDLE;
|
load <= 1'b0;
|
load <= 1'b0;
|
store <= 1'b0;
|
store <= 1'b0;
|
cnt <= 3'd0;
|
cnt <= `OR1200_DCLS'd0;
|
end
|
end
|
if (biudata_valid & (|cnt)) begin
|
if (biudata_valid & (|cnt)) begin
|
cnt <= cnt - 3'd1;
|
cnt <= cnt - 4;
|
addr_r[3:2] <= addr_r[3:2] + 1'b1;
|
addr_r[`OR1200_DCLS-1:2] <= addr_r[`OR1200_DCLS-1:2] + 1;
|
end
|
end
|
else if (biudata_valid & !(|cnt)) begin
|
else if (biudata_valid & !(|cnt)) begin
|
state <= `OR1200_DCFSM_LOOP3;
|
state <= `OR1200_DCFSM_LOOP3;
|
addr_r <= lsu_addr;
|
addr_r <= lsu_addr;
|
load <= 1'b0;
|
load <= 1'b0;
|
store <= 1'b0;
|
store <= 1'b0;
|
end
|
end
|
|
|
// Track if we did an early ack during a load
|
// Track if we did an early ack during a load
|
if (load_miss_ack)
|
if (load_miss_ack)
|
did_early_load_ack <= 1'b1;
|
did_early_load_ack <= 1'b1;
|
|
|
|
|
end // case: `OR1200_DCFSM_LOOP2
|
end // case: `OR1200_DCFSM_LOOP2
|
|
|
`OR1200_DCFSM_LOOP3: begin // figure out next step
|
`OR1200_DCFSM_LOOP3: begin // figure out next step
|
if (cache_dirty_needs_writeback) begin
|
if (cache_dirty_needs_writeback) begin
|
// Just did store of the dirty line so now load new one
|
// Just did store of the dirty line so now load new one
|
load <= 1'b1;
|
load <= 1'b1;
|
// Set the counter for the burst accesses
|
// Set the counter for the burst accesses
|
cnt <= `OR1200_DCLS-1;
|
cnt <= ((1 << `OR1200_DCLS) - 4);
|
// Address of line to be loaded
|
// Address of line to be loaded
|
addr_r <= lsu_addr;
|
addr_r <= lsu_addr;
|
cache_dirty_needs_writeback <= 1'b0;
|
cache_dirty_needs_writeback <= 1'b0;
|
state <= `OR1200_DCFSM_LOOP2;
|
state <= `OR1200_DCFSM_LOOP2;
|
end // if (cache_dirty_needs_writeback)
|
end // if (cache_dirty_needs_writeback)
|
else if (cache_spr_block_flush | cache_spr_block_writeback) begin
|
else if (cache_spr_block_flush | cache_spr_block_writeback) begin
|
// Just wrote back the line to memory, we're finished.
|
// Just wrote back the line to memory, we're finished.
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
state <= `OR1200_DCFSM_WAITSPRCS7;
|
state <= `OR1200_DCFSM_WAITSPRCS7;
|
end
|
end
|
else begin
|
else begin
|
// Just loaded a new line, finish up
|
// Just loaded a new line, finish up
|
did_early_load_ack <= 1'b0;
|
did_early_load_ack <= 1'b0;
|
state <= `OR1200_DCFSM_LOOP4;
|
state <= `OR1200_DCFSM_LOOP4;
|
end
|
end
|
end // case: `OR1200_DCFSM_LOOP3
|
end // case: `OR1200_DCFSM_LOOP3
|
|
|
`OR1200_DCFSM_LOOP4: begin
|
`OR1200_DCFSM_LOOP4: begin
|
state <= `OR1200_DCFSM_IDLE;
|
state <= `OR1200_DCFSM_IDLE;
|
end
|
end
|
|
|
`OR1200_DCFSM_FLUSH5: begin
|
`OR1200_DCFSM_FLUSH5: begin
|
hitmiss_eval <= 1'b0;
|
hitmiss_eval <= 1'b0;
|
if (hitmiss_eval & !tag_v)
|
if (hitmiss_eval & !tag_v)
|
begin
|
begin
|
// Not even cached, just ignore
|
// Not even cached, just ignore
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
state <= `OR1200_DCFSM_WAITSPRCS7;
|
state <= `OR1200_DCFSM_WAITSPRCS7;
|
end
|
end
|
else if (hitmiss_eval & tag_v)
|
else if (hitmiss_eval & tag_v)
|
begin
|
begin
|
// Tag is valid - what do we do?
|
// Tag is valid - what do we do?
|
if ((cache_spr_block_flush | cache_spr_block_writeback) &
|
if ((cache_spr_block_flush | cache_spr_block_writeback) &
|
dirty) begin
|
dirty) begin
|
// Need to writeback
|
// Need to writeback
|
// Address for writeback (spr_dat_i has already changed so
|
// Address for writeback (spr_dat_i has already changed so
|
// use line number from addr_r)
|
// use line number from addr_r)
|
addr_r <= {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
|
addr_r <= {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
|
load <= 1'b0;
|
load <= 1'b0;
|
store <= 1'b1;
|
store <= 1'b1;
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
$display("%t: block flush: dirty block", $time);
|
$display("%t: block flush: dirty block", $time);
|
`endif
|
`endif
|
state <= `OR1200_DCFSM_LOOP2;
|
state <= `OR1200_DCFSM_LOOP2;
|
// Set the counter for the burst accesses
|
// Set the counter for the burst accesses
|
cnt <= `OR1200_DCLS-1;
|
cnt <= ((1 << `OR1200_DCLS) - 4);
|
end
|
end
|
else if (cache_spr_block_flush & !dirty)
|
else if (cache_spr_block_flush & !dirty)
|
begin
|
begin
|
// Line not dirty, just need to invalidate
|
// Line not dirty, just need to invalidate
|
state <= `OR1200_DCFSM_INV6;
|
state <= `OR1200_DCFSM_INV6;
|
end // else: !if(dirty)
|
end // else: !if(dirty)
|
else if (cache_spr_block_writeback & !dirty)
|
else if (cache_spr_block_writeback & !dirty)
|
begin
|
begin
|
// Nothing to do - line is valid but not dirty
|
// Nothing to do - line is valid but not dirty
|
cache_spr_block_writeback <= 1'b0;
|
cache_spr_block_writeback <= 1'b0;
|
state <= `OR1200_DCFSM_WAITSPRCS7;
|
state <= `OR1200_DCFSM_WAITSPRCS7;
|
end
|
end
|
end // if (hitmiss_eval & tag_v)
|
end // if (hitmiss_eval & tag_v)
|
end
|
end
|
`OR1200_DCFSM_INV6: begin
|
`OR1200_DCFSM_INV6: begin
|
cache_spr_block_flush <= 1'b0;
|
cache_spr_block_flush <= 1'b0;
|
// Wait until SPR CS goes low before going back to idle
|
// Wait until SPR CS goes low before going back to idle
|
if (!spr_cswe)
|
if (!spr_cswe)
|
state <= `OR1200_DCFSM_IDLE;
|
state <= `OR1200_DCFSM_IDLE;
|
end
|
end
|
`OR1200_DCFSM_WAITSPRCS7: begin
|
`OR1200_DCFSM_WAITSPRCS7: begin
|
// Wait until SPR CS goes low before going back to idle
|
// Wait until SPR CS goes low before going back to idle
|
if (!spr_cswe)
|
if (!spr_cswe)
|
state <= `OR1200_DCFSM_IDLE;
|
state <= `OR1200_DCFSM_IDLE;
|
end
|
end
|
|
|
endcase // case (state)
|
endcase // case (state)
|
|
|
end // always @ (posedge clk or `OR1200_RST_EVENT rst)
|
end // always @ (posedge clk or `OR1200_RST_EVENT rst)
|
|
|
|
|
endmodule
|
endmodule
|
|
|
