//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Load/Store unit ////
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//// OR1200's Load/Store unit ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Interface between CPU and DC. ////
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//// Interface between CPU and DC. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// $Log: or1200_lsu.v,v $
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// $Log: or1200_lsu.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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module or1200_lsu(
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module or1200_lsu(
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// Clock and Reset
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// Clock and Reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f
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// Internal i/f
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id_addrbase, ex_addrbase, id_addrofs, ex_addrofs, id_lsu_op,
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id_addrbase, ex_addrbase, id_addrofs, ex_addrofs, id_lsu_op,
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lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
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du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
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id_freeze, ex_freeze, flushpipe,
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id_freeze, ex_freeze, flushpipe,
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|
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// External i/f to DC
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// External i/f to DC
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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|
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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|
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [31:0] id_addrbase;
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input [31:0] id_addrbase;
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input [31:0] ex_addrbase;
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input [31:0] ex_addrbase;
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input [31:0] id_addrofs;
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input [31:0] id_addrofs;
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input [31:0] ex_addrofs;
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input [31:0] ex_addrofs;
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input [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
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input [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
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input [dw-1:0] lsu_datain;
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input [dw-1:0] lsu_datain;
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output [dw-1:0] lsu_dataout;
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output [dw-1:0] lsu_dataout;
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output lsu_stall;
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output lsu_stall;
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output lsu_unstall;
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output lsu_unstall;
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input du_stall;
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input du_stall;
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output except_align;
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output except_align;
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output except_dtlbmiss;
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output except_dtlbmiss;
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output except_dmmufault;
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output except_dmmufault;
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output except_dbuserr;
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output except_dbuserr;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input flushpipe;
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input flushpipe;
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|
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//
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//
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// External i/f to DC
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// External i/f to DC
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//
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//
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output [31:0] dcpu_adr_o;
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output [31:0] dcpu_adr_o;
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output dcpu_cycstb_o;
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output dcpu_cycstb_o;
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output dcpu_we_o;
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output dcpu_we_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_sel_o;
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output [3:0] dcpu_tag_o;
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output [3:0] dcpu_tag_o;
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output [31:0] dcpu_dat_o;
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output [31:0] dcpu_dat_o;
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input [31:0] dcpu_dat_i;
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input [31:0] dcpu_dat_i;
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input dcpu_ack_i;
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input dcpu_ack_i;
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input dcpu_rty_i;
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input dcpu_rty_i;
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input dcpu_err_i;
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input dcpu_err_i;
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input [3:0] dcpu_tag_i;
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input [3:0] dcpu_tag_i;
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|
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//
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//
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// Internal wires/regs
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// Internal wires/regs
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//
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//
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reg [3:0] dcpu_sel_o;
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reg [3:0] dcpu_sel_o;
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|
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reg [`OR1200_LSUOP_WIDTH-1:0] ex_lsu_op;
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reg [`OR1200_LSUOP_WIDTH-1:0] ex_lsu_op;
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wire [`OR1200_LSUEA_PRECALC:0] id_precalc_sum;
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wire [`OR1200_LSUEA_PRECALC:0] id_precalc_sum;
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reg [`OR1200_LSUEA_PRECALC:0] dcpu_adr_r;
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reg [`OR1200_LSUEA_PRECALC:0] dcpu_adr_r;
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reg except_align;
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reg except_align;
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|
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//
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//
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// ex_lsu_op
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// ex_lsu_op
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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ex_lsu_op <= `OR1200_LSUOP_NOP;
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ex_lsu_op <= `OR1200_LSUOP_NOP;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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ex_lsu_op <= `OR1200_LSUOP_NOP;
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ex_lsu_op <= `OR1200_LSUOP_NOP;
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else if (!ex_freeze)
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else if (!ex_freeze)
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ex_lsu_op <= id_lsu_op;
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ex_lsu_op <= id_lsu_op;
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end
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end
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//
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//
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// Precalculate part of load/store EA in ID stage
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// Precalculate part of load/store EA in ID stage
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//
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//
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assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
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assign id_precalc_sum = id_addrbase[`OR1200_LSUEA_PRECALC-1:0] +
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id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
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id_addrofs[`OR1200_LSUEA_PRECALC-1:0];
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|
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}};
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dcpu_adr_r <= {`OR1200_LSUEA_PRECALC+1{1'b0}};
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else if (!ex_freeze)
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else if (!ex_freeze)
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dcpu_adr_r <= id_precalc_sum;
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dcpu_adr_r <= id_precalc_sum;
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end
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end
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|
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//
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//
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// Generate except_align in ID stage
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// Generate except_align in ID stage
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//
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//
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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always @(posedge clk or `OR1200_RST_EVENT rst) begin
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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except_align <= 1'b0;
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except_align <= 1'b0;
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else if (!ex_freeze & id_freeze | flushpipe)
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else if (!ex_freeze & id_freeze | flushpipe)
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except_align <= 1'b0;
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except_align <= 1'b0;
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else if (!ex_freeze)
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else if (!ex_freeze)
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except_align <= ((id_lsu_op == `OR1200_LSUOP_SH) |
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except_align <= ((id_lsu_op == `OR1200_LSUOP_SH) |
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(id_lsu_op == `OR1200_LSUOP_LHZ) |
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(id_lsu_op == `OR1200_LSUOP_LHZ) |
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(id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
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(id_lsu_op == `OR1200_LSUOP_LHS)) & id_precalc_sum[0]
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| ((id_lsu_op == `OR1200_LSUOP_SW) |
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| ((id_lsu_op == `OR1200_LSUOP_SW) |
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(id_lsu_op == `OR1200_LSUOP_LWZ) |
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(id_lsu_op == `OR1200_LSUOP_LWZ) |
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(id_lsu_op == `OR1200_LSUOP_LWS)) & |id_precalc_sum[1:0];
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(id_lsu_op == `OR1200_LSUOP_LWS)) & |id_precalc_sum[1:0];
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end
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end
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|
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//
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//
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// Internal I/F assignments
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// Internal I/F assignments
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//
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//
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
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assign lsu_unstall = dcpu_ack_i;
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assign lsu_unstall = dcpu_ack_i;
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
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|
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//
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//
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// External I/F assignments
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// External I/F assignments
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//
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//
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assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] + ex_addrofs[31:`OR1200_LSUEA_PRECALC] + dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
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assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] =
|
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ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
|
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(ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
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// carry from precalc, pad to 30-bits
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{{(32-`OR1200_LSUEA_PRECALC)-1{1'b0}},
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dcpu_adr_r[`OR1200_LSUEA_PRECALC]});
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assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
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assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
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assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ?
|
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ?
|
1'b0 : |ex_lsu_op;
|
1'b0 : |ex_lsu_op;
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assign dcpu_we_o = ex_lsu_op[3];
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assign dcpu_we_o = ex_lsu_op[3];
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
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always @(ex_lsu_op or dcpu_adr_o)
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always @(ex_lsu_op or dcpu_adr_o)
|
casex({ex_lsu_op, dcpu_adr_o[1:0]})
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casez({ex_lsu_op, dcpu_adr_o[1:0]})
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
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{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
|
{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
|
{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
|
{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
|
{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
|
{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
|
{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
|
{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
|
{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
|
{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
|
{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
|
{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
|
{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
|
{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
|
{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
|
{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
|
{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
|
{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
|
{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
|
{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
|
{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
|
{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
|
{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
|
{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
|
{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
|
default : dcpu_sel_o = 4'b0000;
|
default : dcpu_sel_o = 4'b0000;
|
endcase
|
endcase
|
|
|
//
|
//
|
// Instantiation of Memory-to-regfile aligner
|
// Instantiation of Memory-to-regfile aligner
|
//
|
//
|
or1200_mem2reg or1200_mem2reg(
|
or1200_mem2reg or1200_mem2reg(
|
.addr(dcpu_adr_o[1:0]),
|
.addr(dcpu_adr_o[1:0]),
|
.lsu_op(ex_lsu_op),
|
.lsu_op(ex_lsu_op),
|
.memdata(dcpu_dat_i),
|
.memdata(dcpu_dat_i),
|
.regdata(lsu_dataout)
|
.regdata(lsu_dataout)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of Regfile-to-memory aligner
|
// Instantiation of Regfile-to-memory aligner
|
//
|
//
|
or1200_reg2mem or1200_reg2mem(
|
or1200_reg2mem or1200_reg2mem(
|
.addr(dcpu_adr_o[1:0]),
|
.addr(dcpu_adr_o[1:0]),
|
.lsu_op(ex_lsu_op),
|
.lsu_op(ex_lsu_op),
|
.regdata(lsu_datain),
|
.regdata(lsu_datain),
|
.memdata(dcpu_dat_o)
|
.memdata(dcpu_dat_o)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
