//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Generic Single-Port Synchronous RAM ////
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//// Generic Single-Port Synchronous RAM ////
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//// ////
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//// ////
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//// This file is part of memory library available from ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// This block is a wrapper with common single-port ////
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//// This block is a wrapper with common single-port ////
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//// synchronous memory interface for different ////
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//// synchronous memory interface for different ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// interface it also provides behavioral model of generic ////
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//// interface it also provides behavioral model of generic ////
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//// single-port synchronous RAM. ////
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//// single-port synchronous RAM. ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// portable accross different target technologies and ////
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//// portable accross different target technologies and ////
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//// independent of target memory. ////
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//// independent of target memory. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: or1200_dpram_32x32.v,v $
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// $Log: or1200_dpram_32x32.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// New
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// New
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_spram
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module or1200_spram
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(
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(
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, ce, we, addr, di, doq
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clk, rst, ce, we, addr, di, doq
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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, p_err
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, p_err
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`endif
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`endif
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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parameter aw = 10;
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parameter aw = 10;
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parameter dw = 32;
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parameter dw = 32;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input ce; // Chip enable input
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input ce; // Chip enable input
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input we; // Write enable input
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input we; // Write enable input
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input [aw-1:0] addr; // address bus inputs
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input [aw-1:0] addr; // address bus inputs
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input [dw-1:0] di; // input data bus
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input [dw-1:0] di; // input data bus
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output [dw-1:0] doq; // output data bus
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output [dw-1:0] doq; // output data bus
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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output p_err; // parity error indicator
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output p_err; // parity error indicator
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`endif
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`endif
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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//
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//
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// Generic single-port synchronous RAM model
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// Generic single-port synchronous RAM model
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//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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reg [(dw+(dw/8))-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter par_w = (dw/8);
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reg [(dw+par_w)-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`else
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`else
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`endif
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`endif
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reg [aw-1:0] addr_reg; // RAM address register
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reg [aw-1:0] addr_reg; // RAM address register
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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wire [(dw+(dw/8))-1:0] doq_wire;
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wire [(dw+par_w)-1:0] doq_wire;
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wire [(dw/8)-1:0] di_p;
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wire [par_w-1:0] di_p;
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wire [(dw/8)-1:0] do_p;
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wire [par_w-1:0] do_p;
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wire [(dw/8)-1:0] parity_err;
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wire [par_w-1:0] parity_err;
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reg ce_r;
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`else
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`else
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wire [dw-1:0] doq_wire;
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wire [dw-1:0] doq_wire;
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`endif
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`endif
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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genvar i;
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genvar i;
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generate
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generate
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for (i=0;i<(dw/8);i=i+1) begin: paritygen
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for (i=0;i<par_w;i=i+1) begin: paritygen
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or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
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or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
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or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
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or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
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.p_i(do_p[i]), .err_o(parity_err[i]));
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.p_i(do_p[i]), .err_o(parity_err[i]));
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end
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end
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endgenerate
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endgenerate
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// Extract parity bits of data out
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// Extract parity bits of data out
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assign do_p = doq_wire[(dw+(dw/8))-1:dw];
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assign do_p = doq_wire[(dw+par_w)-1:dw];
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always @(posedge clk)
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if (rst)
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ce_r <= 0;
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else
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ce_r <= ce;
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// Indicate error
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// Indicate error
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assign p_err = (|parity_err);
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assign p_err = (|parity_err) & ce_r;
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// Inject a parity error. Can specify GPR number to affect,
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// Inject a parity error.
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// and which parity or data bit to switch.
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task gen_parity_err;
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task gen_parity_err;
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input [aw-1:0] gpr_no;
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input [aw-1:0] addr;
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input [31:0] parity_bit_no;
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input [31:0] parity_bit_no;
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input [31:0] data_bit_no;
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input [31:0] data_bit_no;
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reg [(dw+(dw/8))-1:0] do_temp;
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reg [(dw+par_w)-1:0] do_temp;
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begin
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begin
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do_temp = mem[gpr_no];
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do_temp = mem[addr];
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// Switch parity bit
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// Switch parity bit
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if (parity_bit_no > 0 && parity_bit_no <= (dw/8))
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if (parity_bit_no >= 0 && parity_bit_no < par_w)
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do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
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do_temp[dw+parity_bit_no] = ~do_temp[dw+parity_bit_no];
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// Switch data bit
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// Switch data bit
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if (data_bit_no > 0 && data_bit_no <= dw)
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if (data_bit_no >= 0 && data_bit_no < dw)
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do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
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do_temp[data_bit_no] = ~do_temp[data_bit_no];
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// Write word back
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// Write word back
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mem[gpr_no] = do_temp;
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mem[addr] = do_temp;
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end
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end
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endtask // gen_parity_err
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endtask // gen_parity_err
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`endif
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`endif
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//
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//
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// Data output drivers
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// Data output drivers
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//
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//
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assign doq_wire = mem[addr_reg];
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assign doq_wire = mem[addr_reg];
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assign doq = doq_wire[dw-1:0];
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assign doq = doq_wire[dw-1:0];
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//
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//
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// RAM read address register
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// RAM read address register
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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addr_reg <= addr;
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addr_reg <= addr;
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//
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//
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// RAM write
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// RAM write
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (we && ce)
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`ifdef OR1200_RAM_PARITY
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`ifdef OR1200_RAM_PARITY
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if (we && ce)
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mem[addr] <= {di_p,di};
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mem[addr] <= {di_p,di};
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`else
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`else
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if (we && ce)
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mem[addr] <= di;
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mem[addr] <= di;
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`endif
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`endif
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endmodule // or1200_spram
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endmodule // or1200_spram
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