//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's interface to SPRs ////
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//// OR1200's interface to SPRs ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Decoding of SPR addresses and access to SPRs ////
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//// Decoding of SPR addresses and access to SPRs ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_sprs.v,v $
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// $Log: or1200_sprs.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_sprs(
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module or1200_sprs(
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// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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|
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// Internal CPU interface
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// Internal CPU interface
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
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addrbase, addrofs, dat_i, branch_op, ex_spr_read,
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ex_spr_write,
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epcr, eear, esr, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
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spr_dat_mac,
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boot_adr_sel_i,
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boot_adr_sel_i,
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// Floating point SPR input
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// Floating point SPR input
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fpcsr, fpcsr_we, spr_dat_fpu,
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fpcsr, fpcsr_we, spr_dat_fpu,
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|
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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du_addr, du_dat_du, du_read,
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du_addr, du_dat_du, du_read,
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du_write, du_dat_cpu
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du_write, du_dat_cpu
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|
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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|
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//
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//
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// I/O Ports
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// I/O Ports
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//
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//
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|
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//
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//
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// Internal CPU interface
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// Internal CPU interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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input flagforw; // From ALU
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input flagforw; // From ALU
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input flag_we; // From ALU
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input flag_we; // From ALU
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output flag; // SR[F]
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output flag; // SR[F]
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input cyforw; // From ALU
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input cyforw; // From ALU
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input cy_we; // From ALU
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input cy_we; // From ALU
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output carry; // SR[CY]
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output carry; // SR[CY]
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input [width-1:0] addrbase; // SPR base address
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input [width-1:0] addrbase; // SPR base address
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input [15:0] addrofs; // SPR offset
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input [15:0] addrofs; // SPR offset
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input [width-1:0] dat_i; // SPR write data
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input [width-1:0] dat_i; // SPR write data
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_read; // l.mfspr in EX
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input ex_spr_write; // l.mtspr in EX
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input ex_spr_write; // l.mtspr in EX
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [width-1:0] epcr /* verilator public */; // EPCR0
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input [width-1:0] epcr /* verilator public */;// EPCR0
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input [width-1:0] eear /* verilator public */; // EEAR0
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input [width-1:0] eear /* verilator public */;// EEAR0
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input [`OR1200_SR_WIDTH-1:0] esr /* verilator public */; // ESR0
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input [`OR1200_SR_WIDTH-1:0] esr /* verilator public */; // ESR0
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input except_started; // Exception was started
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input except_started; // Exception was started
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output [width-1:0] to_wbmux; // For l.mfspr
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output [width-1:0] to_wbmux; // For l.mfspr
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output epcr_we; // EPCR0 write enable
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output epcr_we; // EPCR0 write enable
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output eear_we; // EEAR0 write enable
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output eear_we; // EEAR0 write enable
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output esr_we; // ESR0 write enable
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output esr_we; // ESR0 write enable
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output pc_we; // PC write enable
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output pc_we; // PC write enable
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output sr_we; // Write enable SR
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output sr_we; // Write enable SR
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output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
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output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
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output [`OR1200_SR_WIDTH-1:0] sr /* verilator public */; // SR
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output [`OR1200_SR_WIDTH-1:0] sr /* verilator public */;// SR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_rf; // Data from RF
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_npc; // Data from NPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_ppc; // Data from PPC
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input [31:0] spr_dat_mac; // Data from MAC
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input [31:0] spr_dat_mac; // Data from MAC
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input boot_adr_sel_i;
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input boot_adr_sel_i;
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|
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input [`OR1200_FPCSR_WIDTH-1:0] fpcsr; // FPCSR
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input [`OR1200_FPCSR_WIDTH-1:0] fpcsr; // FPCSR
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output fpcsr_we; // Write enable FPCSR
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output fpcsr_we; // Write enable FPCSR
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input [31:0] spr_dat_fpu; // Data from FPU
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input [31:0] spr_dat_fpu; // Data from FPU
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|
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//
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//
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// To/from other RISC units
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// To/from other RISC units
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//
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//
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_tt; // Data from TT
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input [31:0] spr_dat_tt; // Data from TT
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input [31:0] spr_dat_pm; // Data from PM
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input [31:0] spr_dat_pm; // Data from PM
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input [31:0] spr_dat_dmmu; // Data from DMMU
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input [31:0] spr_dat_dmmu; // Data from DMMU
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input [31:0] spr_dat_immu; // Data from IMMU
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input [31:0] spr_dat_immu; // Data from IMMU
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input [31:0] spr_dat_du; // Data from DU
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input [31:0] spr_dat_du; // Data from DU
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output [31:0] spr_addr; // SPR Address
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output [31:0] spr_addr; // SPR Address
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output [31:0] spr_dat_o; // Data to unit
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output [31:0] spr_dat_o; // Data to unit
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output [31:0] spr_cs; // Unit select
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output [31:0] spr_cs; // Unit select
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output spr_we; // SPR write enable
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output spr_we; // SPR write enable
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|
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//
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//
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// To/from Debug Unit
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// To/from Debug Unit
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//
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//
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input [width-1:0] du_addr; // Address
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input [width-1:0] du_addr; // Address
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input [width-1:0] du_dat_du; // Data from DU to SPRS
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input [width-1:0] du_dat_du; // Data from DU to SPRS
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input du_read; // Read qualifier
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input du_read; // Read qualifier
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input du_write; // Write qualifier
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input du_write; // Write qualifier
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output [width-1:0] du_dat_cpu; // Data from SPRS to DU
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output [width-1:0] du_dat_cpu; // Data from SPRS to DU
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|
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//
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//
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// Internal regs & wires
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// Internal regs & wires
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//
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//
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reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
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reg sr_reg_bit_eph; // SR_EPH bit
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reg sr_reg_bit_eph; // SR_EPH bit
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reg sr_reg_bit_eph_select; // SR_EPH select
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reg sr_reg_bit_eph_select;// SR_EPH select
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wire sr_reg_bit_eph_muxed; // SR_EPH muxed bit
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wire sr_reg_bit_eph_muxed;// SR_EPH muxed bit
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg [width-1:0] to_wbmux; // For l.mfspr
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reg [width-1:0] to_wbmux; // For l.mfspr
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wire cfgr_sel; // Select for cfg regs
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wire cfgr_sel; // Select for cfg regs
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wire rf_sel; // Select for RF
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wire rf_sel; // Select for RF
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wire npc_sel; // Select for NPC
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wire npc_sel; // Select for NPC
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wire ppc_sel; // Select for PPC
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wire ppc_sel; // Select for PPC
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wire sr_sel; // Select for SR
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wire sr_sel; // Select for SR
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wire epcr_sel; // Select for EPCR0
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wire epcr_sel; // Select for EPCR0
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wire eear_sel; // Select for EEAR0
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wire eear_sel; // Select for EEAR0
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wire esr_sel; // Select for ESR0
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wire esr_sel; // Select for ESR0
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wire fpcsr_sel; // Select for FPCSR
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wire fpcsr_sel; // Select for FPCSR
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wire [31:0] sys_data; // Read data from system SPRs
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wire [31:0] sys_data;// Read data from system SPRs
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wire du_access; // Debug unit access
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wire du_access; // Debug unit access
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reg [31:0] unqualified_cs; // Unqualified chip selects
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reg [31:0] unqualified_cs; // Unqualified selects
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wire ex_spr_write; // jb
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wire ex_spr_write; // jb
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|
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//
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//
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// Decide if it is debug unit access
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// Decide if it is debug unit access
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//
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//
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assign du_access = du_read | du_write;
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assign du_access = du_read | du_write;
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|
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//
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//
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// Generate SPR address from base address and offset
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// Generate SPR address from base address and offset
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// OR from debug unit address
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// OR from debug unit address
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//
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//
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assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
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assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
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//
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//
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// SPR is written by debug unit or by l.mtspr
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// SPR is written by debug unit or by l.mtspr
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//
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//
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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//
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//
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// debug unit data input:
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// debug unit data input:
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// - read of SPRS by debug unit
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// - read of SPRS by debug unit
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// - write into debug unit SPRs by debug unit itself
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// - write into debug unit SPRs by debug unit itself
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// - write into debug unit SPRs by l.mtspr
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// - write into debug unit SPRs by l.mtspr
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//
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//
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assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
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assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
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//
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//
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// Write into SPRs when DU or l.mtspr
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// Write into SPRs when DU or l.mtspr
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//
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//
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assign spr_we = du_write | ( ex_spr_write & !du_access );
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assign spr_we = du_write | ( ex_spr_write & !du_access );
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//
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//
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// Qualify chip selects
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// Qualify chip selects
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//
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//
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assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
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assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read |
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(ex_spr_write & sr[`OR1200_SR_SM])}};
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//
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//
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// Decoding of groups
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// Decoding of groups
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//
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//
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always @(spr_addr)
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always @(spr_addr)
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case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
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`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs
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`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
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= 32'b00000000_00000000_00000000_00000001;
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`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
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`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs
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`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
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= 32'b00000000_00000000_00000000_00000010;
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`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
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`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs
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`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
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= 32'b00000000_00000000_00000000_00000100;
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`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
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`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs
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`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
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= 32'b00000000_00000000_00000000_00001000;
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`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
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`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs
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`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
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= 32'b00000000_00000000_00000000_00010000;
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`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
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`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
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= 32'b00000000_00000000_00000000_00100000;
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`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
|
= 32'b00000000_00000000_00000000_01000000;
|
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
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`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
|
= 32'b00000000_00000000_00000000_10000000;
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`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
|
= 32'b00000000_00000000_00000001_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
|
= 32'b00000000_00000000_00000010_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
|
= 32'b00000000_00000000_00000100_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
|
= 32'b00000000_00000000_00001000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
|
= 32'b00000000_00000000_00010000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
|
= 32'b00000000_00000000_00100000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
|
= 32'b00000000_00000000_01000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
|
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs
|
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
|
= 32'b00000000_00000000_10000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs
|
|
= 32'b00000000_00000001_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs
|
|
= 32'b00000000_00000010_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs
|
|
= 32'b00000000_00000100_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs
|
|
= 32'b00000000_00001000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs
|
|
= 32'b00000000_00010000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs
|
|
= 32'b00000000_00100000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs
|
|
= 32'b00000000_01000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs
|
|
= 32'b00000000_10000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs
|
|
= 32'b00000001_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs
|
|
= 32'b00000010_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs
|
|
= 32'b00000100_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs
|
|
= 32'b00001000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs
|
|
= 32'b00010000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs
|
|
= 32'b00100000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs
|
|
= 32'b01000000_00000000_00000000_00000000;
|
|
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs
|
|
= 32'b10000000_00000000_00000000_00000000;
|
endcase
|
endcase
|
|
|
//
|
//
|
// SPRs System Group
|
// SPRs System Group
|
//
|
//
|
|
|
//
|
//
|
// What to write into SR
|
// What to write into SR
|
//
|
//
|
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
|
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV]
|
(except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
|
= (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ?
|
(spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
|
esr[`OR1200_SR_FO:`OR1200_SR_OV] : (spr_we && sr_sel) ?
|
|
{1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]} :
|
sr[`OR1200_SR_FO:`OR1200_SR_OV];
|
sr[`OR1200_SR_FO:`OR1200_SR_OV];
|
assign to_sr[`OR1200_SR_TED] =
|
assign to_sr[`OR1200_SR_TED]
|
(except_started) ? 1'b1 :
|
= (except_started) ? 1'b1 :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
|
sr[`OR1200_SR_TED];
|
sr[`OR1200_SR_TED];
|
assign to_sr[`OR1200_SR_CY] =
|
|
(except_started) ? sr[`OR1200_SR_CY] :
|
assign to_sr[`OR1200_SR_CY]
|
|
= (except_started) ? sr[`OR1200_SR_CY] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
|
cy_we ? cyforw :
|
cy_we ? cyforw :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
|
sr[`OR1200_SR_CY];
|
sr[`OR1200_SR_CY];
|
assign to_sr[`OR1200_SR_F] =
|
assign to_sr[`OR1200_SR_F]
|
(except_started) ? sr[`OR1200_SR_F] :
|
= (except_started) ? sr[`OR1200_SR_F] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
|
flag_we ? flagforw :
|
flag_we ? flagforw :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
|
sr[`OR1200_SR_F];
|
sr[`OR1200_SR_F];
|
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
|
|
(except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
|
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM]
|
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
|
= (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00,
|
(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
|
sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
|
|
(branch_op == `OR1200_BRANCHOP_RFE) ?
|
|
esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ?
|
|
spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
|
sr[`OR1200_SR_CE:`OR1200_SR_SM];
|
sr[`OR1200_SR_CE:`OR1200_SR_SM];
|
|
|
//
|
//
|
// Selects for system SPRs
|
// Selects for system SPRs
|
//
|
//
|
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
|
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
|
(spr_addr[10:4] == `OR1200_SPR_CFGR));
|
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
|
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
|
(spr_addr[10:5] == `OR1200_SPR_RF));
|
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
|
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
|
(spr_addr[10:0] == `OR1200_SPR_NPC));
|
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
|
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
|
(spr_addr[10:0] == `OR1200_SPR_PPC));
|
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
|
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_SR));
|
|
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_EPCR));
|
|
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_EEAR));
|
|
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_ESR));
|
|
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
|
|
(spr_addr[10:0] == `OR1200_SPR_FPCSR));
|
|
|
|
|
//
|
//
|
// Write enables for system SPRs
|
// Write enables for system SPRs
|
//
|
//
|
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
|
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
|
|
flag_we | cy_we;
|
assign pc_we = (du_write && (npc_sel | ppc_sel));
|
assign pc_we = (du_write && (npc_sel | ppc_sel));
|
assign epcr_we = (spr_we && epcr_sel);
|
assign epcr_we = (spr_we && epcr_sel);
|
assign eear_we = (spr_we && eear_sel);
|
assign eear_we = (spr_we && eear_sel);
|
assign esr_we = (spr_we && esr_sel);
|
assign esr_we = (spr_we && esr_sel);
|
assign fpcsr_we = (spr_we && fpcsr_sel);
|
assign fpcsr_we = (spr_we && fpcsr_sel);
|
|
|
//
|
//
|
// Output from system SPRs
|
// Output from system SPRs
|
//
|
//
|
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
|
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
|
(spr_dat_rf & {32{rf_sel}}) |
|
(spr_dat_rf & {32{rf_sel}}) |
|
(spr_dat_npc & {32{npc_sel}}) |
|
(spr_dat_npc & {32{npc_sel}}) |
|
(spr_dat_ppc & {32{ppc_sel}}) |
|
(spr_dat_ppc & {32{ppc_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
|
(epcr & {32{epcr_sel}}) |
|
(epcr & {32{epcr_sel}}) |
|
(eear & {32{eear_sel}}) |
|
(eear & {32{eear_sel}}) |
|
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
|
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
|
|
{32{fpcsr_sel}}) |
|
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
|
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
|
|
|
//
|
//
|
// Flag alias
|
// Flag alias
|
//
|
//
|
assign flag = sr[`OR1200_SR_F];
|
assign flag = sr[`OR1200_SR_F];
|
|
|
//
|
//
|
// Carry alias
|
// Carry alias
|
//
|
//
|
assign carry = sr[`OR1200_SR_CY];
|
assign carry = sr[`OR1200_SR_CY];
|
|
|
//
|
//
|
// Supervision register
|
// Supervision register
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
sr_reg <= {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
|
sr_reg <= {2'b01, // Fixed one.
|
|
`OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
|
else if (except_started)
|
else if (except_started)
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
else if (sr_we)
|
else if (sr_we)
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
|
|
|
// EPH part of Supervision register
|
// EPH part of Supervision register
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
always @(posedge clk or `OR1200_RST_EVENT rst)
|
// default value
|
// default value
|
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
|
sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
|
sr_reg_bit_eph_select <= 1'b1; // select async. value due to reset state
|
// select async. value due to reset state
|
|
sr_reg_bit_eph_select <= 1'b1;
|
end
|
end
|
// selected value (different from default) is written into FF after reset state
|
// selected value (different from default) is written into FF after reset
|
|
// state
|
else if (sr_reg_bit_eph_select) begin
|
else if (sr_reg_bit_eph_select) begin
|
sr_reg_bit_eph <= boot_adr_sel_i; // dynamic value can only be assigned to FF out of reset!
|
// dynamic value can only be assigned to FF out of reset!
|
|
sr_reg_bit_eph <= boot_adr_sel_i;
|
sr_reg_bit_eph_select <= 1'b0; // select FF value
|
sr_reg_bit_eph_select <= 1'b0; // select FF value
|
end
|
end
|
else if (sr_we) begin
|
else if (sr_we) begin
|
sr_reg_bit_eph <= to_sr[`OR1200_SR_EPH];
|
sr_reg_bit_eph <= to_sr[`OR1200_SR_EPH];
|
end
|
end
|
|
|
// select async. value of EPH bit after reset
|
// select async. value of EPH bit after reset
|
assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
|
assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ?
|
|
boot_adr_sel_i : sr_reg_bit_eph;
|
|
|
// EPH part joined together with rest of Supervision register
|
// EPH part joined together with rest of Supervision register
|
always @(sr_reg or sr_reg_bit_eph_muxed)
|
always @(sr_reg or sr_reg_bit_eph_muxed)
|
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
|
sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
|
|
sr_reg[`OR1200_SR_WIDTH-4:0]};
|
|
|
`ifdef verilator
|
`ifdef verilator
|
// Function to access various sprs (for Verilator). Have to hide this from
|
// Function to access various sprs (for Verilator). Have to hide this from
|
// simulator, since functions with no inputs are not allowed in IEEE
|
// simulator, since functions with no inputs are not allowed in IEEE
|
// 1364-2001.
|
// 1364-2001.
|
|
|
function [31:0] get_sr;
|
function [31:0] get_sr;
|
// verilator public
|
// verilator public
|
get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
|
get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
|
endfunction // get_sr
|
endfunction // get_sr
|
|
|
function [31:0] get_epcr;
|
function [31:0] get_epcr;
|
// verilator public
|
// verilator public
|
get_epcr = epcr;
|
get_epcr = epcr;
|
endfunction // get_epcr
|
endfunction // get_epcr
|
|
|
function [31:0] get_eear;
|
function [31:0] get_eear;
|
// verilator public
|
// verilator public
|
get_eear = eear;
|
get_eear = eear;
|
endfunction // get_eear
|
endfunction // get_eear
|
|
|
function [31:0] get_esr;
|
function [31:0] get_esr;
|
// verilator public
|
// verilator public
|
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
|
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
|
endfunction // get_esr
|
endfunction // get_esr
|
|
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// MTSPR/MFSPR interface
|
// MTSPR/MFSPR interface
|
//
|
//
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
|
spr_dat_fpu or
|
spr_dat_fpu or
|
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
|
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
|
casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
|
`OR1200_SPR_GROUP_SYS:
|
`OR1200_SPR_GROUP_SYS:
|
to_wbmux = sys_data;
|
to_wbmux = sys_data;
|
`OR1200_SPR_GROUP_TT:
|
`OR1200_SPR_GROUP_TT:
|
to_wbmux = spr_dat_tt;
|
to_wbmux = spr_dat_tt;
|
`OR1200_SPR_GROUP_PIC:
|
`OR1200_SPR_GROUP_PIC:
|
to_wbmux = spr_dat_pic;
|
to_wbmux = spr_dat_pic;
|
`OR1200_SPR_GROUP_PM:
|
`OR1200_SPR_GROUP_PM:
|
to_wbmux = spr_dat_pm;
|
to_wbmux = spr_dat_pm;
|
`OR1200_SPR_GROUP_DMMU:
|
`OR1200_SPR_GROUP_DMMU:
|
to_wbmux = spr_dat_dmmu;
|
to_wbmux = spr_dat_dmmu;
|
`OR1200_SPR_GROUP_IMMU:
|
`OR1200_SPR_GROUP_IMMU:
|
to_wbmux = spr_dat_immu;
|
to_wbmux = spr_dat_immu;
|
`OR1200_SPR_GROUP_MAC:
|
`OR1200_SPR_GROUP_MAC:
|
to_wbmux = spr_dat_mac;
|
to_wbmux = spr_dat_mac;
|
`OR1200_SPR_GROUP_FPU:
|
`OR1200_SPR_GROUP_FPU:
|
to_wbmux = spr_dat_fpu;
|
to_wbmux = spr_dat_fpu;
|
default: //`OR1200_SPR_GROUP_DU:
|
default: //`OR1200_SPR_GROUP_DU:
|
to_wbmux = spr_dat_du;
|
to_wbmux = spr_dat_du;
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
