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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_tt.v] - Diff between revs 360 and 411

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  OR1200's Tick Timer                                         ////
////  OR1200's Tick Timer                                         ////
////                                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  TT according to OR1K architectural specification.           ////
////  TT according to OR1K architectural specification.           ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   None                                                       ////
////   None                                                       ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
 
//
 
// $Log: or1200_tt.v,v $
 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
 
// No update 
 
//
 
// Revision 1.5  2004/06/08 18:17:36  lampret
 
// Non-functional changes. Coding style fixes.
 
//
 
// Revision 1.4  2002/03/29 15:16:56  lampret
 
// Some of the warnings fixed.
 
//
 
// Revision 1.3  2002/02/12 01:33:47  lampret
 
// No longer using async rst as sync reset for the counter.
 
//
 
// Revision 1.2  2002/01/28 01:16:00  lampret
 
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
 
//
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
 
// Revision 1.10  2001/11/13 10:00:49  lampret
 
// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
 
//
 
// Revision 1.9  2001/11/10 03:43:57  lampret
 
// Fixed exceptions.
 
//
 
// Revision 1.8  2001/10/21 17:57:16  lampret
 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
 
//
 
// Revision 1.7  2001/10/14 13:12:10  lampret
 
// MP3 version.
 
//
 
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
 
// no message
 
//
 
// Revision 1.2  2001/08/09 13:39:33  lampret
 
// Major clean-up.
 
//
 
// Revision 1.1  2001/07/20 00:46:23  lampret
 
// Development version of RTL. Libraries are missing.
 
//
 
//
 
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module or1200_tt(
module or1200_tt(
        // RISC Internal Interface
        // RISC Internal Interface
        clk, rst, du_stall,
        clk, rst, du_stall,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        intr
        intr
);
);
 
 
//
//
// RISC Internal Interface
// RISC Internal Interface
//
//
input           clk;            // Clock
input           clk;            // Clock
input           rst;            // Reset
input           rst;            // Reset
input           du_stall;       // DU stall
input           du_stall;       // DU stall
input           spr_cs;         // SPR CS
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          intr;           // Interrupt output
output          intr;           // Interrupt output
 
 
`ifdef OR1200_TT_IMPLEMENTED
`ifdef OR1200_TT_IMPLEMENTED
 
 
//
//
// TT Mode Register bits (or no register)
// TT Mode Register bits (or no register)
//
//
`ifdef OR1200_TT_TTMR
`ifdef OR1200_TT_TTMR
reg     [31:0]   ttmr;   // TTMR bits
reg     [31:0]   ttmr;   // TTMR bits
`else
`else
wire    [31:0]   ttmr;   // No TTMR register
wire    [31:0]   ttmr;   // No TTMR register
`endif
`endif
 
 
//
//
// TT Count Register bits (or no register)
// TT Count Register bits (or no register)
//
//
`ifdef OR1200_TT_TTCR
`ifdef OR1200_TT_TTCR
reg     [31:0]   ttcr;   // TTCR bits
reg     [31:0]   ttcr;   // TTCR bits
`else
`else
wire    [31:0]   ttcr;   // No TTCR register
wire    [31:0]   ttcr;   // No TTCR register
`endif
`endif
 
 
//
//
// Internal wires & regs
// Internal wires & regs
//
//
wire            ttmr_sel;       // TTMR select
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted
wire            stop;           // Stop counter when asserted
reg     [31:0]   spr_dat_o;      // SPR data out
reg     [31:0]   spr_dat_o;      // SPR data out
 
 
//
//
// TT registers address decoder
// TT registers address decoder
//
//
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
 
 
//
//
// Write to TTMR or update of TTMR[IP] bit
// Write to TTMR or update of TTMR[IP] bit
//
//
`ifdef OR1200_TT_TTMR
`ifdef OR1200_TT_TTMR
always @(posedge clk or `OR1200_RST_EVENT rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
        if (rst == `OR1200_RST_VALUE)
                ttmr <= 32'b0;
                ttmr <= 32'b0;
        else if (ttmr_sel && spr_write)
        else if (ttmr_sel && spr_write)
                ttmr <=  spr_dat_i;
                ttmr <=  spr_dat_i;
        else if (ttmr[`OR1200_TT_TTMR_IE])
        else if (ttmr[`OR1200_TT_TTMR_IE])
                ttmr[`OR1200_TT_TTMR_IP] <=  ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
                ttmr[`OR1200_TT_TTMR_IP] <=  ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
`else
`else
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
`endif
`endif
 
 
//
//
// Write to or increment of TTCR
// Write to or increment of TTCR
//
//
`ifdef OR1200_TT_TTCR
`ifdef OR1200_TT_TTCR
always @(posedge clk or `OR1200_RST_EVENT rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
        if (rst == `OR1200_RST_VALUE)
                ttcr <= 32'b0;
                ttcr <= 32'b0;
        else if (restart)
        else if (restart)
                ttcr <=  32'b0;
                ttcr <=  32'b0;
        else if (ttcr_sel && spr_write)
        else if (ttcr_sel && spr_write)
                ttcr <=  spr_dat_i;
                ttcr <=  spr_dat_i;
        else if (!stop)
        else if (!stop)
                ttcr <=  ttcr + 32'd1;
                ttcr <=  ttcr + 32'd1;
`else
`else
assign ttcr = 32'b0;
assign ttcr = 32'b0;
`endif
`endif
 
 
//
//
// Read TT registers
// Read TT registers
//
//
always @(spr_addr or ttmr or ttcr)
always @(spr_addr or ttmr or ttcr)
        case (spr_addr[`OR1200_TTOFS_BITS])     // synopsys parallel_case
        case (spr_addr[`OR1200_TTOFS_BITS])     // synopsys parallel_case
`ifdef OR1200_TT_READREGS
`ifdef OR1200_TT_READREGS
                `OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
                `OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
`endif
                default: spr_dat_o = ttcr;
                default: spr_dat_o = ttcr;
        endcase
        endcase
 
 
//
//
// A match when TTMR[TP] is equal to TTCR[27:0]
// A match when TTMR[TP] is equal to TTCR[27:0]
//
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
 
 
//
//
// Restart when match and TTMR[M]==0x1
// Restart when match and TTMR[M]==0x1
//
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
 
 
//
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
 
 
//
//
// Generate an interrupt request
// Generate an interrupt request
//
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
assign intr = ttmr[`OR1200_TT_TTMR_IP];
 
 
`else
`else
 
 
//
//
// When TT is not implemented, drive all outputs as would when TT is disabled
// When TT is not implemented, drive all outputs as would when TT is disabled
//
//
assign intr = 1'b0;
assign intr = 1'b0;
 
 
//
//
// Read TT registers
// Read TT registers
//
//
`ifdef OR1200_TT_READREGS
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
assign spr_dat_o = 32'b0;
`endif
`endif
 
 
`endif
`endif
 
 
endmodule
endmodule
 
 

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