//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Tick Timer ////
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//// OR1200's Tick Timer ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// TT according to OR1K architectural specification. ////
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//// TT according to OR1K architectural specification. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// None ////
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//// None ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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//
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// $Log: or1200_tt.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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//
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// Revision 1.5 2004/06/08 18:17:36 lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.4 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.3 2002/02/12 01:33:47 lampret
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// No longer using async rst as sync reset for the counter.
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//
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// Revision 1.2 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/13 10:00:49 lampret
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// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:23 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_tt(
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module or1200_tt(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst, du_stall,
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clk, rst, du_stall,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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intr
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intr
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);
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);
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//
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//
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// RISC Internal Interface
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// RISC Internal Interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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input du_stall; // DU stall
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input du_stall; // DU stall
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input spr_cs; // SPR CS
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input spr_cs; // SPR CS
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input spr_write; // SPR Write
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input spr_write; // SPR Write
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_addr; // SPR Address
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input [31:0] spr_dat_i; // SPR Write Data
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input [31:0] spr_dat_i; // SPR Write Data
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output [31:0] spr_dat_o; // SPR Read Data
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output [31:0] spr_dat_o; // SPR Read Data
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output intr; // Interrupt output
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output intr; // Interrupt output
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`ifdef OR1200_TT_IMPLEMENTED
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`ifdef OR1200_TT_IMPLEMENTED
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//
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//
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// TT Mode Register bits (or no register)
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// TT Mode Register bits (or no register)
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//
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//
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`ifdef OR1200_TT_TTMR
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`ifdef OR1200_TT_TTMR
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reg [31:0] ttmr; // TTMR bits
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reg [31:0] ttmr; // TTMR bits
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`else
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`else
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wire [31:0] ttmr; // No TTMR register
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wire [31:0] ttmr; // No TTMR register
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`endif
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`endif
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//
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//
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// TT Count Register bits (or no register)
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// TT Count Register bits (or no register)
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//
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//
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`ifdef OR1200_TT_TTCR
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`ifdef OR1200_TT_TTCR
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reg [31:0] ttcr; // TTCR bits
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reg [31:0] ttcr; // TTCR bits
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`else
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`else
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wire [31:0] ttcr; // No TTCR register
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wire [31:0] ttcr; // No TTCR register
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`endif
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`endif
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//
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//
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// Internal wires & regs
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// Internal wires & regs
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//
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//
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wire ttmr_sel; // TTMR select
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wire ttmr_sel; // TTMR select
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wire ttcr_sel; // TTCR select
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wire ttcr_sel; // TTCR select
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wire match; // Asserted when TTMR[TP]
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wire match; // Asserted when TTMR[TP]
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// is equal to TTCR[27:0]
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// is equal to TTCR[27:0]
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wire restart; // Restart counter when asserted
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wire restart; // Restart counter when asserted
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wire stop; // Stop counter when asserted
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wire stop; // Stop counter when asserted
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reg [31:0] spr_dat_o; // SPR data out
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reg [31:0] spr_dat_o; // SPR data out
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//
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//
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// TT registers address decoder
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// TT registers address decoder
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//
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//
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assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
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assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
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assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
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assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
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//
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//
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// Write to TTMR or update of TTMR[IP] bit
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// Write to TTMR or update of TTMR[IP] bit
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//
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//
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`ifdef OR1200_TT_TTMR
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`ifdef OR1200_TT_TTMR
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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ttmr <= 32'b0;
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ttmr <= 32'b0;
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else if (ttmr_sel && spr_write)
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else if (ttmr_sel && spr_write)
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ttmr <= spr_dat_i;
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ttmr <= spr_dat_i;
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else if (ttmr[`OR1200_TT_TTMR_IE])
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else if (ttmr[`OR1200_TT_TTMR_IE])
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ttmr[`OR1200_TT_TTMR_IP] <= ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
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ttmr[`OR1200_TT_TTMR_IP] <= ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
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`else
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`else
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assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
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assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
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`endif
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`endif
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//
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//
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// Write to or increment of TTCR
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// Write to or increment of TTCR
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//
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//
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`ifdef OR1200_TT_TTCR
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`ifdef OR1200_TT_TTCR
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always @(posedge clk or `OR1200_RST_EVENT rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst == `OR1200_RST_VALUE)
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if (rst == `OR1200_RST_VALUE)
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ttcr <= 32'b0;
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ttcr <= 32'b0;
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else if (restart)
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else if (restart)
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ttcr <= 32'b0;
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ttcr <= 32'b0;
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else if (ttcr_sel && spr_write)
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else if (ttcr_sel && spr_write)
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ttcr <= spr_dat_i;
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ttcr <= spr_dat_i;
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else if (!stop)
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else if (!stop)
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ttcr <= ttcr + 32'd1;
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ttcr <= ttcr + 32'd1;
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`else
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`else
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assign ttcr = 32'b0;
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assign ttcr = 32'b0;
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`endif
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`endif
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//
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//
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// Read TT registers
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// Read TT registers
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//
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//
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always @(spr_addr or ttmr or ttcr)
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always @(spr_addr or ttmr or ttcr)
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case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
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case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
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`ifdef OR1200_TT_READREGS
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`ifdef OR1200_TT_READREGS
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`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
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`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
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`endif
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`endif
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default: spr_dat_o = ttcr;
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default: spr_dat_o = ttcr;
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endcase
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endcase
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//
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//
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// A match when TTMR[TP] is equal to TTCR[27:0]
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// A match when TTMR[TP] is equal to TTCR[27:0]
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//
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//
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assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
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assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
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//
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//
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// Restart when match and TTMR[M]==0x1
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// Restart when match and TTMR[M]==0x1
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//
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//
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assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
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assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
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//
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//
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// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
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// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
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//
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//
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assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
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assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
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//
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//
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// Generate an interrupt request
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// Generate an interrupt request
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//
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//
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assign intr = ttmr[`OR1200_TT_TTMR_IP];
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assign intr = ttmr[`OR1200_TT_TTMR_IP];
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`else
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`else
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//
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//
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// When TT is not implemented, drive all outputs as would when TT is disabled
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// When TT is not implemented, drive all outputs as would when TT is disabled
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//
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//
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assign intr = 1'b0;
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assign intr = 1'b0;
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//
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//
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// Read TT registers
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// Read TT registers
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//
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//
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`ifdef OR1200_TT_READREGS
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`ifdef OR1200_TT_READREGS
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assign spr_dat_o = 32'b0;
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assign spr_dat_o = 32'b0;
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`endif
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`endif
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`endif
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`endif
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endmodule
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endmodule
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