module ram_wb_b3(
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module ram_wb_b3(
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wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
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wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
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wb_stb_i, wb_we_i,
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wb_stb_i, wb_we_i,
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wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
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wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
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wb_clk_i, wb_rst_i);
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wb_clk_i, wb_rst_i);
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parameter dw = 32;
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parameter dw = 32;
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parameter aw = 32;
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parameter aw = 32;
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input [aw-1:0] wb_adr_i;
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input [aw-1:0] wb_adr_i;
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input [1:0] wb_bte_i;
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input [1:0] wb_bte_i;
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input [2:0] wb_cti_i;
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input [2:0] wb_cti_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input [dw-1:0] wb_dat_i;
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input [dw-1:0] wb_dat_i;
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input [3:0] wb_sel_i;
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input [3:0] wb_sel_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_we_i;
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input wb_we_i;
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output wb_ack_o;
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output wb_ack_o;
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output wb_err_o;
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output wb_err_o;
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output wb_rty_o;
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output wb_rty_o;
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output [dw-1:0] wb_dat_o;
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output [dw-1:0] wb_dat_o;
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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// Memory parameters
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// Memory parameters
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parameter mem_size_bytes = 32'h0000_5000; // 20KBytes
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parameter mem_size_bytes = 32'h0000_5000; // 20KBytes
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parameter mem_adr_width = 15; //(log2(mem_size_bytes));
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parameter mem_adr_width = 15; //(log2(mem_size_bytes));
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parameter bytes_per_dw = (dw/8);
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parameter bytes_per_dw = (dw/8);
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parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
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parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
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parameter mem_words = (mem_size_bytes/bytes_per_dw);
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parameter mem_words = (mem_size_bytes/bytes_per_dw);
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// synthesis attribute ram_style of mem is block
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// synthesis attribute ram_style of mem is block
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reg [dw-1:0] mem [ 0 : mem_words-1 ] /* synthesis ram_style = no_rw_check */;
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reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
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// Register to address internal memory array
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// Register to address internal memory array
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reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
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reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
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wire [31:0] wr_data;
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wire [31:0] wr_data;
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// Register to indicate if the cycle is a Wishbone B3-registered feedback
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// Register to indicate if the cycle is a Wishbone B3-registered feedback
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// type access
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// type access
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reg wb_b3_trans;
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reg wb_b3_trans;
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wire wb_b3_trans_start, wb_b3_trans_stop;
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wire wb_b3_trans_start, wb_b3_trans_stop;
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// Register to use for counting the addresses when doing burst accesses
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// Register to use for counting the addresses when doing burst accesses
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reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
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reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
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reg [2:0] wb_cti_i_r;
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reg [2:0] wb_cti_i_r;
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reg [1:0] wb_bte_i_r;
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reg [1:0] wb_bte_i_r;
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wire using_burst_adr;
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wire using_burst_adr;
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wire burst_access_wrong_wb_adr;
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wire burst_access_wrong_wb_adr;
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// Wire to indicate addressing error
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// Wire to indicate addressing error
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wire addr_err;
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wire addr_err;
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// Logic to detect if there's a burst access going on
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// Logic to detect if there's a burst access going on
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assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
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assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
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wb_stb_i & !wb_b3_trans;
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wb_stb_i & !wb_b3_trans;
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assign wb_b3_trans_stop = (wb_cti_i == 3'b111) &
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assign wb_b3_trans_stop = (wb_cti_i == 3'b111) &
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wb_stb_i & wb_b3_trans & wb_ack_o;
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wb_stb_i & wb_b3_trans & wb_ack_o;
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_b3_trans <= 0;
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wb_b3_trans <= 0;
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else if (wb_b3_trans_start)
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else if (wb_b3_trans_start)
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wb_b3_trans <= 1;
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wb_b3_trans <= 1;
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else if (wb_b3_trans_stop)
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else if (wb_b3_trans_stop)
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wb_b3_trans <= 0;
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wb_b3_trans <= 0;
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// Burst address generation logic
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// Burst address generation logic
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always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
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always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
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or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
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or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
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if (wb_b3_trans_start)
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if (wb_b3_trans_start)
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// Kick off burst_adr_counter, this assumes 4-byte words when getting
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// Kick off burst_adr_counter, this assumes 4-byte words when getting
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// address off incoming Wishbone bus address!
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// address off incoming Wishbone bus address!
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// So if dw is no longer 4 bytes, change this!
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// So if dw is no longer 4 bytes, change this!
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burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
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burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
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else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
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else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
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// Incrementing burst
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// Incrementing burst
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begin
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begin
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if (wb_bte_i_r == 2'b00) // Linear burst
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if (wb_bte_i_r == 2'b00) // Linear burst
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burst_adr_counter = adr + 1;
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burst_adr_counter = adr + 1;
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if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
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if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
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burst_adr_counter[1:0] = adr[1:0] + 1;
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burst_adr_counter[1:0] = adr[1:0] + 1;
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if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
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if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
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burst_adr_counter[2:0] = adr[2:0] + 1;
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burst_adr_counter[2:0] = adr[2:0] + 1;
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if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
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if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
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burst_adr_counter[3:0] = adr[3:0] + 1;
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burst_adr_counter[3:0] = adr[3:0] + 1;
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end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
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end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_bte_i_r <= wb_bte_i;
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wb_bte_i_r <= wb_bte_i;
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// Register it locally
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// Register it locally
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_cti_i_r <= wb_cti_i;
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wb_cti_i_r <= wb_cti_i;
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assign using_burst_adr = wb_b3_trans;
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assign using_burst_adr = wb_b3_trans;
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assign burst_access_wrong_wb_adr = (using_burst_adr &
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assign burst_access_wrong_wb_adr = (using_burst_adr &
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(adr != wb_adr_i[mem_adr_width-1:2]));
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(adr != wb_adr_i[mem_adr_width-1:2]));
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// Address registering logic
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// Address registering logic
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always@(posedge wb_clk_i)
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always@(posedge wb_clk_i)
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if(wb_rst_i)
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if(wb_rst_i)
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adr <= 0;
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adr <= 0;
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else if (using_burst_adr)
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else if (using_burst_adr)
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adr <= burst_adr_counter;
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adr <= burst_adr_counter;
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else if (wb_cyc_i & wb_stb_i)
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else if (wb_cyc_i & wb_stb_i)
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adr <= wb_adr_i[mem_adr_width-1:2];
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adr <= wb_adr_i[mem_adr_width-1:2];
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/* Memory initialisation.
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If not Verilator model, always do load, otherwise only load when called
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from SystemC testbench.
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*/
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parameter memory_file = "sram.vmem";
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parameter memory_file = "sram.vmem";
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`ifdef verilator
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task do_readmemh;
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// verilator public
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$readmemh(memory_file, mem);
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endtask // do_readmemh
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`else
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initial
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initial
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begin
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begin
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$readmemh(memory_file, mem);
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$readmemh(memory_file, mem);
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end
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end
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`endif // !`ifdef verilator
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assign wb_rty_o = 0;
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assign wb_rty_o = 0;
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// mux for data to ram, RMW on part sel != 4'hf
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// mux for data to ram, RMW on part sel != 4'hf
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assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
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assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
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assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
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assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
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assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
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assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
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assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
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wire ram_we;
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wire ram_we;
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assign ram_we = wb_we_i & wb_ack_o;
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assign ram_we = wb_we_i & wb_ack_o;
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assign wb_dat_o = mem[adr];
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assign wb_dat_o = mem[adr];
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// Write logic
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// Write logic
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i)
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begin
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begin
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if (ram_we)
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if (ram_we)
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mem[adr] <= wr_data;
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mem[adr] <= wr_data;
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end
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end
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// Ack Logic
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// Ack Logic
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reg wb_ack_o_r;
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reg wb_ack_o_r;
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assign wb_ack_o = wb_ack_o_r & wb_stb_i;
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assign wb_ack_o = wb_ack_o_r & wb_stb_i;
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always @ (posedge wb_clk_i)
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always @ (posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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wb_ack_o_r <= 1'b0;
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wb_ack_o_r <= 1'b0;
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else if (wb_cyc_i) // We have bus
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else if (wb_cyc_i) // We have bus
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begin
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begin
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if (addr_err & wb_stb_i)
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if (addr_err & wb_stb_i)
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begin
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begin
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wb_ack_o_r <= 1;
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wb_ack_o_r <= 1;
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end
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end
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else if (wb_cti_i == 3'b000)
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else if (wb_cti_i == 3'b000)
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begin
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begin
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// Classic cycle acks
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// Classic cycle acks
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if (wb_stb_i)
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if (wb_stb_i)
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begin
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begin
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if (!wb_ack_o_r)
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if (!wb_ack_o_r)
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wb_ack_o_r <= 1;
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wb_ack_o_r <= 1;
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else
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else
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wb_ack_o_r <= 0;
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wb_ack_o_r <= 0;
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end
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end
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end // if (wb_cti_i == 3'b000)
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end // if (wb_cti_i == 3'b000)
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else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
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else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
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begin
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begin
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// Increment/constant address bursts
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// Increment/constant address bursts
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if (wb_stb_i)
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if (wb_stb_i)
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wb_ack_o_r <= 1;
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wb_ack_o_r <= 1;
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else
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else
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wb_ack_o_r <= 0;
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wb_ack_o_r <= 0;
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end
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end
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else if (wb_cti_i == 3'b111)
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else if (wb_cti_i == 3'b111)
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begin
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begin
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// End of cycle
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// End of cycle
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if (!wb_ack_o_r)
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if (!wb_ack_o_r)
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wb_ack_o_r <= wb_stb_i;
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wb_ack_o_r <= wb_stb_i;
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else
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else
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wb_ack_o_r <= 0;
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wb_ack_o_r <= 0;
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end
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end
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end // if (wb_cyc_i)
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end // if (wb_cyc_i)
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else
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else
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wb_ack_o_r <= 0;
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wb_ack_o_r <= 0;
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//
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//
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// Error signal generation
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// Error signal generation
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//
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//
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// Error when out of bounds of memory - skip top byte of address in case
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// Error when out of bounds of memory - skip top byte of address in case
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// this is mapped somewhere other than 0x00.
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// this is mapped somewhere other than 0x00.
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assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
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assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
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// OR in other errors here...
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// OR in other errors here...
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assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
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assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
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`ifdef verilator
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task do_readmemh;
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// verilator public
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$readmemh(memory_file, mem);
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endtask // do_readmemh
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`else
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initial
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begin
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$readmemh(memory_file, mem);
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end
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`endif // !`ifdef verilator
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//
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//
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// Access functions
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// Access functions
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//
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//
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// Function to access RAM (for use by Verilator).
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// Function to access RAM (for use by Verilator).
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function [31:0] get_mem;
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function [31:0] get_mem32;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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get_mem = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
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get_mem32 = mem[addr];
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endfunction // get_mem
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endfunction // get_mem32
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// Function to access RAM (for use by Verilator).
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// Function to access RAM (for use by Verilator).
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function [7:0] get_byte;
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function [7:0] get_mem8;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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reg [31:0] temp_word;
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reg [31:0] temp_word;
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begin
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begin
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temp_word = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
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temp_word = mem[{addr[aw-1:2],2'd0}];
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// Big endian mapping.
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// Big endian mapping.
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get_byte = (addr[1:0]==2'b00) ? temp_word[31:24] :
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get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
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(addr[1:0]==2'b01) ? temp_word[23:16] :
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(addr[1:0]==2'b01) ? temp_word[23:16] :
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(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
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(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
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end
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end
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endfunction // get_mem
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endfunction // get_mem8
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// Function to write RAM (for use by Verilator).
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// Function to write RAM (for use by Verilator).
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function set_mem;
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function set_mem32;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [aw-1:0] addr;
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input [dw-1:0] data;
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input [dw-1:0] data;
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mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]] = data;
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mem[addr] = data;
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endfunction // set_mem
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endfunction // set_mem32
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endmodule // ram_wb_b3
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endmodule // ram_wb_b3
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