# Paths to RTL and testbench directories for board ports.
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# Paths to RTL and testbench directories for board ports.
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COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
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COMMON_RTL_DIR = $(PROJECT_ROOT)/rtl
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COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
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COMMON_RTL_VERILOG_DIR = $(COMMON_RTL_DIR)/verilog
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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#COMMON_RTL_VHDL_DIR = $(COMMON_RTL_DIR)/vhdl
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BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
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BOARD_RTL_DIR=$(BOARD_ROOT)/rtl
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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BOARD_RTL_VERILOG_DIR=$(BOARD_RTL_DIR)/verilog
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#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
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#BOARD_RTL_VHDL_DIR = $(BOARD_RTL_DIR)/vhdl
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BOARD_EXT_MODULES_DIR=$(BOARD_ROOT)/modules
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# Only 1 include path for board builds - their own!
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# Only 1 include path for board builds - their own!
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_RTL_VERILOG_INCLUDE_DIR=$(BOARD_RTL_VERILOG_DIR)/include
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BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
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BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
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BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
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BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
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BOARD_BENCH_VERILOG_INCLUDE_DIR=$(BOARD_BENCH_VERILOG_DIR)/include
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BOARD_BENCH_VERILOG_INCLUDE_DIR=$(BOARD_BENCH_VERILOG_DIR)/include
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COMMON_BENCH_DIR=$(PROJECT_ROOT)
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COMMON_BENCH_DIR=$(PROJECT_ROOT)
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COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
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COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
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COMMON_BENCH_VERILOG_INCLUDE_DIR=$(COMMON_BENCH_VERILOG_DIR)/include
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COMMON_BENCH_VERILOG_INCLUDE_DIR=$(COMMON_BENCH_VERILOG_DIR)/include
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# Simulation directories
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# Simulation directories
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SIM_DIR ?=$(BOARD_ROOT)/sim
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SIM_DIR ?=$(BOARD_ROOT)/sim
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
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RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
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RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
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RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
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RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
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RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
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# Testbench paths
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# Testbench paths
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BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
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BOARD_BENCH_DIR=$(BOARD_ROOT)/bench
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BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
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BOARD_BENCH_VERILOG_DIR=$(BOARD_BENCH_DIR)/verilog
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COMMON_BENCH_DIR=$(PROJECT_ROOT)/bench
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COMMON_BENCH_DIR=$(PROJECT_ROOT)/bench
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COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
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COMMON_BENCH_VERILOG_DIR=$(COMMON_BENCH_DIR)/verilog
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#COMMON_BENCH_VHDL_DIR=$(COMMON_BENCH_DIR)/vhdl
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#COMMON_BENCH_VHDL_DIR=$(COMMON_BENCH_DIR)/vhdl
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#BOARD_BENCH_VHDL_DIR=$(BOARD_BENCH_DIR)/vhdl
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#BOARD_BENCH_VHDL_DIR=$(BOARD_BENCH_DIR)/vhdl
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COMMON_BENCH_SYSC_DIR=$(COMMON_BENCH_DIR)/sysc
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COMMON_BENCH_SYSC_DIR=$(COMMON_BENCH_DIR)/sysc
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COMMON_BENCH_SYSC_SRC_DIR=$(COMMON_BENCH_SYSC_DIR)/src
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COMMON_BENCH_SYSC_SRC_DIR=$(COMMON_BENCH_SYSC_DIR)/src
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COMMON_BENCH_SYSC_INCLUDE_DIR=$(COMMON_BENCH_SYSC_DIR)/include
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COMMON_BENCH_SYSC_INCLUDE_DIR=$(COMMON_BENCH_SYSC_DIR)/include
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# Software directories
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# Software directories
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COMMON_SW_DIR=$(PROJECT_ROOT)/sw
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COMMON_SW_DIR=$(PROJECT_ROOT)/sw
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BOARD_SW_DIR=$(BOARD_ROOT)/sw
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BOARD_SW_DIR=$(BOARD_ROOT)/sw
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# Synthesis directory for board
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# Synthesis directory for board
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BOARD_SYN_DIR=$(BOARD_ROOT)/syn/$(SYNTHESIS_TOOL)
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BOARD_SYN_DIR=$(BOARD_ROOT)/syn/$(SYNTHESIS_TOOL)
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BOARD_SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
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BOARD_SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
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BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
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BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
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