######################################################################
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######################################################################
|
#### ####
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#### ####
|
#### ORPSoCv2 Testbenches Makefile ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ####
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#### ####
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#### Description ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
|
#### ORPSoCv2 Testbenches Makefile, containing rules for ####
|
#### configuring and running different tests on the current ####
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#### configuring and running different tests on the current ####
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#### ORPSoC(v2) design. ####
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#### ORPSoC(v2) design. ####
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#### ####
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#### ####
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#### To do: ####
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#### To do: ####
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#### ####
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#### ####
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#### Author(s): ####
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#### Author(s): ####
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#### - Julius Baxter, julius@opencores.org ####
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#### - Julius Baxter, julius@opencores.org ####
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#### ####
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#### ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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#### ####
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#### ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG ####
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#### ####
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#### ####
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#### This source file may be used and distributed without ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### later version. ####
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#### ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
|
#### details. ####
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#### ####
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#### ####
|
#### You should have received a copy of the GNU Lesser General ####
|
#### You should have received a copy of the GNU Lesser General ####
|
#### Public License along with this source; if not, download it ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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#### ####
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######################################################################
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######################################################################
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# Name of the directory we're currently in
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# Name of the directory we're currently in
|
CUR_DIR=$(shell pwd)
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CUR_DIR=$(shell pwd)
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|
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# The root path of the whole project
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# The root path of the whole project
|
PROJECT_ROOT ?=$(CUR_DIR)/../..
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PROJECT_ROOT ?=$(CUR_DIR)/../..
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|
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DESIGN_NAME=orpsoc
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DESIGN_NAME=orpsoc
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RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
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RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
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# Top level files for DUT and testbench
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# Top level files for DUT and testbench
|
DUT_TOP=$(RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
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DUT_TOP=$(RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
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BENCH_TOP=$(BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
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BENCH_TOP=$(BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
|
|
|
# Need this for individual test variables to not break
|
# Need this for individual test variables to not break
|
TEST ?= or1200-simple
|
TEST ?= or1200-simple
|
|
|
TESTS ?= or1200-simple \
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TESTS ?= or1200-simple \
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or1200-basic \
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or1200-basic \
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or1200-cbasic \
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or1200-cbasic \
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or1200-dctest \
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or1200-dctest \
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or1200-float \
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or1200-float \
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or1200-mmu \
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or1200-mmu \
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or1200-except \
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or1200-except \
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or1200-mac \
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or1200-mac \
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or1200-ext \
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or1200-ext \
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or1200-cy \
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or1200-cy \
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or1200-ov \
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or1200-ov \
|
|
or1200-sf \
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or1200-ffl1 \
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or1200-ffl1 \
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or1200-linkregtest \
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or1200-linkregtest \
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or1200-tick \
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or1200-tick \
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or1200-ticksyscall \
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or1200-ticksyscall \
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uart-simple
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uart-simple
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|
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# Gets turned into verilog `define
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# Gets turned into verilog `define
|
SIM_TYPE=RTL
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SIM_TYPE=RTL
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|
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# Paths to other important parts of this test suite
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# Paths to other important parts of this test suite
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RTL_DIR = $(PROJECT_ROOT)/rtl
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RTL_DIR = $(PROJECT_ROOT)/rtl
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RTL_VERILOG_DIR = $(RTL_DIR)/verilog
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RTL_VERILOG_DIR = $(RTL_DIR)/verilog
|
RTL_VERILOG_INCLUDE_DIR = $(RTL_VERILOG_DIR)/include
|
RTL_VERILOG_INCLUDE_DIR = $(RTL_VERILOG_DIR)/include
|
#RTL_VHDL_DIR = $(RTL_DIR)/vhdl
|
#RTL_VHDL_DIR = $(RTL_DIR)/vhdl
|
|
|
PROJECT_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
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PROJECT_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
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# Detect technology to use for the simulation
|
# Detect technology to use for the simulation
|
DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | \
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DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | \
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sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | \
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sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | \
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awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | \
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awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | \
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grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
|
grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
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|
|
# Rule to look at what defines are being extracted from main file
|
# Rule to look at what defines are being extracted from main file
|
print-defines:
|
print-defines:
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@echo echo; echo "\t### Design defines ###"; echo
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@echo echo; echo "\t### Design defines ###"; echo
|
@echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
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@echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
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@echo $(DESIGN_DEFINES)
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@echo $(DESIGN_DEFINES)
|
|
|
# Simulation directories
|
# Simulation directories
|
SIM_DIR ?=$(PROJECT_ROOT)/sim
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SIM_DIR ?=$(PROJECT_ROOT)/sim
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SIM_VLT_DIR ?=$(SIM_DIR)/vlt
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SIM_VLT_DIR ?=$(SIM_DIR)/vlt
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_DIR=$(SIM_DIR)
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RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
|
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
|
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
|
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
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RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
|
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
|
|
|
# Testbench paths
|
# Testbench paths
|
BENCH_DIR=$(PROJECT_ROOT)/bench
|
BENCH_DIR=$(PROJECT_ROOT)/bench
|
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
|
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
|
BENCH_VERILOG_INCLUDE_DIR=$(BENCH_VERILOG_DIR)/include
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BENCH_VERILOG_INCLUDE_DIR=$(BENCH_VERILOG_DIR)/include
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#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl
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#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl
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BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
|
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
|
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
|
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
|
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
|
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
|
|
|
|
|
# System software dir
|
# System software dir
|
SW_DIR=$(PROJECT_ROOT)/sw
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SW_DIR=$(PROJECT_ROOT)/sw
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# BootROM code, which generates a verilog array select values
|
# BootROM code, which generates a verilog array select values
|
BOOTROM_FILE=bootrom.v
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BOOTROM_FILE=bootrom.v
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BOOTROM_SW_DIR=$(SW_DIR)/bootrom
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BOOTROM_SW_DIR=$(SW_DIR)/bootrom
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BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
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BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
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BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
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BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
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$(BOOTROM_VERILOG): $(BOOTROM_SRC)
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$(BOOTROM_VERILOG): $(BOOTROM_SRC)
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$(Q)echo; echo "\t### Generating bootup ROM ###"; echo
|
$(Q)echo; echo "\t### Generating bootup ROM ###"; echo
|
$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
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$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
|
|
|
# Suffix of file to check after each test for the string
|
# Suffix of file to check after each test for the string
|
TEST_OUT_FILE_SUFFIX=-general.log
|
TEST_OUT_FILE_SUFFIX=-general.log
|
TEST_OK_STRING=8000000d
|
TEST_OK_STRING=8000000d
|
|
|
# Dynamically generated verilog file defining configuration for various things
|
# Dynamically generated verilog file defining configuration for various things
|
TEST_DEFINES_VLG=test-defines.v
|
TEST_DEFINES_VLG=test-defines.v
|
# Set V=1 when calling make to enable verbose output
|
# Set V=1 when calling make to enable verbose output
|
# mainly for debugging purposes.
|
# mainly for debugging purposes.
|
ifeq ($(V), 1)
|
ifeq ($(V), 1)
|
Q=
|
Q=
|
QUIET=
|
QUIET=
|
else
|
else
|
Q ?=@
|
Q ?=@
|
QUIET=-quiet
|
QUIET=-quiet
|
endif
|
endif
|
|
|
# Modelsim variables
|
# Modelsim variables
|
MGC_VSIM=vsim
|
MGC_VSIM=vsim
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MGC_VLOG_COMP=vlog
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MGC_VLOG_COMP=vlog
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MGC_VHDL_COMP=vcom
|
MGC_VHDL_COMP=vcom
|
MODELSIM=modelsim
|
MODELSIM=modelsim
|
|
|
# Icarus variables
|
# Icarus variables
|
ICARUS_COMPILE=iverilog
|
ICARUS_COMPILE=iverilog
|
ICARUS_RUN=vvp
|
ICARUS_RUN=vvp
|
ICARUS_SCRIPT=icarus.scr
|
ICARUS_SCRIPT=icarus.scr
|
ICARUS_SIM_EXE=vlogsim.elf
|
ICARUS_SIM_EXE=vlogsim.elf
|
ICARUS=icarus
|
ICARUS=icarus
|
|
|
#Default simulator is Icarus Verilog
|
#Default simulator is Icarus Verilog
|
# Set SIMULATOR=modelsim to use Modelsim
|
# Set SIMULATOR=modelsim to use Modelsim
|
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog - TODO
|
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog - TODO
|
# Set SIMULATOR=icarus to use Icarus Verilog (Default)
|
# Set SIMULATOR=icarus to use Icarus Verilog (Default)
|
|
|
SIMULATOR ?= $(ICARUS)
|
SIMULATOR ?= $(ICARUS)
|
|
|
# VPI debugging interface variables
|
# VPI debugging interface variables
|
VPI_SRC_C_DIR=$(BENCH_VERILOG_DIR)/vpi/c
|
VPI_SRC_C_DIR=$(BENCH_VERILOG_DIR)/vpi/c
|
VPI_SRC_VERILOG_DIR=$(BENCH_VERILOG_DIR)/vpi/verilog
|
VPI_SRC_VERILOG_DIR=$(BENCH_VERILOG_DIR)/vpi/verilog
|
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
|
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
|
|
|
# Modelsim VPI compile variables
|
# Modelsim VPI compile variables
|
MODELTECH_VPILIB=msim_jp_vpi.sl
|
MODELTECH_VPILIB=msim_jp_vpi.sl
|
# Icarus VPI compile target
|
# Icarus VPI compile target
|
ICARUS_VPILIB=jp_vpi
|
ICARUS_VPILIB=jp_vpi
|
|
|
#
|
#
|
# Modelsim-specific settings
|
# Modelsim-specific settings
|
#
|
#
|
VOPT_ARGS=$(QUIET) -suppress 2241
|
VOPT_ARGS=$(QUIET) -suppress 2241
|
# If VCD dump is desired, tell Modelsim not to optimise
|
# If VCD dump is desired, tell Modelsim not to optimise
|
# away everything.
|
# away everything.
|
ifeq ($(VCD), 1)
|
ifeq ($(VCD), 1)
|
# If certain versions of modelsim don't have the vopt executable, define
|
# If certain versions of modelsim don't have the vopt executable, define
|
# MGC_NO_VOPT=1 when running.
|
# MGC_NO_VOPT=1 when running.
|
ifeq ($(MGC_NO_VOPT), 1)
|
ifeq ($(MGC_NO_VOPT), 1)
|
MGC_VSIM_ARGS +=-voptargs="+acc=rnp"
|
MGC_VSIM_ARGS +=-voptargs="+acc=rnp"
|
MGC_VOPT_CMD=echo
|
MGC_VOPT_CMD=echo
|
MGC_VSIM_TGT=orpsoc_testbench
|
MGC_VSIM_TGT=orpsoc_testbench
|
else
|
else
|
VOPT_ARGS=+acc=rnpqv
|
VOPT_ARGS=+acc=rnpqv
|
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
|
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
|
MGC_VSIM_TGT=tb
|
MGC_VSIM_TGT=tb
|
endif
|
endif
|
|
|
else
|
else
|
|
|
ifeq ($(MGC_NO_VOPT), 1)
|
ifeq ($(MGC_NO_VOPT), 1)
|
MGC_VSIM_ARGS += -vopt
|
MGC_VSIM_ARGS += -vopt
|
MGC_VOPT_CMD=echo
|
MGC_VOPT_CMD=echo
|
MGC_VSIM_TGT=orpsoc_testbench
|
MGC_VSIM_TGT=orpsoc_testbench
|
else
|
else
|
VOPT_ARGS=+acc=rnpqv
|
VOPT_ARGS=+acc=rnpqv
|
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
|
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
|
MGC_VSIM_TGT=tb
|
MGC_VSIM_TGT=tb
|
endif
|
endif
|
|
|
|
|
endif
|
endif
|
# VSIM commands
|
# VSIM commands
|
# Suppressed warnings - 3009: Failed to open $readmemh() file
|
# Suppressed warnings - 3009: Failed to open $readmemh() file
|
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
|
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
|
# directive in effect, but previous modules do.
|
# directive in effect, but previous modules do.
|
# Suppressed warnings - 8598: Non-positive replication multiplier inside
|
# Suppressed warnings - 8598: Non-positive replication multiplier inside
|
# concat. Replication will be ignored
|
# concat. Replication will be ignored
|
MGC_VSIM_ARGS += -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
|
MGC_VSIM_ARGS += -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
|
-do "set StdArithNoWarnings 1; run -all; exit"
|
-do "set StdArithNoWarnings 1; run -all; exit"
|
# Options required when VPI option used
|
# Options required when VPI option used
|
ifeq ($(VPI), 1)
|
ifeq ($(VPI), 1)
|
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
|
|
|
ICARUS_VPI_LIB=$(VPI_SRC_C_DIR)/$(ICARUS_VPILIB)
|
ICARUS_VPI_LIB=$(VPI_SRC_C_DIR)/$(ICARUS_VPILIB)
|
ICARUS_VPI_ARGS=-M$(VPI_SRC_C_DIR) -m$(ICARUS_VPILIB)
|
ICARUS_VPI_ARGS=-M$(VPI_SRC_C_DIR) -m$(ICARUS_VPILIB)
|
endif
|
endif
|
# Rule to make the VPI library for Modelsim
|
# Rule to make the VPI library for Modelsim
|
$(MGC_VPI_LIB): $(VPI_SRCS)
|
$(MGC_VPI_LIB): $(VPI_SRCS)
|
$(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
|
$(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
|
|
|
# Rule to make VPI library for Icarus Verilog
|
# Rule to make VPI library for Icarus Verilog
|
$(ICARUS_VPI_LIB): $(VPI_SRCS)
|
$(ICARUS_VPI_LIB): $(VPI_SRCS)
|
$(MAKE) -C $(VPI_SRC_C_DIR) $(ICARUS_VPILIB)
|
$(MAKE) -C $(VPI_SRC_C_DIR) $(ICARUS_VPILIB)
|
|
|
# Manually add the VPI bench verilog path
|
# Manually add the VPI bench verilog path
|
BENCH_VERILOG_SRC_SUBDIRS += $(VPI_SRC_VERILOG_DIR)
|
BENCH_VERILOG_SRC_SUBDIRS += $(VPI_SRC_VERILOG_DIR)
|
|
|
#
|
#
|
# Verilog DUT source variables
|
# Verilog DUT source variables
|
#
|
#
|
# A list of paths under rtl/verilog we wish to exclude for module searching
|
# A list of paths under rtl/verilog we wish to exclude for module searching
|
VERILOG_MODULES_EXCLUDE= include components
|
VERILOG_MODULES_EXCLUDE= include components
|
VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in \
|
VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in \
|
$(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
|
$(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
|
RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v \
|
RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v \
|
$(VERILOG_MODULES_EXCLUDE_LIST_E) )
|
$(VERILOG_MODULES_EXCLUDE_LIST_E) )
|
# Specific files to exclude, currently none.
|
# Specific files to exclude, currently none.
|
#VERILOG_EXCLUDE=
|
#VERILOG_EXCLUDE=
|
#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); \
|
#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); \
|
do echo "-e $$exclude"; done)
|
do echo "-e $$exclude"; done)
|
# List of verilog source files, minus excluded files
|
# List of verilog source files, minus excluded files
|
#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
|
#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v \
|
ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v \
|
$(VERILOG_EXCLUDE_LIST_E); \
|
$(VERILOG_EXCLUDE_LIST_E); \
|
fi; done)
|
fi; done)
|
# List of verilog source files, ignoring excludes
|
# List of verilog source files, ignoring excludes
|
RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
|
RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
ls $(RTL_VERILOG_DIR)/$$module/*.v; \
|
ls $(RTL_VERILOG_DIR)/$$module/*.v; \
|
fi; done)
|
fi; done)
|
|
|
# List of verilog includes
|
# List of verilog includes
|
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
|
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
|
|
|
print-verilog-src:
|
print-verilog-src:
|
@echo echo; echo "\t### Verilog source ###"; echo
|
@echo echo; echo "\t### Verilog source ###"; echo
|
@echo $(RTL_VERILOG_SRC)
|
@echo $(RTL_VERILOG_SRC)
|
|
|
# Rules to make RTL we might need
|
# Rules to make RTL we might need
|
# Expects modules, if they need making, to have their top verilog file to
|
# Expects modules, if they need making, to have their top verilog file to
|
# correspond to their module name, and the directory should have a make file
|
# correspond to their module name, and the directory should have a make file
|
# and rule which works for this command.
|
# and rule which works for this command.
|
# Add name of module to this list, currently only does verilog ones.
|
# Add name of module to this list, currently only does verilog ones.
|
# Rule 'rtl' is called just before generating DUT modelsim compilation script
|
# Rule 'rtl' is called just before generating DUT modelsim compilation script
|
RTL_TO_CHECK=
|
RTL_TO_CHECK=
|
rtl:
|
rtl:
|
$(Q)for module in $(RTL_TO_CHECK); do \
|
$(Q)for module in $(RTL_TO_CHECK); do \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module $$module.v; \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module $$module.v; \
|
done
|
done
|
|
|
#
|
#
|
# VHDL DUT source variables
|
# VHDL DUT source variables
|
#
|
#
|
# VHDL modules
|
# VHDL modules
|
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
|
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
|
# VHDL sources
|
# VHDL sources
|
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do \
|
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do \
|
if [ -d $(RTL_VHDL_DIR)/$$module ]; then \
|
if [ -d $(RTL_VHDL_DIR)/$$module ]; then \
|
ls $(RTL_VHDL_DIR)/$$module/*.vhd; \
|
ls $(RTL_VHDL_DIR)/$$module/*.vhd; \
|
fi; done)
|
fi; done)
|
#print-vhdl-src:
|
#print-vhdl-src:
|
# @echo echo; echo "\t### VHDL modules and source ###"; echo
|
# @echo echo; echo "\t### VHDL modules and source ###"; echo
|
# @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
|
# @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
|
# @echo "source: "$(RTL_VHDL_SRC)
|
# @echo "source: "$(RTL_VHDL_SRC)
|
|
|
|
|
# Testbench verilog source
|
# Testbench verilog source
|
BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v \
|
BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v \
|
$(DESIGN_NAME)_testbench )
|
$(DESIGN_NAME)_testbench )
|
|
|
print-bench-src:
|
print-bench-src:
|
$(Q)echo "\tBench verilog source"; \
|
$(Q)echo "\tBench verilog source"; \
|
echo $(BENCH_VERILOG_SRC)
|
echo $(BENCH_VERILOG_SRC)
|
|
|
# Testbench source subdirectory detection
|
# Testbench source subdirectory detection
|
BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do \
|
BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do \
|
if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then \
|
if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then \
|
echo $(BENCH_VERILOG_DIR)/$$file; \
|
echo $(BENCH_VERILOG_DIR)/$$file; \
|
fi; done)
|
fi; done)
|
|
|
# Compile script generation rules:
|
# Compile script generation rules:
|
|
|
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
$(BOOTROM_VERILOG)
|
$(BOOTROM_VERILOG)
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
fi; done
|
fi; done
|
$(Q)echo >> $@
|
$(Q)echo >> $@
|
|
|
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
|
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
echo "+incdir+"$$path >> $@; \
|
echo "+incdir+"$$path >> $@; \
|
done
|
done
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
echo "-y "$$path >> $@; \
|
echo "-y "$$path >> $@; \
|
done
|
done
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)echo "+libext+.v" >> $@;
|
$(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
|
$(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
|
$(Q)echo >> $@
|
$(Q)echo >> $@
|
|
|
# Compile DUT into "work" library
|
# Compile DUT into "work" library
|
work: modelsim_dut.scr #$(RTL_VHDL_SRC)
|
work: modelsim_dut.scr #$(RTL_VHDL_SRC)
|
$(Q)if [ ! -e $@ ]; then vlib $@; fi
|
$(Q)if [ ! -e $@ ]; then vlib $@; fi
|
# $(Q)echo; echo "\t### Compiling VHDL design library ###"; echo
|
# $(Q)echo; echo "\t### Compiling VHDL design library ###"; echo
|
# $(Q)vcom -93 $(QUIET) $(RTL_VHDL_SRC)
|
# $(Q)vcom -93 $(QUIET) $(RTL_VHDL_SRC)
|
$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
|
$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
|
$(Q)vlog $(QUIET) -f $< $(DUT_TOP)
|
$(Q)vlog $(QUIET) -f $< $(DUT_TOP)
|
|
|
# Single compile rule
|
# Single compile rule
|
.PHONY : $(MODELSIM)
|
.PHONY : $(MODELSIM)
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work
|
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
$(Q)echo; echo "\t### Compiling testbench ###"; echo
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
|
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
|
$(Q)$(MGC_VOPT_CMD)
|
$(Q)$(MGC_VOPT_CMD)
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)vsim $(VOPT_ARGS) $(MGC_VSIM_ARGS) $(MGC_VSIM_TGT)
|
$(Q)vsim $(VOPT_ARGS) $(MGC_VSIM_ARGS) $(MGC_VSIM_TGT)
|
|
|
#
|
#
|
# Icarus Verilog simulator build and run rules
|
# Icarus Verilog simulator build and run rules
|
#
|
#
|
.PHONY: $(ICARUS_SCRIPT)
|
.PHONY: $(ICARUS_SCRIPT)
|
$(ICARUS_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
$(ICARUS_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
$(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
|
$(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
|
$(Q)echo "# Icarus Verilog simulation script" > $@
|
$(Q)echo "# Icarus Verilog simulation script" > $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
echo "+incdir+"$$path >> $@; \
|
echo "+incdir+"$$path >> $@; \
|
done
|
done
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
$(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
|
echo "-y "$$path >> $@; \
|
echo "-y "$$path >> $@; \
|
done
|
done
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
done
|
done
|
$(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
|
$(Q)echo $(BENCH_TOP) >> $@;
|
$(Q)echo $(BENCH_TOP) >> $@;
|
$(Q) echo >> $@
|
$(Q) echo >> $@
|
|
|
# Icarus design compilation rule
|
# Icarus design compilation rule
|
$(ICARUS_SIM_EXE): $(ICARUS_SCRIPT) $(TEST_DEFINES_VLG)
|
$(ICARUS_SIM_EXE): $(ICARUS_SCRIPT) $(TEST_DEFINES_VLG)
|
$(Q)echo; echo "\t### Compiling ###"; echo
|
$(Q)echo; echo "\t### Compiling ###"; echo
|
$(Q) $(ICARUS_COMPILE) -s$(RTL_TESTBENCH_TOP) -c $< -o $@
|
$(Q) $(ICARUS_COMPILE) -s$(RTL_TESTBENCH_TOP) -c $< -o $@
|
|
|
# Icarus simulation run rule
|
# Icarus simulation run rule
|
$(ICARUS): $(ICARUS_SIM_EXE) $(ICARUS_VPI_LIB)
|
$(ICARUS): $(ICARUS_SIM_EXE) $(ICARUS_VPI_LIB)
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q) $(ICARUS_RUN) $(ICARUS_VPI_ARGS) -l ../out/$(ICARUS_RUN).log $<
|
$(Q) $(ICARUS_RUN) $(ICARUS_VPI_ARGS) -l ../out/$(ICARUS_RUN).log $<
|
|
|
|
|
|
|
.PHONY: rtl-test
|
.PHONY: rtl-test
|
rtl-test: clean-sim-test-sw sw-vmem clean-test-defines $(TEST_DEFINES_VLG) \
|
rtl-test: clean-sim-test-sw sw-vmem clean-test-defines $(TEST_DEFINES_VLG) \
|
$(SIMULATOR)
|
$(SIMULATOR)
|
|
|
# Run an RTL test followed by checking of generated results
|
# Run an RTL test followed by checking of generated results
|
rtl-test-with-check: rtl-test
|
rtl-test-with-check: rtl-test
|
$(Q)$(MAKE) check-test-log; \
|
$(Q)$(MAKE) check-test-log; \
|
if [ $$? -ne 0 ]; then \
|
if [ $$? -ne 0 ]; then \
|
echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \
|
echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \
|
else \
|
else \
|
echo; echo "\t### "$(TEST)" test OK ###"; echo; \
|
echo; echo "\t### "$(TEST)" test OK ###"; echo; \
|
fi
|
fi
|
|
|
# Do check, don't print anything out
|
# Do check, don't print anything out
|
rtl-test-with-check-no-print: rtl-test check-test-log
|
rtl-test-with-check-no-print: rtl-test check-test-log
|
|
|
# Main RTL test loop
|
# Main RTL test loop
|
rtl-tests:
|
rtl-tests:
|
$(Q)for test in $(TESTS); do \
|
$(Q)for test in $(TESTS); do \
|
export TEST=$$test; \
|
export TEST=$$test; \
|
$(MAKE) rtl-test-with-check-no-print; \
|
$(MAKE) rtl-test-with-check-no-print; \
|
if [ $$? -ne 0 ]; then break; fi; \
|
if [ $$? -ne 0 ]; then break; fi; \
|
echo; echo "\t### $$test test OK ###"; echo; \
|
echo; echo "\t### $$test test OK ###"; echo; \
|
done
|
done
|
|
|
|
|
.PHONY: check-test-log
|
.PHONY: check-test-log
|
check-test-log:
|
check-test-log:
|
$(Q)echo "#!/bin/bash" > $@
|
$(Q)echo "#!/bin/bash" > $@
|
$(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@
|
$(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@
|
$(Q)echo "check-test-log" >> $@
|
$(Q)echo "check-test-log" >> $@
|
$(Q)chmod +x $@
|
$(Q)chmod +x $@
|
$(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo;
|
$(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo;
|
$(Q)./$@
|
$(Q)./$@
|
|
|
# Include the test-defines.v generation rule
|
# Include the test-defines.v generation rule
|
include ../bin/definesgen.inc
|
include ../bin/definesgen.inc
|
|
|
#
|
#
|
# Software make rules (called recursively)
|
# Software make rules (called recursively)
|
#
|
#
|
|
|
# Path for the current test
|
# Path for the current test
|
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
|
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
|
|
|
# This file name corresponds to the VMEM file the RAM models will attempt to
|
# This file name corresponds to the VMEM file the RAM models will attempt to
|
# load via $readmemh().
|
# load via $readmemh().
|
SIM_DIR_VMEM_IMAGE ?=sram.vmem
|
SIM_DIR_VMEM_IMAGE ?=sram.vmem
|
|
|
ifeq ($(USER_ELF),)
|
ifeq ($(USER_ELF),)
|
ELF_FILE=$(TEST_SW_DIR)/$(TEST).elf
|
ELF_FILE=$(TEST_SW_DIR)/$(TEST).elf
|
else
|
else
|
ELF_FILE=$(USER_ELF)
|
ELF_FILE=$(USER_ELF)
|
ELF_FILE_NOTDIR=$(notdir $(USER_ELF))
|
ELF_FILE_NOTDIR=$(notdir $(USER_ELF))
|
ELF_FILE_NOTDIR_BASENAME=$(basename $(ELF_FILE_NOTDIR))
|
ELF_FILE_NOTDIR_BASENAME=$(basename $(ELF_FILE_NOTDIR))
|
endif
|
endif
|
|
|
# Rules allowing user to specify a pre-existing VMEM file to load into the
|
# Rules allowing user to specify a pre-existing VMEM file to load into the
|
# simulation, instead of compiling a test.
|
# simulation, instead of compiling a test.
|
ifeq ($(USER_VMEM),)
|
ifeq ($(USER_VMEM),)
|
VMEM_FILE=$(TEST_SW_DIR)/$(TEST).vmem
|
VMEM_FILE=$(TEST_SW_DIR)/$(TEST).vmem
|
.PHONY: $(VMEM_FILE)
|
.PHONY: $(VMEM_FILE)
|
|
|
|
|
# If USER_ELF was specified, then we need a slightly different way of
|
# If USER_ELF was specified, then we need a slightly different way of
|
# generating the VMEM file from it than a usual test
|
# generating the VMEM file from it than a usual test
|
ifeq ($(USER_ELF),)
|
ifeq ($(USER_ELF),)
|
$(SIM_DIR_VMEM_IMAGE): $(VMEM_FILE)
|
$(SIM_DIR_VMEM_IMAGE): $(VMEM_FILE)
|
$(Q)if [ -L $@ ]; then unlink $@; fi
|
$(Q)if [ -L $@ ]; then unlink $@; fi
|
$(Q)if [ -e $@ ]; then rm $@; fi
|
$(Q)if [ -e $@ ]; then rm $@; fi
|
$(Q)ln -s $< $@
|
$(Q)ln -s $< $@
|
else
|
else
|
$(SIM_DIR_VMEM_IMAGE): $(USER_ELF)
|
$(SIM_DIR_VMEM_IMAGE): $(USER_ELF)
|
$(Q)$(MAKE) -C $(SW_DIR)/lib \
|
$(Q)$(MAKE) -C $(SW_DIR)/lib \
|
USER_ELF_BIN=`pwd`/$(ELF_FILE_NOTDIR_BASENAME).bin \
|
USER_ELF_BIN=`pwd`/$(ELF_FILE_NOTDIR_BASENAME).bin \
|
USER_ELF_VMEM=`pwd`/$(ELF_FILE_NOTDIR_BASENAME).vmem \
|
USER_ELF_VMEM=`pwd`/$(ELF_FILE_NOTDIR_BASENAME).vmem \
|
gen-user-elf-vmem
|
gen-user-elf-vmem
|
$(Q)cp -v $(ELF_FILE_NOTDIR_BASENAME).vmem $@
|
$(Q)cp -v $(ELF_FILE_NOTDIR_BASENAME).vmem $@
|
|
|
TEST=$(ELF_FILE_NOTDIR_BASENAME)
|
TEST=$(ELF_FILE_NOTDIR_BASENAME)
|
endif
|
endif
|
|
|
else
|
else
|
VMEM_FILE=$(USER_VMEM)
|
VMEM_FILE=$(USER_VMEM)
|
USER_VMEM_NOTDIR=$(notdir $(USER_VMEM))
|
USER_VMEM_NOTDIR=$(notdir $(USER_VMEM))
|
TEST=$(basename $(USER_VMEM_NOTDIR))
|
TEST=$(basename $(USER_VMEM_NOTDIR))
|
|
|
$(SIM_DIR_VMEM_IMAGE): $(VMEM_FILE)
|
$(SIM_DIR_VMEM_IMAGE): $(VMEM_FILE)
|
cp -v $< $@
|
cp -v $< $@
|
|
|
endif
|
endif
|
|
|
|
|
|
|
|
|
.PHONY : sw-vmem sw-elf
|
.PHONY : sw-vmem sw-elf
|
sw-vmem: $(SIM_DIR_VMEM_IMAGE)
|
sw-vmem: $(SIM_DIR_VMEM_IMAGE)
|
|
|
$(TEST_SW_DIR)/$(TEST).vmem:
|
$(TEST_SW_DIR)/$(TEST).vmem:
|
$(Q) echo; echo "\t### Compiling software ###"; echo;
|
$(Q) echo; echo "\t### Compiling software ###"; echo;
|
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
|
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
|
|
|
# Compile ELF and copy it here
|
# Compile ELF and copy it here
|
sw-elf: $(ELF_FILE)
|
sw-elf: $(ELF_FILE)
|
$(Q)cp -v $< .
|
$(Q)cp -v $< .
|
|
|
$(TEST_SW_DIR)/$(TEST).elf:
|
$(TEST_SW_DIR)/$(TEST).elf:
|
$(Q) echo; echo "\t### Compiling software ###"; echo;
|
$(Q) echo; echo "\t### Compiling software ###"; echo;
|
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).elf
|
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).elf
|
|
|
|
|
# Rule to force generation of the processed orpsoc-defines.h file
|
# Rule to force generation of the processed orpsoc-defines.h file
|
processed-verilog-headers-in-c-for-vlt:
|
processed-verilog-headers-in-c-for-vlt:
|
$(Q)$(MAKE) -C $(SW_DIR)/lib processed-verilog-headers
|
$(Q)$(MAKE) -C $(SW_DIR)/lib processed-verilog-headers
|
# Now copy the file into the Verilated model build path
|
# Now copy the file into the Verilated model build path
|
$(Q)cp $(SW_DIR)/lib/include/orpsoc-defines.h $(SIM_VLT_DIR)
|
$(Q)cp $(SW_DIR)/lib/include/orpsoc-defines.h $(SIM_VLT_DIR)
|
|
|
# Create test software disassembly
|
# Create test software disassembly
|
|
|
sw-dis: $(TEST_SW_DIR)/$(TEST).dis
|
sw-dis: $(TEST_SW_DIR)/$(TEST).dis
|
$(Q)cp -v $< .
|
$(Q)cp -v $< .
|
|
|
$(TEST_SW_DIR)/$(TEST).dis:
|
$(TEST_SW_DIR)/$(TEST).dis:
|
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).dis
|
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).dis
|
|
|
|
|
#
|
#
|
# Cleaning rules
|
# Cleaning rules
|
#
|
#
|
clean: clean-sim clean-sim-test-sw clean-bootrom clean-vlt clean-out clean-sw
|
clean: clean-sim clean-sim-test-sw clean-bootrom clean-vlt clean-out clean-sw
|
|
|
clean-sim:
|
clean-sim:
|
$(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo;
|
$(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo;
|
$(Q)rm -rf *.* lib_* work transcript check-test-log
|
$(Q)rm -rf *.* lib_* work transcript check-test-log
|
$(Q) if [ -e $(VPI_SRC_C_DIR) ]; then \
|
$(Q) if [ -e $(VPI_SRC_C_DIR) ]; then \
|
$(MAKE) -C $(VPI_SRC_C_DIR) clean; \
|
$(MAKE) -C $(VPI_SRC_C_DIR) clean; \
|
fi
|
fi
|
|
|
clean-bootrom:
|
clean-bootrom:
|
$(MAKE) -C $(BOOTROM_SW_DIR) clean
|
$(MAKE) -C $(BOOTROM_SW_DIR) clean
|
|
|
clean-out:
|
clean-out:
|
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
$(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
|
|
|
# Clean away verilator build path and objects in SystemC path
|
# Clean away verilator build path and objects in SystemC path
|
clean-vlt:
|
clean-vlt:
|
$(Q)rm -rf $(SIM_VLT_DIR)
|
$(Q)rm -rf $(SIM_VLT_DIR)
|
$(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f \
|
$(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f \
|
$(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
$(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
|
|
clean-test-defines:
|
clean-test-defines:
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
$(Q)rm -f $(TEST_DEFINES_VLG)
|
|
|
clean-sim-test-sw:
|
clean-sim-test-sw:
|
$(Q)if [ -L $(SIM_DIR_VMEM_IMAGE) ]; then unlink $(SIM_DIR_VMEM_IMAGE); fi
|
$(Q)if [ -L $(SIM_DIR_VMEM_IMAGE) ]; then unlink $(SIM_DIR_VMEM_IMAGE); fi
|
|
|
clean-sw:
|
clean-sw:
|
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
|
$(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
|
$(Q) $(MAKE) -C $(SW_DIR)/lib distclean
|
$(Q) $(MAKE) -C $(SW_DIR)/lib distclean
|
|
|
clean-rtl:
|
clean-rtl:
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
for module in $(RTL_TO_CHECK); do \
|
for module in $(RTL_TO_CHECK); do \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
|
done
|
done
|
|
|
# Removes any checked out RTL
|
# Removes any checked out RTL
|
distclean: clean
|
distclean: clean
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
$(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
|
$(Q)for module in $(RTL_TO_CHECK); do \
|
$(Q)for module in $(RTL_TO_CHECK); do \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module distclean; \
|
$(MAKE) -C $(RTL_VERILOG_DIR)/$$module distclean; \
|
done
|
done
|
|
|
################################################################################
|
################################################################################
|
# Verilator model build rules
|
# Verilator model build rules
|
################################################################################
|
################################################################################
|
|
|
VLT_EXE=Vorpsoc_top
|
VLT_EXE=Vorpsoc_top
|
VLT_SCRIPT=verilator.scr
|
VLT_SCRIPT=verilator.scr
|
|
|
# Script for Verilator
|
# Script for Verilator
|
$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
|
$(BOOTROM_VERILOG)
|
$(BOOTROM_VERILOG)
|
$(Q)echo "\tGenerating Verilator script"
|
$(Q)echo "\tGenerating Verilator script"
|
$(Q)echo "# Verilator sources script" > $@
|
$(Q)echo "# Verilator sources script" > $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
|
$(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
|
$(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
$(Q)for module in $(RTL_VERILOG_MODULES); do \
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
|
done
|
done
|
$(Q)echo $(DUT_TOP) >> $@;
|
$(Q)echo $(DUT_TOP) >> $@;
|
$(Q) echo >> $@
|
$(Q) echo >> $@
|
|
|
|
|
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
|
|
|
|
# List of System C models - use this list to link the sources into the Verilator
|
# List of System C models - use this list to link the sources into the Verilator
|
# build directory
|
# build directory
|
SYSC_MODELS=OrpsocAccess MemoryLoad
|
SYSC_MODELS=OrpsocAccess MemoryLoad
|
|
|
ifdef VLT_LINT
|
ifdef VLT_LINT
|
VLT_FLAGS +=--lint-only
|
VLT_FLAGS +=--lint-only
|
endif
|
endif
|
|
|
ifdef VLT_DEBUG
|
ifdef VLT_DEBUG
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
# Enabling the following generates a TON of debugging
|
# Enabling the following generates a TON of debugging
|
# when running verilator. Not so helpful.
|
# when running verilator. Not so helpful.
|
#VLT_FLAGS = --debug --dump-tree
|
#VLT_FLAGS = --debug --dump-tree
|
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
|
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
|
endif
|
endif
|
|
|
# This will build a verilator model that will generate profiling information
|
# This will build a verilator model that will generate profiling information
|
# suitable for gprof
|
# suitable for gprof
|
# Run it through gprof after exection with: gprof Vorpsoc_top > gprof.out
|
# Run it through gprof after exection with: gprof Vorpsoc_top > gprof.out
|
# then run this through the Verilator tool with:
|
# then run this through the Verilator tool with:
|
# verilator_profcfunc gprof.out > vprof.out
|
# verilator_profcfunc gprof.out > vprof.out
|
ifdef VLT_EXECUTION_PROFILE_BUILD
|
ifdef VLT_EXECUTION_PROFILE_BUILD
|
VLT_CPPFLAGS +=-g -pg
|
VLT_CPPFLAGS +=-g -pg
|
# Maybe add these to VLT_CPPFLAGS: -ftest-coverage -fprofile-arcs
|
# Maybe add these to VLT_CPPFLAGS: -ftest-coverage -fprofile-arcs
|
VLT_FLAGS +=-profile-cfuncs
|
VLT_FLAGS +=-profile-cfuncs
|
endif
|
endif
|
|
|
# If set on the command line we build the cycle accurate model which will
|
# If set on the command line we build the cycle accurate model which will
|
# generate verilator-specific profiling information. This is useful for
|
# generate verilator-specific profiling information. This is useful for
|
# checking the efficiency of the model - not really useful for checking code
|
# checking the efficiency of the model - not really useful for checking code
|
# or the function of the model.
|
# or the function of the model.
|
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
|
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
|
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt \
|
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt \
|
-funroll-loops -fpeel-loops -ftracer
|
-funroll-loops -fpeel-loops -ftracer
|
else
|
else
|
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
endif
|
endif
|
|
|
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
|
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
|
# executable in GDB.
|
# executable in GDB.
|
ifdef VLT_IN_GDB
|
ifdef VLT_IN_GDB
|
VLT_CPPFLAGS +=-g -O0
|
VLT_CPPFLAGS +=-g -O0
|
else
|
else
|
# The default optimisation flag applied to all of the cycle accurate model files
|
# The default optimisation flag applied to all of the cycle accurate model files
|
VLT_CPPFLAGS +=-O3
|
VLT_CPPFLAGS +=-O3
|
endif
|
endif
|
|
|
# VCD Enabled by default when building, enable it at runtime
|
# VCD Enabled by default when building, enable it at runtime
|
VLT_FLAGS +=-trace
|
VLT_FLAGS +=-trace
|
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
|
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
|
|
|
# Verilator tuning
|
# Verilator tuning
|
# Inlining:
|
# Inlining:
|
VLT_FLAGS +=--inline-mult 1
|
VLT_FLAGS +=--inline-mult 1
|
# Optimisation option for Verilator scripts
|
# Optimisation option for Verilator scripts
|
VLT_FLAGS +=-O3
|
VLT_FLAGS +=-O3
|
# X-assign - at reset, all signals are set to random values, helps find
|
# X-assign - at reset, all signals are set to random values, helps find
|
# reset bugs
|
# reset bugs
|
VLT_FLAGS +=-x-assign unique
|
VLT_FLAGS +=-x-assign unique
|
|
|
VLT_TRACEOBJ = verilated_vcd_c
|
VLT_TRACEOBJ = verilated_vcd_c
|
|
|
|
|
# This is the list of extra models we'll issue make commands for
|
# This is the list of extra models we'll issue make commands for
|
# Included is the SystemPerl trace model
|
# Included is the SystemPerl trace model
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
|
|
# List of sources for rule sensitivity
|
# List of sources for rule sensitivity
|
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
|
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
|
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
|
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
|
|
|
VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do \
|
VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do \
|
echo $(SIM_VLT_DIR)/$$mod.o; \
|
echo $(SIM_VLT_DIR)/$$mod.o; \
|
done)
|
done)
|
|
|
VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do \
|
VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do \
|
echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
done)
|
done)
|
|
|
# Make Verilator build path if it doesn't exist
|
# Make Verilator build path if it doesn't exist
|
$(SIM_VLT_DIR):
|
$(SIM_VLT_DIR):
|
mkdir -p $@
|
mkdir -p $@
|
|
|
# Dummy files the RTL requires: timescale.v
|
# Dummy files the RTL requires: timescale.v
|
DUMMY_FILES_FOR_VLT=$(SIM_VLT_DIR)/timescale.v
|
DUMMY_FILES_FOR_VLT=$(SIM_VLT_DIR)/timescale.v
|
$(DUMMY_FILES_FOR_VLT):
|
$(DUMMY_FILES_FOR_VLT):
|
$(Q)for file in $@; do if [ ! -e $$file ]; then touch $$file; fi; done
|
$(Q)for file in $@; do if [ ! -e $$file ]; then touch $$file; fi; done
|
|
|
build-vlt: rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
build-vlt: rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
processed-verilog-headers-in-c-for-vlt $(SIM_VLT_DIR)/$(VLT_EXE)
|
processed-verilog-headers-in-c-for-vlt $(SIM_VLT_DIR)/$(VLT_EXE)
|
|
|
# Main Cycle-accurate build rule
|
# Main Cycle-accurate build rule
|
prepare-vlt: build-vlt
|
prepare-vlt: build-vlt
|
@echo;echo "\tCycle-accurate model compiled successfully"
|
@echo;echo "\tCycle-accurate model compiled successfully"
|
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo
|
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo
|
$(SIM_VLT_DIR)/$(VLT_EXE) -h
|
$(SIM_VLT_DIR)/$(VLT_EXE) -h
|
@echo;echo
|
@echo;echo
|
|
|
$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a \
|
$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a \
|
$(SIM_VLT_DIR)/OrpsocMain.o
|
$(SIM_VLT_DIR)/OrpsocMain.o
|
# Final linking of the simulation executable. Order of libraries here is
|
# Final linking of the simulation executable. Order of libraries here is
|
# important!
|
# important!
|
$(Q)echo; echo "\tGenerating simulation executable"; echo
|
$(Q)echo; echo "\tGenerating simulation executable"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
g++ $(VLT_DEBUG_COMPILE_FLAGS) \
|
g++ $(VLT_DEBUG_COMPILE_FLAGS) \
|
$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
|
$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
|
-I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) \
|
-I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) \
|
-L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) \
|
-L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) \
|
OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
|
OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
|
|
|
# Now compile the top level systemC "testbench" module from the systemC source
|
# Now compile the top level systemC "testbench" module from the systemC source
|
# path
|
# path
|
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
cd $(SIM_VLT_DIR) && \
|
cd $(SIM_VLT_DIR) && \
|
g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) \
|
g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) \
|
-I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
|
-I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
|
-I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c \
|
-I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c \
|
$(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
$(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
|
|
$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a \
|
$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a \
|
$(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
|
$(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
|
# Now archive all of the libraries from verilator witht he other modules we
|
# Now archive all of the libraries from verilator witht he other modules we
|
# might have
|
# might have
|
@echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
|
@echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
|
cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
|
ar rcs lib$(VLT_EXE).a verilated.o; \
|
ar rcs lib$(VLT_EXE).a verilated.o; \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
ar rcs lib$(VLT_EXE).a $$SYSCMODEL.o; \
|
ar rcs lib$(VLT_EXE).a $$SYSCMODEL.o; \
|
done
|
done
|
|
|
$(SIM_VLT_DIR)/verilated.o: $(SYSC_MODEL_SOURCES)
|
$(SIM_VLT_DIR)/verilated.o: $(SYSC_MODEL_SOURCES)
|
@echo; echo "\tCompiling verilated.o"; echo
|
@echo; echo "\tCompiling verilated.o"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -f $(VLT_EXE).mk verilated.o
|
$(MAKE) -f $(VLT_EXE).mk verilated.o
|
|
|
print-sysmod-objs:
|
print-sysmod-objs:
|
$(Q)echo $(VLT_MODULES_OBJS):
|
$(Q)echo $(VLT_MODULES_OBJS):
|
|
|
$(VLT_MODULES_OBJS):
|
$(VLT_MODULES_OBJS):
|
# Compile the module files
|
# Compile the module files
|
@echo; echo "\tCompiling SystemC models"
|
@echo; echo "\tCompiling SystemC models"
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
|
$(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
|
done
|
done
|
|
|
$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk \
|
$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk \
|
$(SYSC_MODEL_SOURCES)
|
$(SYSC_MODEL_SOURCES)
|
@echo; echo "\tCompiling main design"; echo
|
@echo; echo "\tCompiling main design"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
|
$(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
|
|
|
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) \
|
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) \
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a
|
# Now call verilator to generate the .mk files
|
# Now call verilator to generate the .mk files
|
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
|
$(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc \
|
verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc \
|
$(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) \
|
$(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) \
|
-f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
-f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
|
|
# SystemC modules library
|
# SystemC modules library
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
|
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
|
@echo; echo "\tCompiling SystemC modules"; echo
|
@echo; echo "\tCompiling SystemC modules"; echo
|
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) \
|
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) \
|
-f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
-f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
|
|
print-vlt-model-link-paths:
|
print-vlt-model-link-paths:
|
$(Q)echo $(VLT_MODEL_LINKS)
|
$(Q)echo $(VLT_MODEL_LINKS)
|
|
|
$(VLT_MODEL_LINKS):
|
$(VLT_MODEL_LINKS):
|
# Link all the required system C model files into the verilator work dir
|
# Link all the required system C model files into the verilator work dir
|
$(Q)for SYSCMODEL in $(SYSC_MODELS); do \
|
$(Q)for SYSCMODEL in $(SYSC_MODELS); do \
|
if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
|
if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
|
echo \
|
echo \
|
"\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \
|
"\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp \
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp \
|
$(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
$(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h \
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h \
|
$(SIM_VLT_DIR)/$$SYSCMODEL.h; \
|
$(SIM_VLT_DIR)/$$SYSCMODEL.h; \
|
fi; \
|
fi; \
|
done
|
done
|
|
|
|
|
################################################################################
|
################################################################################
|
# Verilator model test rules
|
# Verilator model test rules
|
################################################################################
|
################################################################################
|
|
|
vlt-test: build-vlt clean-sim-test-sw sw-vmem
|
vlt-test: build-vlt clean-sim-test-sw sw-vmem
|
$(SIM_VLT_DIR)/$(VLT_EXE) $(TEST)
|
$(SIM_VLT_DIR)/$(VLT_EXE) $(TEST)
|
|
|
vlt-tests:
|
vlt-tests:
|
$(Q)for test in $(TESTS); do \
|
$(Q)for test in $(TESTS); do \
|
export TEST=$$test; \
|
export TEST=$$test; \
|
$(MAKE) vlt-test; \
|
$(MAKE) vlt-test; \
|
if [ $$? -ne 0 ]; then break; fi; \
|
if [ $$? -ne 0 ]; then break; fi; \
|
echo; echo "\t### $$test test OK ###"; echo; \
|
echo; echo "\t### $$test test OK ###"; echo; \
|
done
|
done
|
|
|
|
|
|
|
###############################################################################
|
###############################################################################
|
# Verilator profiled model build rules
|
# Verilator profiled model build rules
|
###############################################################################
|
###############################################################################
|
# To run this, first run a "make prepare-vlt-profiled"
|
# To run this, first run a "make prepare-vlt-profiled"
|
# This new make target copies athe results of the profiling back to the right
|
# This new make target copies athe results of the profiling back to the right
|
# paths before we create everything again
|
# paths before we create everything again
|
###############################################################################
|
###############################################################################
|
.PHONY: prepare-vlt-profiled
|
.PHONY: prepare-vlt-profiled
|
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda \
|
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda \
|
clean-vlt-after-profile-run \
|
clean-vlt-after-profile-run \
|
rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
|
$(SIM_VLT_DIR)/$(VLT_EXE)
|
$(SIM_VLT_DIR)/$(VLT_EXE)
|
|
|
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
|
$(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
|
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
|
$(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
|
|
|
# Clean all compiled things
|
# Clean all compiled things
|
clean-vlt-after-profile-run:
|
clean-vlt-after-profile-run:
|
$(Q)echo "\tCleaning away compiled cycle-accurate files"
|
$(Q)echo "\tCleaning away compiled cycle-accurate files"
|
$(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)
|
$(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)
|
$(Q)rm -f $(BENCH_SYSC_SRC_DIR)/*.[oa]
|
$(Q)rm -f $(BENCH_SYSC_SRC_DIR)/*.[oa]
|
|
|
#.PHONY: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
#.PHONY: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
|
$(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling:
|
$(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling:
|
$(MAKE) build-vlt VLT_DO_PERFORMANCE_PROFILE_BUILD=1
|
$(MAKE) build-vlt VLT_DO_PERFORMANCE_PROFILE_BUILD=1
|
|
|
.PHONY: vlt-restore-profileoutput
|
.PHONY: vlt-restore-profileoutput
|
vlt-restore-profileoutput:
|
vlt-restore-profileoutput:
|
@echo;echo "\tRestoring profiling outputs"; echo
|
@echo;echo "\tRestoring profiling outputs"; echo
|
$(Q)mkdir -p ../vlt
|
$(Q)mkdir -p ../vlt
|
$(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
|
$(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
|
$(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
|
$(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
|
|
|
|
|
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
$(Q)echo; echo "\tLinting design with Verilator"; echo
|
$(Q)echo; echo "\tLinting design with Verilator"; echo
|
$(Q)cd $(SIM_VLT_DIR) && \
|
$(Q)cd $(SIM_VLT_DIR) && \
|
verilator -language 1364-2001 --top-module orpsoc_top --lint-only \
|
verilator -language 1364-2001 --top-module orpsoc_top --lint-only \
|
-Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) \
|
-Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) \
|
-I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
-I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
|
|
|
################################################################################
|
################################################################################
|
# Architectural simulator test rules
|
# Architectural simulator test rules
|
################################################################################
|
################################################################################
|
|
|
ARCH_SIM_EXE ?=or32-elf-sim
|
ARCH_SIM_EXE ?=or32-elf-sim
|
ARCH_SIM_CFG ?= ../bin/refdesign-or1ksim.cfg
|
ARCH_SIM_CFG ?= ../bin/refdesign-or1ksim.cfg
|
ARCH_SIM_OPTS ?= -q
|
ARCH_SIM_OPTS ?= -q
|
|
|
.PHONY: rtl-test
|
.PHONY: rtl-test
|
sim-test: clean-sim-test-sw sw-elf
|
sim-test: clean-sim-test-sw sw-elf
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)echo; echo "\t### Launching simulation ###"; echo
|
$(Q)$(ARCH_SIM_EXE) $(ARCH_SIM_OPTS) -f $(ARCH_SIM_CFG) $(TEST).elf > \
|
$(Q)$(ARCH_SIM_EXE) $(ARCH_SIM_OPTS) -f $(ARCH_SIM_CFG) $(TEST).elf > \
|
$(RTL_SIM_RESULTS_DIR)/$(TEST)$(TEST_OUT_FILE_SUFFIX)
|
$(RTL_SIM_RESULTS_DIR)/$(TEST)$(TEST_OUT_FILE_SUFFIX)
|
|
|
# Run tests in simulation, check output
|
# Run tests in simulation, check output
|
sim-test-with-check: sim-test check-test-log
|
sim-test-with-check: sim-test check-test-log
|
|
|
# Main architectural simulations test loop
|
# Main architectural simulations test loop
|
sim-tests:
|
sim-tests:
|
$(Q)for test in $(TESTS); do \
|
$(Q)for test in $(TESTS); do \
|
export TEST=$$test; \
|
export TEST=$$test; \
|
$(MAKE) sim-test-with-check; \
|
$(MAKE) sim-test-with-check; \
|
if [ $$? -ne 0 ]; then break; fi; \
|
if [ $$? -ne 0 ]; then break; fi; \
|
echo; echo "\t### $$test test OK ###"; echo; \
|
echo; echo "\t### $$test test OK ###"; echo; \
|
done
|
done
|
|
|
