//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/// ////
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/// ////
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/// bootrom ////
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/// bootrom ////
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/// ////
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/// ////
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/// Assembly programs to be embedded inside system to aid boot ////
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/// Assembly programs to be embedded inside system to aid boot ////
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/// ////
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/// ////
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/// Julius Baxter, julius@opencores.org ////
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/// Julius Baxter, julius@opencores.org ////
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/// ////
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/// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// Defines for which bootrom app to use are in board.h - TODO: use the
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// Defines for which bootrom app to use are in board.h - TODO: use the
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// processed orspoc-defines.v file for this define. It makes more sense
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// processed orspoc-defines.v file for this define. It makes more sense
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// as this software ends up as gates.
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// as this software ends up as gates.
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#include "board.h"
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#include "board.h"
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#ifdef BOOTROM_SPI_FLASH
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#ifdef BOOTROM_SPI_FLASH
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/* Assembly program to go into the boot ROM */
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/* Assembly program to go into the boot ROM */
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/* For use with simple_spi SPI master core and standard SPI flash
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interface-compatible parts (ST M25P16 for example.)*/
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/* Currently just loads a program from SPI flash into RAM */
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/* Currently just loads a program from SPI flash into RAM */
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/* Assuming address at RAM_LOAD_BASE gets clobbered, we need
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/* Assuming address at RAM_LOAD_BASE gets clobbered, we need
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a byte writable address somewhere!*/
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a byte writable address somewhere!*/
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#define SPI_BASE SPI0_BASE
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#define SPI_BASE SPI0_BASE
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/* simple_spi driver */
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/* simple_spi driver */
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#define SPI_SPCR 0x0
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#define SPI_SPCR 0x0
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#define SPI_SPSR 0x1
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#define SPI_SPSR 0x1
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#define SPI_SPDR 0x2
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#define SPI_SPDR 0x2
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#define SPI_SPER 0x3
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#define SPI_SPER 0x3
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#define SPI_SPSS 0x4
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#define SPI_SPSS 0x4
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#define SPI_SPCR_XFER_GO 0x51
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#define SPI_SPCR_XFER_GO 0x51
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#define SPI_SPSS_INIT 0x1
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#define SPI_SPSS_INIT 0x1
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#define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/
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#define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/
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#define RAM_LOAD_BASE SDRAM_BASE
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#define RAM_LOAD_BASE SDRAM_BASE
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#define RESET_ADDR 0x100
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#define RESET_ADDR 0x100
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boot_init:
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boot_init:
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l.movhi r0, 0
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l.movhi r0, 0
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l.movhi r1, RAM_LOAD_BASE
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l.movhi r1, RAM_LOAD_BASE
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l.movhi r4, hi(SPI_BASE)
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l.movhi r4, hi(SPI_BASE)
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spi_init:
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spi_init:
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l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
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l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
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l.sb SPI_SPCR(r4), r2
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l.sb SPI_SPCR(r4), r2
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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l.ori r6, r0, SPI_SPSS_INIT
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l.ori r6, r0, SPI_SPSS_INIT
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l.sb SPI_SPSS(r4), r6 /* Now put in appropriate slave select */
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l.sb SPI_SPSS(r4), r6 /* Set appropriate slave select */
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l.jal spi_xfer
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l.jal spi_xfer
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l.ori r3, r0, 0x3 /* READ command opcode for SPI device */
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l.ori r3, r0, 0x3 /* READ command opcode for SPI device*/
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l.jal spi_xfer
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l.jal spi_xfer
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#ifdef BOOTROM_ADDR_BYTE2
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l.ori r3, r0, BOOTROM_ADDR_BYTE2 /* Use addr if defined. MSB first */
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#else
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l.or r3, r0, r0
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l.or r3, r0, r0
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#endif
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l.jal spi_xfer
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l.jal spi_xfer
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#ifdef BOOTROM_ADDR_BYTE1
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l.ori r3, r0, BOOTROM_ADDR_BYTE1
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#else
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l.or r3, r0, r0
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l.or r3, r0, r0
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#endif
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l.jal spi_xfer
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l.jal spi_xfer
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#ifdef BOOTROM_ADDR_BYTE0
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l.ori r3, r0, BOOTROM_ADDR_BYTE0
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#else
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l.or r3, r0, r0
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l.or r3, r0, r0
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#endif
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l.movhi r6, 0
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l.movhi r6, 0
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l.movhi r7, 0xffff
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l.movhi r7, 0xffff
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copy:
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copy:
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l.jal spi_xfer /* Read a byte into r3 */
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l.jal spi_xfer /* Read a byte into r3 */
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l.add r8, r1, r6 /* Calculate store address */
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l.add r8, r1, r6 /* Calculate store address */
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l.sb 0(r8), r3 /* Write byte to memory */
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l.sb 0(r8), r3 /* Write byte to memory */
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l.addi r6, r6, 1 /* Increment counter */
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l.addi r6, r6, 1 /* Increment counter */
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l.sfeqi r6, 0x4 /* Is this the first word */
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l.sfeqi r6, 0x4 /* Is this the first word ?*/
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l.bf store_sizeword /* put sizeword in the register */
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l.bf store_sizeword /* put sizeword in the register */
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l.sfeq r6, r7 /* Check if we've finished loading the words */
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l.sfeq r6, r7 /* Check if we've finished loading the words */
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l.bnf copy /* Continue copying if not last word */
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l.bnf copy /* Continue copying if not last word */
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l.nop
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l.nop
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goto_reset:
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goto_reset:
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l.ori r1, r1, RESET_ADDR
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l.ori r1, r1, RESET_ADDR
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l.jr r1
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l.jr r1
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */
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store_sizeword:
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store_sizeword:
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#ifdef SPI_RETRY_IF_INSANE_SIZEWORD
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l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
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l.srli r10, r7, 16 /* Chop the sizeword we read in half */
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l.sfgtui r10, 0x0200 /* It's unlikely we'll ever load > 32MB */
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l.bf boot_init
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l.nop
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l.j copy
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l.nop
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#else
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l.j copy
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l.j copy
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l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
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l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */
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#endif
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spi_xfer:
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spi_xfer:
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l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */
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l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */
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l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
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l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
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spi_xfer_poll:
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spi_xfer_poll:
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l.andi r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */
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l.andi r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */
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l.sfeqi r3, SPI_SPSR_RX_CHECK /* is bit set? ... */
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l.sfeqi r3, SPI_SPSR_RX_CHECK /* is bit set? ... */
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l.bf spi_xfer_poll /* ... if so, rxfifo empty, keep polling */
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l.bf spi_xfer_poll /* ... if so, rxfifo empty, keep polling */
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l.lbz r3, SPI_SPSR(r4) /* Read SPSR */
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l.lbz r3, SPI_SPSR(r4) /* Read SPSR */
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l.jr r9
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l.jr r9
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l.lbz r3, SPI_SPDR(r4) /* Get data byte */
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l.lbz r3, SPI_SPDR(r4) /* Get data byte */
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#endif
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#endif
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#ifdef BOOTROM_GOTO_RESET
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#ifdef BOOTROM_GOTO_RESET
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/* Jump to reset vector in the SDRAM */
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/* Jump to reset vector in the SDRAM */
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l.movhi r0, 0
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l.movhi r0, 0
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l.movhi r4, SDRAM_BASE
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l.movhi r4, SDRAM_BASE
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l.ori r4, r4, 0x100
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l.ori r4, r4, 0x100
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l.jr r4
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l.jr r4
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l.nop
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l.nop
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#endif
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#endif
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#ifdef BOOTROM_LOOP_AT_ZERO
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#ifdef BOOTROM_LOOP_AT_ZERO
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/* Don't load app via SPI, instead just put an infinite loop into bottom
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/* Don't load app via SPI, instead just put an infinite loop into bottom
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of memory and jump there.
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of memory and jump there.
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*/
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*/
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l.movhi r0, 0
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l.movhi r0, 0
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l.movhi r4, SDRAM_BASE
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l.movhi r4, SDRAM_BASE
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l.sw 0x0(r4), r0
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l.sw 0x0(r4), r0
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l.movhi r5, hi(0x15000001) /* A l.nop 1 so sim exits if this enabled */
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l.movhi r5, hi(0x15000001) /* A l.nop 1 so sim exits if this enabled */
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l.ori r5, r5, lo(0x15000001)
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l.ori r5, r5, lo(0x15000001)
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l.sw 0x4(r4), r5
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l.sw 0x4(r4), r5
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l.sw 0x8(r4), r5
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l.sw 0x8(r4), r5
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l.sw 0xc(r4), r5
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l.sw 0xc(r4), r5
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l.jr r4
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l.jr r4
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l.nop
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l.nop
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#endif
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#endif
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#ifdef BOOTROM_LOOP_IN_ROM
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#ifdef BOOTROM_LOOP_IN_ROM
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/* Don't load app via SPI, instead just put an infinite loop into bottom
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/* Don't load app via SPI, instead just put an infinite loop into bottom
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of memory and jump there.
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of memory and jump there.
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*/
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*/
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l.movhi r0, 0
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l.movhi r0, 0
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l.nop 0x1
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l.nop 0x1
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l.j 0
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l.j 0
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l.nop
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l.nop
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l.nop
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l.nop
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#endif
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#endif
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