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#include "spr-defs.h"
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#include "board.h"
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/* ======================================================= [ macros ] === */
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#define CLEAR_GPR(gpr) \
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l.or gpr, r0, r0
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#define ENTRY(symbol) \
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.global symbol ; \
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symbol:
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#define LOAD_SYMBOL_2_GPR(gpr,symbol) \
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.global symbol ; \
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l.movhi gpr, hi(symbol) ; \
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l.ori gpr, gpr, lo(symbol)
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// Really goes to configurable interrupt handler
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#define UNHANDLED_EXCEPTION \
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l.addi r1, r1, -128; \
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l.sw 4(r1), r3; \
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l.sw 8(r1), r4; \
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l.mfspr r3,r0,SPR_NPC; \
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l.mfspr r4,r0,SPR_EPCR_BASE; \
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l.j default_exception_handler; \
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l.nop
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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l.movhi r0, 0
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/* Clear status register, set supervisor mode */
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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/* Early Stack initilization */
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LOAD_SYMBOL_2_GPR(r1, _stack)
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l.addi r2, r0, -3
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l.and r1, r1, r2
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/* Jump to program initialisation code */
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LOAD_SYMBOL_2_GPR(r4, _start)
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l.jr r4
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l.nop
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/* ---[ 0x200: BUS exception ]------------------------------------------- */
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.org 0x200
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UNHANDLED_EXCEPTION
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/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
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.org 0x300
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UNHANDLED_EXCEPTION
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/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
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.org 0x400
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UNHANDLED_EXCEPTION
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/* ---[ 0x500: Timer exception ]----------------------------------------- */
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.org 0x500
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#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
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//UNHANDLED_EXCEPTION
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/* Simply load timer_ticks variable and increment */
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.extern timer_ticks
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l.addi r1, r1, -8
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l.sw 0(r1), r25
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l.sw 4(r1), r26
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l.movhi r25, hi(timer_ticks)
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l.ori r25, r25, lo(timer_ticks)
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l.lwz r26, 0(r25) /* Load variable addr.*/
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l.addi r26, r26, 1 /* Increment variable */
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l.sw 0(r25), r26 /* Store variable */
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l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */
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l.ori r25, r25, lo(TIMER_RELOAD_VALUE)
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l.mtspr r0, r25, SPR_TTMR /* Reset timer */
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l.lwz r25, 0(r1)
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l.lwz r26, 4(r1)
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l.addi r1, r1, 8
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l.rfe
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/* ---[ 0x600: Aligment exception ]-------------------------------------- */
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.org 0x600
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UNHANDLED_EXCEPTION
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/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
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.org 0x700
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UNHANDLED_EXCEPTION
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/* ---[ 0x800: External interrupt exception ]---------------------------- */
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.org 0x800
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UNHANDLED_EXCEPTION
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/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
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.org 0x900
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UNHANDLED_EXCEPTION
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/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
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.org 0xa00
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UNHANDLED_EXCEPTION
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/* ---[ 0xb00: Range exception ]----------------------------------------- */
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.org 0xb00
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UNHANDLED_EXCEPTION
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/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
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.org 0xc00
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UNHANDLED_EXCEPTION
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/* ---[ 0xd00: Trap exception ]------------------------------------------ */
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.org 0xd00
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UNHANDLED_EXCEPTION
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/* ---[ 0xe00: Trap exception ]------------------------------------------ */
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.org 0xe00
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UNHANDLED_EXCEPTION
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/* ---[ 0xf00: Reserved exceptions ]------------------------------------- */
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.org 0xf00
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UNHANDLED_EXCEPTION
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/*
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.org 0x1000
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UNHANDLED_EXCEPTION
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.org 0x1100
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UNHANDLED_EXCEPTION
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.org 0x1200
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UNHANDLED_EXCEPTION
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.org 0x1300
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UNHANDLED_EXCEPTION
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.org 0x1400
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UNHANDLED_EXCEPTION
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.org 0x1500
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UNHANDLED_EXCEPTION
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.org 0x1600
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UNHANDLED_EXCEPTION
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.org 0x1700
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UNHANDLED_EXCEPTION
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.org 0x1800
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UNHANDLED_EXCEPTION
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.org 0x1900
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UNHANDLED_EXCEPTION
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.org 0x1a00
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UNHANDLED_EXCEPTION
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.org 0x1b00
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UNHANDLED_EXCEPTION
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.org 0x1c00
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UNHANDLED_EXCEPTION
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.org 0x1d00
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UNHANDLED_EXCEPTION
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.org 0x1e00
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UNHANDLED_EXCEPTION
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.org 0x1f00
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UNHANDLED_EXCEPTION
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*/
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/* ========================================================= [ entry ] === */
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.section .text
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ENTRY(_start)
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.bf .L8
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l.nop
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate IC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.bf .L7
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l.add r6,r6,r14
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.L8:
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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l.bf .L10
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l.nop
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/* Disable DC */
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.sll r14,r30,r28
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/* Establish number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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*/
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.sll r16,r30,r28
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/* Invalidate DC */
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l.addi r6,r0,0
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l.sll r5,r14,r28
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.L9:
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l.mtspr r0,r6,SPR_DCBIR
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l.sfne r6,r5
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l.bf .L9
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l.add r6,r6,r14
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/* Enable DC */
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_DCE
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l.mtspr r0,r6,SPR_SR
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.L10:
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/* Initialise stack */
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/* LOAD_SYMBOL_2_GPR(r1, _stack)
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l.addi r2, r0, -3
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l.and r1, r1, r2
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*/
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/* Clear BSS */
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LOAD_SYMBOL_2_GPR(r28, ___bss_start)
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LOAD_SYMBOL_2_GPR(r30, __end)
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1:
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l.sw (0)(r28), r0
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l.sfltu r28, r30
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l.bf 1b
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l.addi r28, r28, 4
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/* Initialise UART in a C function */
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/*l.jal _uart_init
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l.nop*/
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/* Jump to main program entry point (argc = argv = 0) */
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CLEAR_GPR(r3)
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CLEAR_GPR(r4)
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l.jal main
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l.nop
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/* If program exits, call exit routine */
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l.addi r3, r11, 0
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l.jal exit
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l.nop
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/* ====================================== [ default exception handler ] === */
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default_exception_handler:
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l.sw 0x00(r1), r2
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l.sw 0x0c(r1), r5
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l.sw 0x10(r1), r6
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l.sw 0x14(r1), r7
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l.sw 0x18(r1), r8
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l.sw 0x1c(r1), r9
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l.sw 0x20(r1), r10
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l.sw 0x24(r1), r11
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l.sw 0x28(r1), r12
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l.sw 0x2c(r1), r13
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l.sw 0x30(r1), r14
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l.sw 0x34(r1), r15
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l.sw 0x38(r1), r16
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l.sw 0x3c(r1), r17
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l.sw 0x40(r1), r18
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l.sw 0x44(r1), r19
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l.sw 0x48(r1), r20
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l.sw 0x4c(r1), r21
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l.sw 0x50(r1), r22
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l.sw 0x54(r1), r23
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l.sw 0x58(r1), r24
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l.sw 0x5c(r1), r25
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l.sw 0x60(r1), r26
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l.sw 0x64(r1), r27
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l.sw 0x68(r1), r28
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l.sw 0x6c(r1), r29
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l.sw 0x70(r1), r30
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l.sw 0x74(r1), r31
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l.sw 0x78(r1), r32
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l.jal default_exception_handler_c
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l.nop
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l.lwz r2, 0x00(r1)
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l.lwz r3, 0x04(r1)
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l.lwz r4, 0x08(r1)
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l.lwz r5, 0x0c(r1)
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l.lwz r6, 0x10(r1)
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l.lwz r7, 0x14(r1)
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l.lwz r8, 0x18(r1)
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l.lwz r9, 0x1c(r1)
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l.lwz r10, 0x20(r1)
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l.lwz r11, 0x24(r1)
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l.lwz r12, 0x28(r1)
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l.lwz r13, 0x2c(r1)
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l.lwz r14, 0x30(r1)
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l.lwz r15, 0x34(r1)
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l.lwz r16, 0x38(r1)
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l.lwz r17, 0x3c(r1)
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l.lwz r18, 0x40(r1)
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l.lwz r19, 0x44(r1)
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l.lwz r20, 0x48(r1)
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l.lwz r21, 0x4c(r1)
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l.lwz r22, 0x50(r1)
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l.lwz r23, 0x54(r1)
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l.lwz r24, 0x58(r1)
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l.lwz r25, 0x5c(r1)
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l.lwz r26, 0x60(r1)
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l.lwz r27, 0x64(r1)
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l.lwz r28, 0x68(r1)
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l.lwz r29, 0x6c(r1)
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l.lwz r30, 0x70(r1)
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l.lwz r31, 0x74(r1)
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l.lwz r32, 0x78(r1)
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l.addi r1, r1, 128
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l.rfe
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l.nop
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