/*
|
/*
|
OR1200 carry bit checking
|
OR1200 carry bit checking
|
|
|
Carry generated on all adds which we interpret to be
|
Carry generated on all adds which we interpret to be
|
unsigned. The CPU will generate both CY and OV.
|
unsigned. The CPU will generate both CY and OV.
|
CY is generated when unsigned values generate an extra bit.
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CY is generated when unsigned values generate an extra bit.
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OV is when the values, interpreted as signed, cannot have
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OV is when the values, interpreted as signed, cannot have
|
the result displayed as it is too large.
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the result displayed as it is too large.
|
|
|
OV is not checked here. Just CY generation and inclusion by
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OV is not checked here. Just CY generation and inclusion by
|
the l.addc and l.addic instructions.
|
the l.addc and l.addic instructions.
|
|
|
Very basic, testing.
|
Very basic, testing.
|
|
|
TODO: Substraction carry out testing.
|
TODO: Substraction carry out testing.
|
|
|
Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
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Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
|
|
|
*/
|
*/
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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|
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#include "or1200-defines.h"
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#include "or1200-defines.h"
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|
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/* =================================================== [ exceptions ] === */
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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.section .vectors, "ax"
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|
|
|
|
/* ---[ 0x100: RESET exception ]----------------------------------------- */
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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.org 0x100
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l.movhi r0, 0
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l.movhi r0, 0
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/* Clear status register */
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
|
l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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l.mtspr r0, r0, SPR_TTMR
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|
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/* Jump to program initialisation code */
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/* Jump to program initialisation code */
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.global _start
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.global _start
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l.movhi r4, hi(_start)
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
|
l.jr r4
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l.nop
|
l.nop
|
|
|
.org 0x600
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.org 0x600
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l.nop 0x1
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l.nop 0x1
|
|
|
|
|
/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
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/* ---[ 0x700: Illegal instruction exception ]-------------------------- */
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.org 0x700
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.org 0x700
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#ifndef OR1200_IMPL_ADDC
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#ifndef OR1200_IMPL_ADDC
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// No problem - instruction not supported
|
// No problem - instruction not supported
|
l.movhi r3, hi(0x8000000d)
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l.movhi r3, hi(0x8000000d)
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l.ori r3, r3, lo(0x8000000d)
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l.ori r3, r3, lo(0x8000000d)
|
l.nop 0x2
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l.nop 0x2
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l.ori r3, r0, 0
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l.ori r3, r0, 0
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#else
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#else
|
l.ori r3, r0, 1
|
l.ori r3, r0, 1
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#endif
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#endif
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l.nop 0x1
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l.nop 0x1
|
|
|
/* ---[ 0xb00: Range exception ]---------------------------------------- */
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/* ---[ 0xb00: Range exception ]---------------------------------------- */
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.org 0xb00
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.org 0xb00
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l.sw 0(r0), r3
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l.sw 0(r0), r3
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l.ori r3, r0, 0xaaee
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l.ori r3, r0, 0xaaee
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l.nop 0x2
|
l.nop 0x2
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l.lwz r3, 0(r0)
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l.lwz r3, 0(r0)
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l.rfe
|
l.rfe
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|
|
/* =================================================== [ text ] === */
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/* =================================================== [ text ] === */
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.section .text
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.section .text
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|
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/* =================================================== [ start ] === */
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/* =================================================== [ start ] === */
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|
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.global _start
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.global _start
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_start:
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_start:
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// Clear all regs
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// Clear regs
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l.movhi r1, 0
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l.movhi r1, 0
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l.movhi r2, 0
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l.movhi r2, 0
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l.movhi r3, 0
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l.movhi r3, 0
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l.movhi r4, 0
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l.movhi r4, 0
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l.movhi r5, 0
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l.movhi r5, 0
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l.movhi r6, 0
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l.movhi r6, 0
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l.movhi r7, 0
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l.movhi r8, 0
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l.movhi r9, 0
|
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l.movhi r10, 0
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l.movhi r11, 0
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l.movhi r12, 0
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l.movhi r13, 0
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l.movhi r14, 0
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l.movhi r15, 0
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l.movhi r16, 0
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l.movhi r17, 0
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l.movhi r18, 0
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l.movhi r19, 0
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l.movhi r20, 0
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l.movhi r21, 0
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l.movhi r22, 0
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l.movhi r23, 0
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l.movhi r24, 0
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l.movhi r25, 0
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l.movhi r26, 0
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l.movhi r27, 0
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l.movhi r28, 0
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l.movhi r29, 0
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l.movhi r30, 0
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l.movhi r31, 0
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|
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#ifdef OR1200_IMPL_CY
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#ifdef OR1200_IMPL_CY
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// Kick off test
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// Kick off test
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l.jal _main
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l.jal _main
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#else
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#else
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// Not supported, exit test
|
// Not supported, exit test
|
l.j _finish
|
l.j _finish
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#endif
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#endif
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l.nop
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l.nop
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|
|
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/* =================================================== [ main ] === */
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/* =================================================== [ main ] === */
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|
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#define CHECK_CY_CLEAR \
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#define CHECK_CY_CLEAR \
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l.mfspr r20, r0, SPR_SR ; \
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l.mfspr r6, r0, SPR_SR ; \
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l.andi r21, r20, SPR_SR_CY ; \
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l.andi r6, r6, SPR_SR_CY ; \
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l.sfne r21, r0 ; \
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l.sfne r6, r0 ; \
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l.bf _fail ; \
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l.bf _fail ; \
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l.nop
|
l.nop
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|
|
#define CHECK_CY_SET \
|
#define CHECK_CY_SET \
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l.mfspr r20, r0, SPR_SR ; \
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l.mfspr r6, r0, SPR_SR ; \
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l.andi r21, r20, SPR_SR_CY ; \
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l.andi r6, r6, SPR_SR_CY ; \
|
l.sfnei r21, SPR_SR_CY ; \
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l.sfnei r6, SPR_SR_CY ; \
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l.bf _fail ; \
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l.bf _fail ; \
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l.nop
|
l.nop
|
|
|
.global _main
|
.global _main
|
_main:
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_main:
|
|
|
// Set up some values, check the CY bit is cleared from reset
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// Set up some values, check the CY bit is cleared from reset
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CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
// A large unsigned value
|
// A large unsigned value
|
l.movhi r4, 0xffff
|
l.movhi r4, 0xffff
|
l.ori r4, r4, 0xefff
|
l.ori r4, r4, 0xefff
|
|
|
// A value large enough to cause carry
|
// A value large enough to cause carry
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l.ori r5, r0, 0x1001
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l.ori r5, r0, 0x1001
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|
|
l.add r3, r5, r4 ;// Should set CY
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l.add r3, r5, r4 ;// Should set CY
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l.nop 0x2
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l.nop 0x2
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CHECK_CY_SET
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CHECK_CY_SET
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|
|
l.add r3, r0, r0 ;// Should clear CY
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l.add r3, r0, r0 ;// Should clear CY
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CHECK_CY_CLEAR
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CHECK_CY_CLEAR
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|
|
l.addi r3, r4, 0x1001 ;// Should set CY
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l.addi r3, r4, 0x1001 ;// Should set CY
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l.nop 0x2
|
l.nop 0x2
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CHECK_CY_SET
|
CHECK_CY_SET
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|
|
l.addi r3, r4, 0x1000 ;// Shouldn't set CY
|
l.addi r3, r4, 0x1000 ;// Shouldn't set CY
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l.nop 0x2
|
l.nop 0x2
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CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
l.add r3, r0, r0 ;// Should clear CY
|
l.add r3, r0, r0 ;// Should clear CY
|
CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
// Check use of carry - l.addc
|
// Check use of carry - l.addc
|
l.addi r3, r4, 0x1001 ;// Should set CY
|
l.addi r3, r4, 0x1001 ;// Should set CY
|
;; // Consequtive instructions
|
;; // Consequtive instructions
|
l.addc r3, r3, r5 ;// r3 should be 0x1002
|
l.addc r3, r3, r5 ;// r3 should be 0x1002
|
l.nop 0x2 ;// Report
|
l.nop 0x2 ;// Report
|
|
|
l.sfnei r3, 0x1002
|
l.sfnei r3, 0x1002
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
l.add r3, r4, r5 ;// Should set CY
|
l.add r3, r4, r5 ;// Should set CY
|
l.nop ;// 1 delay instruction
|
l.nop ;// 1 delay instruction
|
l.addc r3, r3, r5 ;// r3 should be 0x1002
|
l.addc r3, r3, r5 ;// r3 should be 0x1002
|
l.nop 0x2 ;// Report
|
l.nop 0x2 ;// Report
|
|
|
l.sfnei r3, 0x1002
|
l.sfnei r3, 0x1002
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
l.add r3, r4, r5 ;// Should set
|
l.add r3, r4, r5 ;// Should set
|
l.nop 0x2 ;// 1 delay instruction
|
l.nop 0x2 ;// 1 delay instruction
|
l.nop ;// 2nd delay instruction
|
l.nop ;// 2nd delay instruction
|
l.addc r3, r3, r5 ;// r3 should be 0x1002
|
l.addc r3, r3, r5 ;// r3 should be 0x1002
|
l.nop 0x2 ;// Report
|
l.nop 0x2 ;// Report
|
|
|
l.sfnei r3, 0x1002
|
l.sfnei r3, 0x1002
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
l.add r3, r0, r0 ;// Should clear CY
|
l.add r3, r0, r0 ;// Should clear CY
|
CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
// Check use of carry - l.addic
|
// Check use of carry - l.addic
|
l.addi r3, r4, 0x1001 ;// Should set CY
|
l.addi r3, r4, 0x1001 ;// Should set CY
|
;; // Consequtive instructions
|
;; // Consequtive instructions
|
l.addic r3, r3, 0x1 ;// r3 should be 2
|
l.addic r3, r3, 0x1 ;// r3 should be 2
|
l.nop 0x2 ;// Report
|
l.nop 0x2 ;// Report
|
|
|
l.sfnei r3, 0x2
|
l.sfnei r3, 0x2
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
l.add r3, r0, r0 ;// Should clear CY
|
l.add r3, r0, r0 ;// Should clear CY
|
CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
l.add r3, r4, r5 ;// Should set CY
|
l.add r3, r4, r5 ;// Should set CY
|
l.nop ;// 1 delay instruction
|
l.nop ;// 1 delay instruction
|
l.addic r3, r3, 0x1 ;// r3 should be 2
|
l.addic r3, r3, 0x1 ;// r3 should be 2
|
l.nop 0x2 ;// Report
|
l.nop 0x2 ;// Report
|
|
|
l.sfnei r3, 0x2
|
l.sfnei r3, 0x2
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
l.add r3, r0, r0 ;// Should clear CY
|
l.add r3, r0, r0 ;// Should clear CY
|
CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
l.add r3, r4, r5 ;// Should set
|
l.add r3, r4, r5 ;// Should set
|
l.nop 0x2 ;// 1 delay instruction
|
l.nop 0x2 ;// 1 delay instruction
|
l.nop ;// 2nd delay instruction
|
l.nop ;// 2nd delay instruction
|
l.addic r3, r3, 0x1 ;// r3 should be 2
|
l.addic r3, r3, 0x1 ;// r3 should be 2
|
l.nop 0x2 ;// Report
|
l.nop 0x2 ;// Report
|
|
|
l.sfnei r3, 0x2
|
l.sfnei r3, 0x2
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
l.add r3, r0, r0 ;// Should clear CY
|
l.add r3, r0, r0 ;// Should clear CY
|
CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
// Add with carry and generate carry with l.addc
|
// Add with carry and generate carry with l.addc
|
|
|
l.add r3, r4, r5
|
l.add r3, r4, r5
|
l.addc r3, r4, r5
|
l.addc r3, r4, r5
|
l.nop 0x2
|
l.nop 0x2
|
|
|
l.sfnei r3, 0x1
|
l.sfnei r3, 0x1
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
CHECK_CY_SET
|
CHECK_CY_SET
|
|
|
l.add r3, r0, r0 ;// Should clear CY
|
l.add r3, r0, r0 ;// Should clear CY
|
CHECK_CY_CLEAR
|
CHECK_CY_CLEAR
|
|
|
// Add with carry and generate carry with l.addic
|
// Add with carry and generate carry with l.addic
|
|
|
l.addi r3, r4, 0x1001
|
l.addi r3, r4, 0x1001
|
l.addic r3, r4, 0x1001
|
l.addic r3, r4, 0x1001
|
l.nop 0x2
|
l.nop 0x2
|
|
|
l.sfnei r3, 0x1
|
l.sfnei r3, 0x1
|
l.bf _fail
|
l.bf _fail
|
l.nop
|
l.nop
|
|
|
CHECK_CY_SET
|
CHECK_CY_SET
|
|
|
_finish:
|
_finish:
|
l.movhi r3, hi(0x8000000d)
|
l.movhi r3, hi(0x8000000d)
|
l.ori r3, r3, lo(0x8000000d)
|
l.ori r3, r3, lo(0x8000000d)
|
l.nop 0x2
|
l.nop 0x2
|
l.ori r3, r0, 0
|
l.ori r3, r0, 0
|
l.nop 0x1
|
l.nop 0x1
|
|
|
_fail:
|
_fail:
|
l.ori r3, r0, 1
|
l.ori r3, r0, 1
|
l.nop 0x1
|
l.nop 0x1
|
|
|
