/*
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/*
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* OR1200 Data cache test
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* OR1200 Data cache test
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* Writes and checks various values in places to exercise data cache line
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* Writes and checks various values in places to exercise data cache line
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* swaps.
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* swaps.
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*
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*
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* Change LOOPS define to alter length of test (2048 is OK size)
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* Change LOOPS define to alter length of test (2048 is OK size)
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*/
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*/
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#include "cpu-utils.h"
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#include "cpu-utils.h"
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#include "lib-utils.h"
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#include "lib-utils.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#define LOOPS 64
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#define LOOPS 64
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#define WORD_STRIDE 8
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#define WORD_STRIDE 8
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// Memory area to test at
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#define TEST_BASE 0x600000 /* 6MB */
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unsigned long int my_lfsr;
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unsigned long int my_lfsr;
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unsigned long int next_rand()
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unsigned long int next_rand()
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{
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{
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my_lfsr = (my_lfsr >> 1) ^ (unsigned long int)((0 - (my_lfsr & 1u)) & 0xd0000001u);
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my_lfsr = (my_lfsr >> 1) ^ (unsigned long int)((0 - (my_lfsr & 1u)) & 0xd0000001u);
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return my_lfsr;
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return my_lfsr;
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}
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}
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int
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int
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main()
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main()
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{
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{
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// Check data cache is present and enabled
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// Check data cache is present and enabled
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if (!(mfspr(SPR_UPR)& SPR_UPR_DCP) | !(mfspr(SPR_SR) & SPR_SR_DCE))
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if (!(mfspr(SPR_UPR)& SPR_UPR_DCP) | !(mfspr(SPR_SR) & SPR_SR_DCE))
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{
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{
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// Not really a pass, but not really a fail, either.
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// Not really a pass, but not really a fail, either.
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report(0x8000000d);
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report(0x8000000d);
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return 0;
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return 0;
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}
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}
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volatile char* ptr = (volatile char*) 0xe00000;
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volatile char* ptr = (volatile char*) TEST_BASE;
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int i;
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int i;
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ptr[0] = 0xab;
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ptr[0] = 0xab;
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ptr[4096] = 0xcd;
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ptr[4096] = 0xcd;
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ptr[8192] = 0xef;
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ptr[8192] = 0xef;
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report(ptr[0]);
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report(ptr[0]);
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report(ptr[4096]);
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report(ptr[4096]);
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report(ptr[8192]);
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report(ptr[8192]);
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// If cache is write back, then test flush and writeback functionalities
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// If cache is write back, then test flush and writeback functionalities
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// Check cache write stategy bit (CWS) for write back
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// Check cache write stategy bit (CWS) for write back
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if (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS)
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if (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS)
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{
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{
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// TODO: Check flush and write back actually work by mapping the same
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// TODO: Check flush and write back actually work by mapping the same
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// space as CI through DMMU. For now the following will aid checking on
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// space as CI through DMMU. For now the following will aid checking on
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// waveform.
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// waveform.
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volatile int * test_addr = (int *) 0xefaa10;
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volatile int * test_addr = (int *) 0xefaa10;
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// Fill some lines with data
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// Fill some lines with data
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for (i=0;i<64;i++)
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for (i=0;i<64;i++)
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test_addr[i] = 1+(i<<i)/(i+1);
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test_addr[i] = 1+(i<<i)/(i+1);
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// Flush the lines
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// Flush the lines
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int spr_addr = SPR_DCBFR;
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int spr_addr = SPR_DCBFR;
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for (i=0;i<16;i++)
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for (i=0;i<16;i++)
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asm("l.mtspr\t\t%0,%1,0": : "r" (spr_addr), "r" (test_addr+(i*4)));
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asm("l.mtspr\t\t%0,%1,0": : "r" (spr_addr), "r" (test_addr+(i*4)));
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// Check the data
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// Check the data
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for (i=0;i<64;i++)
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for (i=0;i<64;i++)
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if (test_addr[i] != (1+(i<<i)/(i+1)))
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if (test_addr[i] != (1+(i<<i)/(i+1)))
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return i;
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return i;
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// Fill some lines with data
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// Fill some lines with data
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for (i=0;i<64;i++)
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for (i=0;i<64;i++)
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test_addr[i] = ~i;
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test_addr[i] = ~i;
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// Force writeback of the lines
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// Force writeback of the lines
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spr_addr = SPR_DCBWR;
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spr_addr = SPR_DCBWR;
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for (i=0;i<16;i++)
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for (i=0;i<16;i++)
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asm("l.mtspr\t\t%0,%1,0": : "r" (spr_addr), "r" (test_addr+(i*4)));
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asm("l.mtspr\t\t%0,%1,0": : "r" (spr_addr), "r" (test_addr+(i*4)));
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// Check the data
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// Check the data
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for (i=0;i<64;i++)
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for (i=0;i<64;i++)
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if (test_addr[i] != ~i)
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if (test_addr[i] != ~i)
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return ~i;
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return ~i;
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}
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}
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// Now generate some random numbers, write them in in strides that should
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// Now generate some random numbers, write them in in strides that should
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// execercise the cache's line reloading/storing mechanism.
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// execercise the cache's line reloading/storing mechanism.
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// init LFSR
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// init LFSR
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my_lfsr = RAND_LFSR_SEED;
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my_lfsr = RAND_LFSR_SEED;
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volatile unsigned long int *lptr = (volatile unsigned long int*) 0xa00000;
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volatile unsigned long int *lptr = (volatile unsigned long int*) TEST_BASE;
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for(i=0;i<LOOPS;i++)
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for(i=0;i<LOOPS;i++)
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{
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{
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lptr[(i*WORD_STRIDE)-1] = next_rand();
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lptr[(i*WORD_STRIDE)-1] = next_rand();
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lptr[(i*WORD_STRIDE)+0] = next_rand();
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lptr[(i*WORD_STRIDE)+0] = next_rand();
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lptr[(i*WORD_STRIDE)+1] = next_rand();
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lptr[(i*WORD_STRIDE)+1] = next_rand();
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lptr[(i*WORD_STRIDE)+2] = next_rand();
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lptr[(i*WORD_STRIDE)+2] = next_rand();
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lptr[(i*WORD_STRIDE)+3] = next_rand();
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lptr[(i*WORD_STRIDE)+3] = next_rand();
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lptr[(i*WORD_STRIDE)+4] = next_rand();
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lptr[(i*WORD_STRIDE)+4] = next_rand();
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}
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}
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report(next_rand());
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report(next_rand());
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#define CHECK(off) expected=next_rand(); \
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#define CHECK(off) expected=next_rand(); \
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if (lptr[(i*WORD_STRIDE)+off] != expected)
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if (lptr[(i*WORD_STRIDE)+off] != expected)
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#define FAILURE(x,y) report(y); report(expected); \
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#define FAILURE(x,y) report(y); report(expected); \
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report(lptr[(i*WORD_STRIDE)+y]);exit(0xbaaaaaad)
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report(lptr[(i*WORD_STRIDE)+y]);exit(0xbaaaaaad)
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// reset lfsr seed
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// reset lfsr seed
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my_lfsr = RAND_LFSR_SEED;
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my_lfsr = RAND_LFSR_SEED;
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unsigned long int expected;
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unsigned long int expected;
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for (i=0;i<LOOPS;i++)
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for (i=0;i<LOOPS;i++)
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{
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{
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report(i);
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report(i);
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CHECK(-1)
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CHECK(-1)
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{
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{
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FAILURE(i,-1);
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FAILURE(i,-1);
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}
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}
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CHECK(0)
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CHECK(0)
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{
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{
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FAILURE(i,0);
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FAILURE(i,0);
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}
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}
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CHECK(1)
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CHECK(1)
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{
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{
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FAILURE(i,1);
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FAILURE(i,1);
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}
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}
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CHECK(2)
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CHECK(2)
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{
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{
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FAILURE(i,2);
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FAILURE(i,2);
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}
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}
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CHECK(3)
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CHECK(3)
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{
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{
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FAILURE(i,3);
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FAILURE(i,3);
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}
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}
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CHECK(4)
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CHECK(4)
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{
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{
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FAILURE(i,4);
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FAILURE(i,4);
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}
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}
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}
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}
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report(next_rand());
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report(next_rand());
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report(0x8000000d);
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report(0x8000000d);
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exit(0);
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exit(0);
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}
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}
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