/*
|
/*
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OR1200 Find First/Last '1' Test
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OR1200 Find First/Last '1' Test
|
|
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Checks l.ff1 and l.fl1 outputs for every bit position
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Checks l.ff1 and l.fl1 outputs for every bit position
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|
Julius Baxter, julius.baxter@orsoc.se
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Julius Baxter, julius.baxter@orsoc.se
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|
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*/
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*/
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
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//// ////
|
//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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#include "or1200-defines.h"
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#include "or1200-defines.h"
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// Check MAC unit is enabled before trying to run this test
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// Check MAC unit is enabled before trying to run this test
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#ifndef OR1200_IMPL_ALU_FFL1
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#ifndef OR1200_IMPL_ALU_FFL1
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# error
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# error
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# error Find First/Last '1' isntructions not enabled.
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# error Find First/Last '1' isntructions not enabled.
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# error
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# error
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#endif
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#endif
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/* =================================================== [ exceptions ] === */
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/* =================================================== [ exceptions ] === */
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.section .vectors, "ax"
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.section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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.org 0x100
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.org 0x100
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l.movhi r0, 0
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l.movhi r0, 0
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/* Clear status register */
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/* Clear status register */
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l.ori r1, r0, SPR_SR_SM
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l.ori r1, r0, SPR_SR_SM
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l.mtspr r0, r1, SPR_SR
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l.mtspr r0, r1, SPR_SR
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/* Clear timer */
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/* Clear timer */
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l.mtspr r0, r0, SPR_TTMR
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l.mtspr r0, r0, SPR_TTMR
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|
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/* Jump to program initialisation code */
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/* Jump to program initialisation code */
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.global _start
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.global _start
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l.movhi r4, hi(_start)
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l.movhi r4, hi(_start)
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l.ori r4, r4, lo(_start)
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l.ori r4, r4, lo(_start)
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l.jr r4
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l.jr r4
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l.nop
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l.nop
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/* =================================================== [ text ] === */
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/* =================================================== [ text ] === */
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.section .text
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.section .text
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/* =================================================== [ start ] === */
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/* =================================================== [ start ] === */
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.global _start
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.global _start
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_start:
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_start:
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/* Instruction cache enable */
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.sfeq r26,r0
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l.bf .L8
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l.bf .L8
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l.nop
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l.nop
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/* Disable IC */
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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/* Establish cache block size
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If BS=0, 16;
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If BS=0, 16;
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If BS=1, 32;
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If BS=1, 32;
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r14 contain block size
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r14 contain block size
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*/
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.ori r30,r0,16
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l.sll r14,r30,r28
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l.sll r14,r30,r28
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/* Establish number of cache sets
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/* Establish number of cache sets
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r16 contains number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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r28 contains log(# of cache sets)
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*/
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.ori r30,r0,1
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l.sll r16,r30,r28
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l.sll r16,r30,r28
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/* Invalidate IC */
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/* Invalidate IC */
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l.addi r6,r0,0
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l.addi r6,r0,0
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l.sll r5,r14,r28
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l.sll r5,r14,r28
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.L7:
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.sfne r6,r5
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l.bf .L7
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l.bf .L7
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l.add r6,r6,r14
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l.add r6,r6,r14
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/* Enable IC */
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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.L8:
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.L8:
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/* Data cache enable */
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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l.sfeq r26,r0
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l.bf .L10
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l.bf .L10
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l.nop
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l.nop
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/* Disable DC */
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/* Disable DC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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/* Establish cache block size
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If BS=0, 16;
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If BS=0, 16;
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If BS=1, 32;
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If BS=1, 32;
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r14 contain block size
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r14 contain block size
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*/
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.mfspr r24,r0,SPR_DCCFGR
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.andi r26,r24,SPR_DCCFGR_CBS
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l.srli r28,r26,7
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.ori r30,r0,16
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l.sll r14,r30,r28
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l.sll r14,r30,r28
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/* Establish number of cache sets
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/* Establish number of cache sets
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r16 contains number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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r28 contains log(# of cache sets)
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*/
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*/
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.andi r26,r24,SPR_DCCFGR_NCS
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l.srli r28,r26,3
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.ori r30,r0,1
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l.sll r16,r30,r28
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l.sll r16,r30,r28
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/* Invalidate DC */
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/* Invalidate DC */
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l.addi r6,r0,0
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l.addi r6,r0,0
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l.sll r5,r14,r28
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l.sll r5,r14,r28
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.L9:
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.L9:
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l.mtspr r0,r6,SPR_DCBIR
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l.mtspr r0,r6,SPR_DCBIR
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l.sfne r6,r5
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l.sfne r6,r5
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l.bf .L9
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l.bf .L9
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l.add r6,r6,r14
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l.add r6,r6,r14
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/* Enable DC */
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/* Enable DC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_DCE
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l.ori r6,r6,SPR_SR_DCE
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l.mtspr r0,r6,SPR_SR
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l.mtspr r0,r6,SPR_SR
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.L10:
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.L10:
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// Kick off test
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// Kick off test
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l.jal _main
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l.jal _main
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l.nop
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l.nop
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/* =================================================== [ main ] === */
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/* =================================================== [ main ] === */
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|
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.global _main
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.global _main
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_main:
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_main:
|
l.movhi r3, 0
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l.movhi r3, 0
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l.movhi r4, 0 // Bit we're checking works
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l.movhi r4, 0 // Bit we're checking works
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l.movhi r5, 0
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l.movhi r5, 0
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l.ori r6, r0, 32
|
l.ori r6, r0, 32
|
l.movhi r7, 0 // Register we'll put a value in to check with l.ff1
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l.movhi r7, 0 // Register we'll put a value in to check with l.ff1
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|
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#define REPORT(reg) l.or r3, reg, r0 ; \
|
#define REPORT(reg) l.or r3, reg, r0 ; \
|
l.nop 0x2
|
l.nop 0x2
|
|
|
|
|
ff1_loop:
|
ff1_loop:
|
// Set a loop going, creating a register with a '1' in a known position
|
// Set a loop going, creating a register with a '1' in a known position
|
// and checking the output of the l.ff1
|
// and checking the output of the l.ff1
|
l.ori r7, r0, 1 // Put 1 in bit 0
|
l.ori r7, r0, 1 // Put 1 in bit 0
|
l.sll r7, r7, r4 // Shift '1' by r4
|
l.sll r7, r7, r4 // Shift '1' by r4
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REPORT(r7) // Report value
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REPORT(r7) // Report value
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l.ff1 r5, r7 // Do Find First '1' op
|
l.ff1 r5, r7 // Do Find First '1' op
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l.fl1 r8, r7 // Do Find Last '1' op
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l.fl1 r8, r7 // Do Find Last '1' op
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REPORT(r5) // Report value
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REPORT(r5) // Report value
|
REPORT(r8) // Report value
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REPORT(r8) // Report value
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l.addi r4, r4, 1 // Increment bit we're checking (will also be
|
l.addi r4, r4, 1 // Increment bit we're checking (will also be
|
// result from l.ff1)
|
// result from l.ff1)
|
REPORT(r4) // Report value
|
REPORT(r4) // Report value
|
l.sfne r5, r4 // r5 should = r4
|
l.sfne r5, r4 // r5 should = r4
|
l.bf ff1_error
|
l.bf ff1_error
|
l.sfne r8, r4 // r8 should = r4
|
l.sfne r8, r4 // r8 should = r4
|
l.bf fl1_error
|
l.bf fl1_error
|
l.sfne r6, r4 // Check if loop is finished
|
l.sfne r6, r4 // Check if loop is finished
|
l.bf ff1_loop // Keep checking
|
l.bf ff1_loop // Keep checking
|
l.nop
|
l.nop
|
l.j ffl1_test2 // All OK, next test
|
l.j ffl1_test2 // All OK, next test
|
l.nop
|
l.nop
|
|
|
ffl1_test2:
|
ffl1_test2:
|
// Try 3 values - all '0', all '1' and a block of values in between
|
// Try 3 values - all '0', all '1' and a block of values in between
|
l.movhi r4, 0
|
l.movhi r4, 0
|
l.movhi r5, 0xffff
|
l.movhi r5, 0xffff
|
l.ori r5, r5, 0xffff
|
l.ori r5, r5, 0xffff
|
l.movhi r6, 0x00ff
|
l.movhi r6, 0x00ff
|
l.ori r6, r6, 0xff00
|
l.ori r6, r6, 0xff00
|
// Test '0'
|
// Test '0'
|
REPORT(r4)
|
REPORT(r4)
|
l.ff1 r7, r4
|
l.ff1 r7, r4
|
l.fl1 r8, r4
|
l.fl1 r8, r4
|
REPORT(r7)
|
REPORT(r7)
|
REPORT(r8)
|
REPORT(r8)
|
l.sfnei r7, 0
|
l.sfnei r7, 0
|
l.bf ff1_error
|
l.bf ff1_error
|
l.sfnei r8, 0
|
l.sfnei r8, 0
|
l.bf fl1_error
|
l.bf fl1_error
|
|
|
// Test '0xffffffff'
|
// Test '0xffffffff'
|
REPORT(r5)
|
REPORT(r5)
|
l.ff1 r7, r5
|
l.ff1 r7, r5
|
l.fl1 r8, r5
|
l.fl1 r8, r5
|
REPORT(r7)
|
REPORT(r7)
|
REPORT(r8)
|
REPORT(r8)
|
l.sfnei r7, 1
|
l.sfnei r7, 1
|
l.bf ff1_error
|
l.bf ff1_error
|
l.sfnei r8, 32
|
l.sfnei r8, 32
|
l.bf fl1_error
|
l.bf fl1_error
|
|
|
// Test '0x00ffff00'
|
// Test '0x00ffff00'
|
REPORT(r6)
|
REPORT(r6)
|
l.ff1 r7, r6
|
l.ff1 r7, r6
|
l.fl1 r8, r6
|
l.fl1 r8, r6
|
REPORT(r7)
|
REPORT(r7)
|
REPORT(r8)
|
REPORT(r8)
|
l.sfnei r7, 9
|
l.sfnei r7, 9
|
l.bf ff1_error
|
l.bf ff1_error
|
l.sfnei r8, 24
|
l.sfnei r8, 24
|
l.bf fl1_error
|
l.bf fl1_error
|
l.nop
|
l.nop
|
l.j ffl1_ok // Tests OK
|
l.j ffl1_ok // Tests OK
|
|
|
ff1_error:
|
ff1_error:
|
l.movhi r3, hi(0xbaaadff1)
|
l.movhi r3, hi(0xbaaadff1)
|
l.ori r3, r3, lo(0xbaaadff1)
|
l.ori r3, r3, lo(0xbaaadff1)
|
l.nop 0x1
|
l.nop 0x1
|
|
|
|
|
fl1_error:
|
fl1_error:
|
l.movhi r3, hi(0xbaaadf11)
|
l.movhi r3, hi(0xbaaadf11)
|
l.ori r3, r3, lo(0xbaaadf11)
|
l.ori r3, r3, lo(0xbaaadf11)
|
l.nop 0x1
|
l.nop 0x1
|
|
|
|
|
ffl1_ok:
|
ffl1_ok:
|
|
|
l.movhi r3, hi(0x8000000d)
|
l.movhi r3, hi(0x8000000d)
|
l.ori r3, r3, lo(0x8000000d)
|
l.ori r3, r3, lo(0x8000000d)
|
|
l.nop 0x2 /* Report */
|
|
l.ori r3, r0, 0 /* Return 0 */
|
l.nop 0x1
|
l.nop 0x1
|
|
|