#include "board.h"
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#include "board.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "or32-utils.h"
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#include "cpu-utils.h"
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#include "simple-spi.h"
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#include "simple-spi.h"
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#include "int.h"
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#include "int.h"
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#include "simple-spi.h"
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#include "simple-spi.h"
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#include "design-defines.h"
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#include "orpsoc-defines.h"
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// Detect which of the SPI cores are enabled, tailor the test for that
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// Detect which of the SPI cores are enabled, tailor the test for that
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#ifndef SPI1
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#ifndef SPI1
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# ifndef SPI2
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# ifndef SPI2
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# error
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# error
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# error No SPI cores to test with! Please enable SPI1 and/or SPI2
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# error No SPI cores to test with! Please enable SPI1 and/or SPI2
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# error
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# error
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# else
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# else
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# define NUM_SPI_CORES 1
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# define NUM_SPI_CORES 1
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# define FIRST_SPI_CORE 2
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# define FIRST_SPI_CORE 2
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# endif
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# endif
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#else
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#else
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# ifdef SPI2
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# ifdef SPI2
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# define NUM_SPI_CORES 2
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# define NUM_SPI_CORES 2
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# define FIRST_SPI_CORE 1
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# define FIRST_SPI_CORE 1
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# else
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# else
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# define NUM_SPI_CORES 1
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# define NUM_SPI_CORES 1
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# define FIRST_SPI_CORE 1
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# define FIRST_SPI_CORE 1
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# endif
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# endif
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#endif
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#endif
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struct spi_int_data{
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struct spi_int_data{
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unsigned long data;
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unsigned long data;
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char retrieved;
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char retrieved;
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};
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};
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volatile struct spi_int_data spi1_int_data;
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volatile struct spi_int_data spi1_int_data;
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void spi1_int_handler(void);
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void spi1_int_handler(void);
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void spi1_int_handler(void)
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void spi1_int_handler(void)
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{
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{
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// Should have recieved 4 bytes, let's pull them off and put them into
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// Should have recieved 4 bytes, let's pull them off and put them into
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// the data struct
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// the data struct
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char* spi1_data = (char*) &spi1_int_data.data;
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char* spi1_data = (char*) &spi1_int_data.data;
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int i;
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int i;
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for (i=0;i<4;i++)
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for (i=0;i<4;i++)
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{
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{
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while (!spi_core_data_avail(1));
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while (!spi_core_data_avail(1));
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spi1_data[i] = spi_core_read_data(1);
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spi1_data[i] = spi_core_read_data(1);
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}
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}
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spi1_int_data.retrieved = 1;
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spi1_int_data.retrieved = 1;
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// Clear the interrupt flag
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// Clear the interrupt flag
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spi_core_interrupt_flag_clear(1);
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spi_core_interrupt_flag_clear(1);
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return;
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return;
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}
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}
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volatile struct spi_int_data spi2_int_data;
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volatile struct spi_int_data spi2_int_data;
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void spi2_int_handler(void);
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void spi2_int_handler(void);
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void spi2_int_handler(void)
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void spi2_int_handler(void)
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{
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{
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// Should have recieved 4 bytes, let's pull them off and put them into
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// Should have recieved 4 bytes, let's pull them off and put them into
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// the data struct
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// the data struct
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char* spi2_data = (char*) &spi2_int_data.data;
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char* spi2_data = (char*) &spi2_int_data.data;
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int i;
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int i;
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for (i=0;i<4;i++)
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for (i=0;i<4;i++)
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{
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{
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while (!spi_core_data_avail(2));
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while (!spi_core_data_avail(2));
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spi2_data[i] = spi_core_read_data(2);
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spi2_data[i] = spi_core_read_data(2);
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}
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}
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spi2_int_data.retrieved = 1;
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spi2_int_data.retrieved = 1;
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// Clear the interrupt flag
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// Clear the interrupt flag
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spi_core_interrupt_flag_clear(2);
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spi_core_interrupt_flag_clear(2);
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return;
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return;
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}
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}
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int main()
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int main()
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{
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{
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int spi_master;
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int spi_master;
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int spi_slave = 2;
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int spi_slave = 2;
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int i,j;
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int i,j;
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spi1_int_data.retrieved = 0;
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spi1_int_data.retrieved = 0;
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spi2_int_data.retrieved = 0;
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spi2_int_data.retrieved = 0;
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int_init();
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int_init();
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/* Install SPI core 1 interrupt handler */
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/* Install SPI core 1 interrupt handler */
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int_add(SPI1_IRQ, spi1_int_handler, 0);
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int_add(SPI1_IRQ, spi1_int_handler, 0);
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/* Install SPI core 2 interrupt handler */
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/* Install SPI core 2 interrupt handler */
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int_add(SPI2_IRQ, spi2_int_handler, 0);
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int_add(SPI2_IRQ, spi2_int_handler, 0);
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/* Enable interrupts in supervisor register */
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/* Enable interrupts in supervisor register */
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mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
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mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
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for (spi_master = FIRST_SPI_CORE;
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for (spi_master = FIRST_SPI_CORE;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master++)
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spi_master++)
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{
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{
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// Init master -- disable it first
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// Init master -- disable it first
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spi_core_disable(spi_master);
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spi_core_disable(spi_master);
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// polarity, phase, dividers :
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// polarity, phase, dividers :
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spi_core_clock_setup(spi_master, 0, 0, 0, 0);
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spi_core_clock_setup(spi_master, 0, 0, 0, 0);
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// Set number of transfers per interrupt to 4
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// Set number of transfers per interrupt to 4
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spi_core_set_int_count(spi_master, SIMPLESPI_SPER_ICNT_FOUR);
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spi_core_set_int_count(spi_master, SIMPLESPI_SPER_ICNT_FOUR);
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// Enable interrupts on the core
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// Enable interrupts on the core
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spi_core_interrupt_enable(spi_master);
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spi_core_interrupt_enable(spi_master);
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// Now enable core after configuration, before using it
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// Now enable core after configuration, before using it
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spi_core_enable(spi_master);
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spi_core_enable(spi_master);
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}
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}
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// Play with the slaves
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// Play with the slaves
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for(i=0;i<16;i++)
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for(i=0;i<16;i++)
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{
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{
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for (spi_master = FIRST_SPI_CORE;
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for (spi_master = FIRST_SPI_CORE;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master++)
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spi_master++)
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{
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{
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spi_slave = i % 3;
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spi_slave = i % 3;
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spi_slave = (1 << spi_slave);
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spi_slave = (1 << spi_slave);
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for(j=0;j<4;j++)
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for(j=0;j<4;j++)
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{
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{
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// Select a slave on SPI bus
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// Select a slave on SPI bus
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spi_core_slave_select(spi_master, spi_slave);
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spi_core_slave_select(spi_master, spi_slave);
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// Do a SPI bus transaction - we're only reading
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// Do a SPI bus transaction - we're only reading
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// coming back
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// coming back
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while (!spi_core_write_avail(spi_master));
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while (!spi_core_write_avail(spi_master));
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spi_core_write_data(spi_master, (i&0xff));
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spi_core_write_data(spi_master, (i&0xff));
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// Deselect all masters
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// Deselect all masters
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spi_core_slave_select(spi_master, 0);
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spi_core_slave_select(spi_master, 0);
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}
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}
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// Wait for the interrupt to retrieve the data and signal this
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// Wait for the interrupt to retrieve the data and signal this
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if (spi_master == 1){
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if (spi_master == 1){
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while (!spi1_int_data.retrieved);
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while (!spi1_int_data.retrieved);
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// Now report it
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// Now report it
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report(spi1_int_data.data);
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report(spi1_int_data.data);
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// And reset the retrieved bit
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// And reset the retrieved bit
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spi1_int_data.retrieved = 0;
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spi1_int_data.retrieved = 0;
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}
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}
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if (spi_master == 2){
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if (spi_master == 2){
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while (!spi2_int_data.retrieved);
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while (!spi2_int_data.retrieved);
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// Now report it
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// Now report it
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report(spi2_int_data.data);
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report(spi2_int_data.data);
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// And reset the retrieved bit
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// And reset the retrieved bit
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spi2_int_data.retrieved = 0;
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spi2_int_data.retrieved = 0;
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}
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}
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}
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}
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}
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}
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exit(0x8000000d);
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exit(0x8000000d);
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}
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}
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