/*
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/*
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SPI controller simple test
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SPI controller simple test
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Do some reads from the SPI slaves. Select a different slave each loop
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Do some reads from the SPI slaves. Select a different slave each loop
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and does a read and reports the value.
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and does a read and reports the value.
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Nothing much actually gets tested here.
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Nothing much actually gets tested here.
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Ensure the slave selects for the spi are enabled in design-defines.v
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Ensure the slave selects for the spi are enabled in orpsoc-defines.v
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*/
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*/
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#include "or32-utils.h"
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#include "cpu-utils.h"
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#include "simple-spi.h"
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#include "simple-spi.h"
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#include "design-defines.h"
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#include "orpsoc-defines.h"
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// Detect which of the SPI cores are enabled, tailor the test for that
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// Detect which of the SPI cores are enabled, tailor the test for that
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#ifndef SPI1
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#ifndef SPI1
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# ifndef SPI2
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# ifndef SPI2
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# error
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# error
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# error No SPI cores to test with! Please enable SPI1 and/or SPI2
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# error No SPI cores to test with! Please enable SPI1 and/or SPI2
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# error
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# error
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# else
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# else
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# define NUM_SPI_CORES 1
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# define NUM_SPI_CORES 1
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# define FIRST_SPI_CORE 2
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# define FIRST_SPI_CORE 2
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# endif
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# endif
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#else
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#else
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# ifdef SPI2
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# ifdef SPI2
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# define NUM_SPI_CORES 2
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# define NUM_SPI_CORES 2
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# define FIRST_SPI_CORE 1
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# define FIRST_SPI_CORE 1
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# else
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# else
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# define NUM_SPI_CORES 1
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# define NUM_SPI_CORES 1
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# define FIRST_SPI_CORE 1
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# define FIRST_SPI_CORE 1
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# endif
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# endif
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#endif
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#endif
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int main()
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int main()
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{
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{
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int spi_master = FIRST_SPI_CORE;
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int spi_master = FIRST_SPI_CORE;
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int spi_slave = 2;
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int spi_slave = 2;
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int i;
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int i;
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// Init the masters
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// Init the masters
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for (spi_master = FIRST_SPI_CORE;
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for (spi_master = FIRST_SPI_CORE;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master++)
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spi_master++)
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{
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{
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spi_core_clock_setup(spi_master, 0, 0, 2, 0);
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spi_core_clock_setup(spi_master, 0, 0, 2, 0);
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spi_core_enable(spi_master);
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spi_core_enable(spi_master);
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}
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}
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// Play with the slaves
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// Play with the slaves
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for(i=0;i<64;i++)
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for(i=0;i<64;i++)
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{
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{
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for (spi_master = FIRST_SPI_CORE;
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for (spi_master = FIRST_SPI_CORE;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master < FIRST_SPI_CORE+ NUM_SPI_CORES;
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spi_master++)
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spi_master++)
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{
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{
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spi_slave = i % 3;
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spi_slave = i % 3;
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spi_slave = (1 << spi_slave);
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spi_slave = (1 << spi_slave);
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// Select slave on SPI bus
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// Select slave on SPI bus
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spi_core_slave_select(spi_master, spi_slave);
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spi_core_slave_select(spi_master, spi_slave);
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// Do a SPI bus transaction - we're only interested in the read data
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// Do a SPI bus transaction - we're only interested in the read data
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// coming back
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// coming back
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while (!spi_core_write_avail(spi_master));
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while (!spi_core_write_avail(spi_master));
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spi_core_write_data(spi_master, (i&0xff));
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spi_core_write_data(spi_master, (i&0xff));
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while (!spi_core_data_avail(spi_master));
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while (!spi_core_data_avail(spi_master));
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report(spi_core_read_data(spi_master));
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report(spi_core_read_data(spi_master));
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// Deselect slaves
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// Deselect slaves
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spi_core_slave_select(spi_master, 0);
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spi_core_slave_select(spi_master, 0);
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}
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}
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}
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}
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exit(0x8000000d);
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exit(0x8000000d);
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}
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}
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